// cs_buf.v v1 Frank Berndt
// cs buffers;
// :set tabstop=4

module cs_buf (
	clk, ra, dout, wa, di, wen
);
	input clk;				// sync clock;
	input [4:0] ra;			// read address;
	output [31:0] dout;		// read data;
	input [4:0] wa;			// write address;
	input [31:0] di;		// write data;
	input wen;				// write enable;

	// instantiate NEC model;
	// 32x32 1R1W port SRAM;
	// A port is write, B port is read;

	wire csa;		// enable port A write;
	wire csb;		// enable port B read;

	assign csa = ~wen;
	assign csb = 1'b0;

	WBSRAMDHDWR32W32C2 ram (
		.DO31(dout[31]),
		.DO30(dout[30]),
		.DO29(dout[29]),
		.DO28(dout[28]),
		.DO27(dout[27]),
		.DO26(dout[26]),
		.DO25(dout[25]),
		.DO24(dout[24]),
		.DO23(dout[23]),
		.DO22(dout[22]),
		.DO21(dout[21]),
		.DO20(dout[20]),
		.DO19(dout[19]),
		.DO18(dout[18]),
		.DO17(dout[17]),
		.DO16(dout[16]),
		.DO15(dout[15]),
		.DO14(dout[14]),
		.DO13(dout[13]),
		.DO12(dout[12]),
		.DO11(dout[11]),
		.DO10(dout[10]),
		.DO9(dout[9]),
		.DO8(dout[8]),
		.DO7(dout[7]),
		.DO6(dout[6]),
		.DO5(dout[5]),
		.DO4(dout[4]),
		.DO3(dout[3]),
		.DO2(dout[2]),
		.DO1(dout[1]),
		.DO0(dout[0]),
		.DI31(di[31]),
		.DI30(di[30]),
		.DI29(di[29]),
		.DI28(di[28]),
		.DI27(di[27]),
		.DI26(di[26]),
		.DI25(di[25]),
		.DI24(di[24]),
		.DI23(di[23]),
		.DI22(di[22]),
		.DI21(di[21]),
		.DI20(di[20]),
		.DI19(di[19]),
		.DI18(di[18]),
		.DI17(di[17]),
		.DI16(di[16]),
		.DI15(di[15]),
		.DI14(di[14]),
		.DI13(di[13]),
		.DI12(di[12]),
		.DI11(di[11]),
		.DI10(di[10]),
		.DI9(di[9]),
		.DI8(di[8]),
		.DI7(di[7]),
		.DI6(di[6]),
		.DI5(di[5]),
		.DI4(di[4]),
		.DI3(di[3]),
		.DI2(di[2]),
		.DI1(di[1]),
		.DI0(di[0]),
		.AA4(wa[4]),
		.AA3(wa[3]),
		.AA2(wa[2]),
		.AA1(wa[1]),
		.AA0(wa[0]),
		.AB4(ra[4]),
		.AB3(ra[3]),
		.AB2(ra[2]),
		.AB1(ra[1]),
		.AB0(ra[0]),
		.CSA(csa),
		.CSB(csb),
		.BEA(clk),
		.BEB(clk),
		.TBEA(1'b0),
		.TBEB(1'b0),
		.TEST(1'b0),
		.BUB(1'b1)
	);

endmodule