// $Id: sudp_reg.v,v 1.3 2003/01/23 00:06:34 berndt Exp $

module sudp_reg (clk,d,q);

input clk;
input [31:0] d;

output [31:0] q;
reg [31:0] q;

always @(posedge clk)
	q <= d;

endmodule  //  sudp_reg