// cpu.vh v1 Frank Berndt
// cpu definitions;

// syscmd[] encoding;
// syscmd[4] 0=address, 1=data phase;
// syscmd[3:0] are phase dependent;

// ssycmd[4] 0 command identifier;
// syscmd[3] 0=read, 1=write;
// syscmd[2..0] see CPU_SIZE below;

// syscmd[4] 1 data/response identifier;
// syscmd[3] 0=last data, 1=more data;
// syscmd[2] 0=response data, 1=not;
// syscmd[1] 0=no error, 1=error;
// syscmd[0] reserved;

`define	SYS_CMD_SREAD	5'b00000	// single word read;
`define	SYS_CMD_SWRITE	5'b01000	// single word write;
`define	SYS_CMD_BREAD	5'b00100	// block read;
`define	SYS_CMD_BWRITE	5'b01100	// block write;

`define	SYS_CMD_DATA	5'b11000	// data phase;
`define	SYS_CMD_EOD	5'b10000	// last data item;

// cpu single/block/block read/write request sizes;
// syscmd[2:0] during address phase;

`define	CPU_SIZE_1	2'b00		// byte;
`define	CPU_SIZE_2	2'b01		// half;
`define	CPU_SIZE_3	2'b10
`define	CPU_SIZE_4	2'b11		// word;

`define	CPU_SIZE_8	2'b00		// double-word;
`define	CPU_SIZE_16	2'b01		// 16-byte dcache;
`define	CPU_SIZE_32	2'b10		// 32-byte icache;
`define	CPU_SIZE_RSVD	2'b11		// reserved;

// hard cpu limits;
// exceeding these limits will panic the simulator;

`define	CPU_RDY_TIMEOUT	625	// EOK ready timeout;
`define	CPU_RSP_TIMEOUT	625	// read response timeout;

// interrupt bits;

`define	INTR_RCP	0	// rcp interupt;
`define	INTR_DEV	1	// new devices interupt;
`define	INTR_BUT	2	// button interupt;
`define	INTR_ERR	3	// system error interupt;
`define	INTR_RSVD	4	// unused;