// Behavioral RAC
//
// Copyright 1994, Rambus Inc., All Rights Reserved
// CONFIDENTIAL INFORMATION - RAMBUS INC. PROPRIETARY
// 
// Data contained herein is proprietary information of Rambus Inc.
// which shall be treated confidentially and shall not be furnished to
// third parties or made public without prior written permission by
// Rambus Inc. Rambus Inc. does not convey any license under its
// patent, copyright or maskwork rights or any rights of others.
// 
// Data contained herein is preliminary. Rambus Inc. makes no warranties,
// expressed or implied, of functionality or suitability for any purpose.
// Rambus Inc. assumes no obligation to correct any errors contained
// herein or to advise any user of this text of any correction if such be
// made.

// This model supports only synchronous mode operation.  Testability, 
// PowerDown, or Stop clock features are not supported by this RAC model.

`timescale 1ns/1ns

module rac (
	 RData7, RData6, RData5, RData4, RData3, RData2, RData1, RData0, 
	 SynClk, SynClkFd,
 	 BusEnable, BISTFlag, SCANOut,
 	 BusCtrl, BusData,
 	 BusClk, BDSel, BCSel, BESel, RDSel, RCSel,
 	 Reset, 
	 TData7, TData6, TData5, TData4, TData3, TData2, TData1, TData0,
 	 Vref,
 	 BISTMode, IOSTMode, SCANMode, SCANClk, SCANEn, SCANIn, SynClkIn,
 	 CCtlEn, CCtlLd, CCtlI, CCtlPgm, PwrUp, ExtBE, StopR, StopT,
	 ByPass, ByPSel, rclkASIC, tclkASIC, PhStall);

output  [9:0]   RData7, RData6, RData5, RData4, RData3, RData2, RData1, RData0;
output          SynClk, SynClkFd;
output          BusEnable;
output          BISTFlag, SCANOut;
 
inout           BusCtrl;
inout   [8:0]   BusData;
input           BusClk;
input   [3:0]   BDSel, BCSel, BESel, RDSel, RCSel;
input           Reset;
input   [10:0]  TData7, TData6, TData5, TData4, TData3, TData2, TData1, TData0;
input           Vref;
input           BISTMode, IOSTMode, SCANMode, SCANClk, SCANEn, SCANIn,SynClkIn;
input           CCtlEn, CCtlLd;
input   [5:0]   CCtlI;
input           CCtlPgm, PwrUp, ExtBE, StopR, StopT;
input		ByPass, ByPSel, rclkASIC, tclkASIC, PhStall;

parameter	RAC_NUM = 99;

// Test Modes ( This is a temporary placeholder to get rid of "no fanin" warn )
wire		BISTFlag;
assign		BISTFlag = 1'b0;

wire		SCANOut;
assign		SCANOut = 1'b0;


// This code performs basic error checking and causes the rac to fail 
// disastrously upon detection.  It's just a reminder that it is only
// a very simple model.

reg	bhv_rac_error;
reg	error_checking_on;


initial	bhv_rac_error = 0;
initial	error_checking_on = 0;

always @( posedge BusClk )
    if ( error_checking_on & ~bhv_rac_error )
      begin
	if ( IOSTMode !== 1'b0 ) 
	  begin
	   $display("bhv_rac: BISTMode detected, not supported, stopping now!");
	   $display("bhv_rac: RAC# %d at time %d", RAC_NUM, $stime);
	   if ( RAC_NUM == 99 )
	       $display("bhv_rac:Override RAC_NUM parameter for sensible report.");
	   bhv_rac_error = 1;
	  end
	if ( BISTMode !== 1'b0 ) 
	  begin
	   $display("bhv_rac: BISTMode detected, not supported, stopping now!");
	   $display("bhv_rac: RAC# %d at time %d", RAC_NUM, $stime);
	   if ( RAC_NUM == 99 )
	       $display("bhv_rac:Override RAC_NUM parameter for sensible report.");
	   bhv_rac_error = 1;
	  end
	if ( SCANMode !== 1'b0 ) 
	  begin
	   $display("bhv_rac: SCANMode detected, not supported, stopping now!");
	   $display("bhv_rac: RAC# %d at time %d", RAC_NUM, $stime);
	   if ( RAC_NUM == 99 )
	       $display("bhv_rac:Override RAC_NUM parameter for sensible report.");
	   bhv_rac_error = 1;
	  end
	if ( SCANEn !== 1'b0 ) 
	  begin
	   $display("bhv_rac: SCANEn detected, not supported, stopping now!");
	   $display("bhv_rac: RAC# %d at time %d", RAC_NUM, $stime);
	   if ( RAC_NUM == 99 )
	       $display("bhv_rac:Override RAC_NUM parameter for sensible report.");
	   bhv_rac_error = 1;
	  end
	if (( ExtBE !== 1'b0 ) && ( Reset === 1'b0))
	  begin
	   $display("bhv_rac: ExtBE detected outside of Reset, stopping now!");
	   $display("bhv_rac: RAC# %d at time %d", RAC_NUM, $stime);
	   if ( RAC_NUM == 99 )
	       $display("bhv_rac:Override RAC_NUM parameter for sensible report.");
	   bhv_rac_error = 1;
	  end
	if ( StopR !== 1'b0 ) 
	  begin
	   $display("bhv_rac: StopR detected, not supported, stopping now!");
	   $display("bhv_rac: RAC# %d at time %d", RAC_NUM, $stime);
	   if ( RAC_NUM == 99 )
	       $display("bhv_rac:Override RAC_NUM parameter for sensible report.");
	   bhv_rac_error = 1;
	  end
	if ( StopT !== 1'b0 ) 
	  begin
	   $display("bhv_rac: StopT detected, not supported, stopping now!");
	   $display("bhv_rac: RAC# %d at time %d", RAC_NUM, $stime);
	   if ( RAC_NUM == 99 )
	       $display("bhv_rac:Override RAC_NUM parameter for sensible report.");
	   bhv_rac_error = 1;
	  end
	if ( ByPass !== 1'b0 ) 
	  begin
	   $display("bhv_rac: ByPass detected, not supported, stopping now!");
	   $display("bhv_rac: RAC# %d at time %d", RAC_NUM, $stime);
	   if ( RAC_NUM == 99 )
	       $display("bhv_rac:Override RAC_NUM parameter for sensible report.");
	   bhv_rac_error = 1;
	  end
	if ( PhStall !== 1'b0 ) 
	  begin
	   $display("bhv_rac: PhStall detected, not supported, stopping now!");
	   $display("bhv_rac: RAC# %d at time %d", RAC_NUM, $stime);
	   if ( RAC_NUM == 99 )
	       $display("bhv_rac:Override RAC_NUM parameter for sensible report.");
	   bhv_rac_error = 1;
	  end
      end

// The following code sets up the definition for the clocks.  A temporary
// flip-flop is used to divide the SynClkIn signal and passes that to the
// SynClkFd output.  This in turn is divided later to generate SynClk.

reg	SynClk, SynClkFd, SynClk_Quad_Gen;
reg	SynClk_Quad_Gen_sample, SynClk_Quad_Gen2;
reg	dll_on;
integer	i;

initial	dll_on = 0;
initial	i = 0;

wire	SynClk_wire, SynClkFd_wire, SynClk_Quad_Gen_wire;

assign	SynClk_wire = SynClk;
assign	SynClkFd_wire = SynClkFd;
assign	SynClk_Quad_Gen_wire = SynClk_Quad_Gen;


always @ ( negedge BusClk ) SynClk_Quad_Gen_sample = SynClkIn;

always @ ( posedge BusClk ) SynClk_Quad_Gen = SynClk_Quad_Gen_sample;

always @ ( negedge BusClk ) SynClk_Quad_Gen2 = SynClk_Quad_Gen;

always @ ( posedge BusClk )
  begin
    if ( dll_on & ~bhv_rac_error )
      SynClk = ~SynClk_Quad_Gen2;
    else if ( bhv_rac_error )
      SynClk = 1'bx;
    else
      SynClk = SynClk_wire;
  end

always @ ( posedge BusClk )
  begin
    if ( dll_on & ~bhv_rac_error )
      SynClkFd = ~SynClk_Quad_Gen2;
    else if ( bhv_rac_error )
      SynClkFd = 1'bx;
    else
      SynClkFd = SynClkFd_wire;
  end


always @( posedge BusClk )
  begin
    if ( PwrUp & ~dll_on )	// PwrUp started, clocks unstable until dll_on
      begin
	i = i + 1;
	if ( i == 20 )
	    dll_on = 1;
      end
    else if ( PwrUp & dll_on )	// PwrUp complete, clocks running
      begin
	i = 0;
      end
    else if ( bhv_rac_error )
      begin
	i = 0;
	dll_on = 0;
      end
    else if ( ~dll_on )	// non-run condition, RAC not PwrUp
      begin
	error_checking_on = 0;
	i = 0;
      end
    else 		// normal run condition, dll_on and !Reset
      begin
	error_checking_on = 1;
	i = 0;
      end
  end

// This ensures that a Reset condition clears out error checking.
always @ ( posedge Reset )
  begin
    bhv_rac_error = 0;
    error_checking_on = 0;
  end

always @ ( PwrUp )
  begin
    dll_on = 0;
    i = 0;
  end

// This routine helps to simulate the reset sequence that the
// real rac goes through.  Not exact, but similar and painful.
// This is modelled this way so that a simulation model that 
// switches between this RAC and a gate-level model may use 
// an identical reset procedure.

reg		CCtl_OK;
integer		CCtl_ctr_load;

initial	CCtl_OK =0;

always @ ( negedge SynClk )
  begin
    if ( CCtlLd & ~CCtlEn & (CCtl_ctr_load >= 32))
      begin
	if ( CCtlI === 'bx )
	  begin
            CCtl_OK = 0;
	  end
	else
	  begin
	    CCtl_OK = 1;
	  end
      end
    else if ( CCtlLd & CCtlEn & CCtl_OK )
      begin
        if ( CCtlPgm === 'bx )
	  begin
	    CCtl_OK = 0;
	  end
	else
	  begin
	    CCtl_OK = 1;
	  end
      end
  end

always @ ( posedge Reset )
  CCtl_ctr_load = 0;

always @ ( negedge SynClk )
  begin
    if ( Reset )
      CCtl_ctr_load = 0;
    else if ( CCtl_ctr_load < 40 )
      CCtl_ctr_load = CCtl_ctr_load + 1;
  end

wire	SynClk_QUAD1;
assign	SynClk_QUAD1 = ( ~SynClk_Quad_Gen_wire & ~SynClk_wire );

wire	SynClk_QUAD0;
assign	SynClk_QUAD0 = ( SynClk_Quad_Gen_wire & ~SynClk_wire );

// This code generates an internal clock that is used to center the data
// around the edges of BusClk.  This is for modelling purposes only.

reg	BusClk_Center;
integer	B_CLK_PERIOD;
time	TIME_DELAY;

initial TIME_DELAY = 0;
initial B_CLK_PERIOD = 0;

always @ (posedge BusClk)
begin
  if ( Reset )
    TIME_DELAY = $time;
  else if ( TIME_DELAY < $time )
    B_CLK_PERIOD = ( $time - TIME_DELAY ) / 4;
  else B_CLK_PERIOD = B_CLK_PERIOD;

  TIME_DELAY = $time;
end

always @ (BusClk) #B_CLK_PERIOD BusClk_Center = BusClk;


// This code generates the BusEnable output.
// BusEnable is made from a combination of the shift circuitry and
// a combinatorial logic produced from Reset and ExtBE.  This shifter is
// slightly different than the others for this reason.

wire	BusEnable_Shifter_wire;
assign	BusEnable = (Reset & ExtBE) ? (CCtl_OK ? 1'b0 : 1'bx) : BusEnable_Shifter_wire;

reg	[3:0]	BESel_Hold;
reg	[3:0]	BESel_Shift;

wire	BESel_Load;
assign	BESel_Load = BESel_Shift[0];

always @ ( negedge SynClk ) BESel_Hold = BESel;

always @ ( posedge BusClk )
  if ( SynClk_QUAD1 )
    BESel_Shift = BESel_Hold;
  else
    BESel_Shift = ( BESel_Shift >> 1'b1 );
  
wire	[7:0]	BE_Bus;
assign	BE_Bus = { TData7[10], TData6[10], TData5[10], TData4[10],
		   TData3[10], TData2[10], TData1[10], TData0[10] };

pin_shift_driver	BE_shifter
( BusEnable_Shifter_wire, BE_Bus, BusClk, BusClk_Center, BESel_Load, CCtl_OK );

// This code generates the BusControl output.

reg	[3:0]	BCSel_Hold;
reg	[3:0]	BCSel_Shift;

wire	BCSel_Load;
assign	BCSel_Load = BCSel_Shift[0];

always @ ( negedge SynClk ) BCSel_Hold = BCSel;

always @ ( posedge BusClk )
  if ( SynClk_QUAD1 )
    BCSel_Shift = BCSel_Hold;
  else
    BCSel_Shift = ( BCSel_Shift >> 1'b1 );
  
wire	[7:0]	BC_Bus;
assign	BC_Bus = { TData7[9], TData6[9], TData5[9], TData4[9],
		   TData3[9], TData2[9], TData1[9], TData0[9] };

pin_shift_driver	BC_shifter
	( BusCtrl, BC_Bus, BusClk, BusClk_Center, BCSel_Load, CCtl_OK );


// This code generates the BusData outputs.

reg	[3:0]	BDSel_Hold;
reg	[3:0]	BDSel_Shift;

wire	BDSel_Load;
assign	BDSel_Load = BDSel_Shift[0];

always @ ( negedge SynClk ) BDSel_Hold = BDSel;

always @ ( posedge BusClk )
  if ( SynClk_QUAD1 )
    BDSel_Shift = BDSel_Hold;
  else
    BDSel_Shift = ( BDSel_Shift >> 1'b1 );

wire	[7:0]	BD_Bus8;
assign	BD_Bus8 = { TData7[8], TData6[8], TData5[8], TData4[8],
		    TData3[8], TData2[8], TData1[8], TData0[8] };

pin_shift_driver	BD_shifter8
	( BusData[8], BD_Bus8, BusClk, BusClk_Center, BDSel_Load, CCtl_OK );

wire	[7:0]	BD_Bus7;
assign	BD_Bus7 = { TData7[7], TData6[7], TData5[7], TData4[7],
		    TData3[7], TData2[7], TData1[7], TData0[7] };

pin_shift_driver	BD_shifter7
	( BusData[7], BD_Bus7, BusClk, BusClk_Center, BDSel_Load, CCtl_OK );

wire	[7:0]	BD_Bus6;
assign	BD_Bus6 = { TData7[6], TData6[6], TData5[6], TData4[6],
		    TData3[6], TData2[6], TData1[6], TData0[6] };

pin_shift_driver	BD_shifter6
	( BusData[6], BD_Bus6, BusClk, BusClk_Center, BDSel_Load, CCtl_OK );

wire	[7:0]	BD_Bus5;
assign	BD_Bus5 = { TData7[5], TData6[5], TData5[5], TData4[5],
		    TData3[5], TData2[5], TData1[5], TData0[5] };

pin_shift_driver	BD_shifter5
	( BusData[5], BD_Bus5, BusClk, BusClk_Center, BDSel_Load, CCtl_OK );

wire	[7:0]	BD_Bus4;
assign	BD_Bus4 = { TData7[4], TData6[4], TData5[4], TData4[4],
		    TData3[4], TData2[4], TData1[4], TData0[4] };

pin_shift_driver	BD_shifter4
	( BusData[4], BD_Bus4, BusClk, BusClk_Center, BDSel_Load, CCtl_OK );

wire	[7:0]	BD_Bus3;
assign	BD_Bus3 = { TData7[3], TData6[3], TData5[3], TData4[3],
		    TData3[3], TData2[3], TData1[3], TData0[3] };

pin_shift_driver	BD_shifter3
	( BusData[3], BD_Bus3, BusClk, BusClk_Center, BDSel_Load, CCtl_OK );

wire	[7:0]	BD_Bus2;
assign	BD_Bus2 = { TData7[2], TData6[2], TData5[2], TData4[2],
		    TData3[2], TData2[2], TData1[2], TData0[2] };

pin_shift_driver	BD_shifter2
	( BusData[2], BD_Bus2, BusClk, BusClk_Center, BDSel_Load, CCtl_OK );

wire	[7:0]	BD_Bus1;
assign	BD_Bus1 = { TData7[1], TData6[1], TData5[1], TData4[1],
		    TData3[1], TData2[1], TData1[1], TData0[1] };

pin_shift_driver	BD_shifter1
	( BusData[1], BD_Bus1, BusClk, BusClk_Center, BDSel_Load, CCtl_OK );

wire	[7:0]	BD_Bus0;
assign	BD_Bus0 = { TData7[0], TData6[0], TData5[0], TData4[0],
		    TData3[0], TData2[0], TData1[0], TData0[0] };

pin_shift_driver	BD_shifter0
	( BusData[0], BD_Bus0, BusClk, BusClk_Center, BDSel_Load, CCtl_OK );


// This code generates the RData bus for the internal logic of the ASIC.
// This is for RCData, which is RData[8] or the BusControl wire.

reg	[3:0]	RCSel_Hold;
reg	[3:0]	RCSel_Shift;

wire	RCSel_Load;
assign	RCSel_Load = RCSel_Shift[0];

always @ ( negedge SynClk ) RCSel_Hold = RCSel;

always @ ( posedge BusClk )
  if ( SynClk_QUAD0 )
    RCSel_Shift = RCSel_Hold;
  else
    RCSel_Shift = ( RCSel_Shift >> 1'b1 );
  
wire	[7:0]	RD_Bus9;
assign	{ RData7[9], RData6[9], RData5[9], RData4[9],
	  RData3[9], RData2[9], RData1[9], RData0[9] } = RD_Bus9;

pin_shift_sampler
	RD_shifter9( RD_Bus9, BusCtrl, BusClk, RCSel_Load );

// This code generates the RData bus for the internal logic of the ASIC.
// This is for the remainder of the RData bus which includes BusData[8:0]

reg	[3:0]	RDSel_Hold;
reg	[3:0]	RDSel_Shift;

wire	RDSel_Load;
assign	RDSel_Load = RDSel_Shift[0];

always @ ( negedge SynClk ) RDSel_Hold = RDSel;

always @ ( posedge BusClk )
  if ( SynClk_QUAD0 )
    RDSel_Shift = RDSel_Hold;
  else
    RDSel_Shift = ( RDSel_Shift >> 1'b1 );
  
wire	[7:0]	RD_Bus0;
assign	{ RData7[0], RData6[0], RData5[0], RData4[0],
	  RData3[0], RData2[0], RData1[0], RData0[0] } = RD_Bus0;

pin_shift_sampler
	RD_shifter0( RD_Bus0, BusData[0], BusClk, RDSel_Load );

wire	[7:0]	RD_Bus1;
assign	{ RData7[1], RData6[1], RData5[1], RData4[1],
	  RData3[1], RData2[1], RData1[1], RData0[1] } = RD_Bus1;

pin_shift_sampler
	RD_shifter1( RD_Bus1, BusData[1], BusClk, RDSel_Load );

wire	[7:0]	RD_Bus2;
assign	{ RData7[2], RData6[2], RData5[2], RData4[2],
	  RData3[2], RData2[2], RData1[2], RData0[2] } = RD_Bus2;

pin_shift_sampler
	RD_shifter2( RD_Bus2, BusData[2], BusClk, RDSel_Load );

wire	[7:0]	RD_Bus3;
assign	{ RData7[3], RData6[3], RData5[3], RData4[3],
	  RData3[3], RData2[3], RData1[3], RData0[3] } = RD_Bus3;

pin_shift_sampler
	RD_shifter3( RD_Bus3, BusData[3], BusClk, RDSel_Load );

wire	[7:0]	RD_Bus4;
assign	{ RData7[4], RData6[4], RData5[4], RData4[4],
	  RData3[4], RData2[4], RData1[4], RData0[4] } = RD_Bus4;

pin_shift_sampler
	RD_shifter4( RD_Bus4, BusData[4], BusClk, RDSel_Load );

wire	[7:0]	RD_Bus5;
assign	{ RData7[5], RData6[5], RData5[5], RData4[5],
	  RData3[5], RData2[5], RData1[5], RData0[5] } = RD_Bus5;

pin_shift_sampler
	RD_shifter5( RD_Bus5, BusData[5], BusClk, RDSel_Load );

wire	[7:0]	RD_Bus6;
assign	{ RData7[6], RData6[6], RData5[6], RData4[6],
	  RData3[6], RData2[6], RData1[6], RData0[6] } = RD_Bus6;

pin_shift_sampler
	RD_shifter6( RD_Bus6, BusData[6], BusClk, RDSel_Load );

wire	[7:0]	RD_Bus7;
assign	{ RData7[7], RData6[7], RData5[7], RData4[7],
	  RData3[7], RData2[7], RData1[7], RData0[7] } = RD_Bus7;

pin_shift_sampler
	RD_shifter7( RD_Bus7, BusData[7], BusClk, RDSel_Load );

wire	[7:0]	RD_Bus8;
assign	{ RData7[8], RData6[8], RData5[8], RData4[8],
	  RData3[8], RData2[8], RData1[8], RData0[8] } = RD_Bus8;

pin_shift_sampler
	RD_shifter8( RD_Bus8, BusData[8], BusClk, RDSel_Load );

endmodule


module pin_shift_driver
	( pin_out, Data_In, BusClk, BusClk_Center, Load, CCtl_OK );

  output	pin_out;

  input	[7:0]	Data_In;
  input		BusClk;
  input		BusClk_Center;
  input		Load;
  input		CCtl_OK;
reg	[7:0]	shifter;
reg		pin_out;

always @ ( BusClk_Center )
  if ( BusClk_Center )
    if ( shifter[0] == 1'b1 )
      pin_out = 1'b0;
    else if ( shifter[0] === 1'bx )
      pin_out = 1'bx;
    else 
      pin_out = 1'bz;
  else
    if ( shifter[1] == 1'b1 )
      pin_out = 1'b0;
    else if ( shifter[1] === 1'bx )
      pin_out = 1'bx;
    else
      pin_out = 1'bz;

always @( posedge BusClk )
  if ( Load & CCtl_OK )
    shifter = Data_In;
  else if ( Load & ~CCtl_OK )
    shifter = 8'bx;
  else
    shifter = { 2'b0,shifter[7:2] };

endmodule

module pin_shift_sampler
	( Data_In, pin_in, BusClk, Sample );

  output	[7:0]	Data_In;

  input			pin_in;
  input			BusClk;
  input			Sample;

reg	[9:0]	bit_stream;
reg	[7:0]	Data_In;

wire	[9:0]	bit_stream_wire;
assign	bit_stream_wire = bit_stream;

always @ ( BusClk )
  begin
    bit_stream[8:0] = bit_stream_wire[9:1];
    bit_stream[9] = ~pin_in;
  end

always @ ( posedge BusClk )
  if ( Sample )
    Data_In = bit_stream[7:0];	// [9:8] is receive latency

endmodule