TDBIAUSBNNLMOC.v
1.12 KB
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// VERSION:1.00 DATE:2002/07/26 OPENCAD Verilog LIBRARY (1ps)
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDBIAUSBNNLMOC ( N01, N02, H01, H02, H03, H04, H05 );
inout N01;
output N02;
input H01;
input H02;
input H03;
input H04;
input H05;
buf ( _H01, H01 );
buf ( _H02, H02 );
buf ( _H03, H03 );
buf ( _H04, H04 );
buf ( _H05, H05 );
not ( _G001, _H03 );
and ( _G002, _H01, _G001 );
and ( _ENA, _H02, _H05 );
bufif1 ( _G003, _ENA, _H04 );
buf ( _G004, _G003 );
bufif1 ( _G005, _G002, _G004 );
bufif1 ( N01, _G005, _G004 );
buf ( N02, N01 );
specify
specparam DMY_SPC=1:1:1;
( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
( H02 *> N01 ) = ( 0:0:0, 0:0:0, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC );
( H03 *> N01 ) = ( DMY_SPC, DMY_SPC );
( H05 *> N01 ) = ( 0:0:0, 0:0:0, DMY_SPC, DMY_SPC, DMY_SPC, DMY_SPC );
( N01 *> N02 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine