TDBSSTE2X4.v
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// VERSION:4.00 DATE:00/02/15 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDBSSTE2X4 ( BSCON, N02, H01, H02, H03, H04, H05 );
input H01 ;
input H02 ;
input H03 ;
input H04 ;
input H05 ;
output BSCON ;
output N02 ;
buf ( _H01, H01 );
buf ( _H02, H02 );
buf ( _H03, H03 );
buf ( _H04, H04 );
buf ( _H05, H05 );
not ( _G001, _H01 );
not ( _G002, _H02 );
not ( _G003, _H03 );
and ( _G004, _G001, _G002 );
and ( _G005, _G001, _G003 );
and ( _G006, _G002, _H03 );
or ( _G007, _G004, _G005, _G006 );
or ( _G008, _H04, _H05 );
nor ( BSCON, _G007, _G008 );
not ( N02, _G007 );
specify
specparam DMY_SPC=1;
( H01 *> BSCON ) = ( DMY_SPC, DMY_SPC );
( H02 *> BSCON ) = ( DMY_SPC, DMY_SPC );
( H04 *> BSCON ) = ( DMY_SPC, DMY_SPC );
( H05 *> BSCON ) = ( DMY_SPC, DMY_SPC );
( H01 *> N02 ) = ( DMY_SPC, DMY_SPC );
( H02 *> N02 ) = ( DMY_SPC, DMY_SPC );
if ( H03 )
( H03 *> BSCON ) = ( DMY_SPC, DMY_SPC );
if ( !H03 )
( H03 *> BSCON ) = ( DMY_SPC, DMY_SPC );
if ( H03 )
( H03 *> N02 ) = ( DMY_SPC, DMY_SPC );
if ( !H03 )
( H03 *> N02 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine