TBSEDFLQRBX4U.v
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// VERSION:4.00 DATE:2001/05/14 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TBSEDFLQRBX4U ( N01, H01, H02, H03 );
input H01;
input H02;
input H03;
output N01;
reg notifier;
reg docheck1;
reg docheck2;
reg docheck3;
reg docheck4;
reg docheck5;
reg docheck6;
buf ( _H01, H01 );
buf ( _H02, H02 );
buf ( _H03, H03 );
not ( _G004, _H02 );
buf ( _G006, _G003 );
and ( N01, _G006, _H03 );
DESFQ ( _G003, _H01, _G004, _H03, 1'b1, notifier );
buf #1 ( _G099, _G003 );
`ifdef INCA
buf #1 ( _docheck1, docheck1 );
buf #1 ( _docheck2, docheck2 );
buf #1 ( _docheck3, docheck3 );
buf #1 ( _docheck4, docheck4 );
buf #1 ( _docheck5, docheck5 );
buf #1 ( _docheck6, docheck6 );
`else
`ifdef VCS
buf #1 ( _docheck1, docheck1 );
buf #1 ( _docheck2, docheck2 );
buf #1 ( _docheck3, docheck3 );
buf #1 ( _docheck4, docheck4 );
buf #1 ( _docheck5, docheck5 );
buf #1 ( _docheck6, docheck6 );
`else
buf ( _docheck1, docheck1 );
buf ( _docheck2, docheck2 );
buf ( _docheck3, docheck3 );
buf ( _docheck4, docheck4 );
buf ( _docheck5, docheck5 );
buf ( _docheck6, docheck6 );
`endif
`endif
initial //initialize data flags
begin
docheck1 = 0;
docheck2 = 0;
docheck3 = 0;
docheck4 = 0;
docheck5 = 0;
docheck6 = 0;
end
always @( _H01 or _H03 )
begin
docheck1 = ( _H03 !== 1'b0 );
if ( (_H02 === 1'b1) && (_H03 !== 1'b0) )
docheck5 = ( _G099 !== _H01 );
if ( (_H02 === 1'b0) && (_H03 !== 1'b0) )
docheck4 = ( _G099 !== _H01 );
end
always @( negedge _H02 )
begin
docheck1 = ( _H03 !== 1'b0 );
docheck3 = ( _H01 !== 1'b0 );
docheck5 = ( (_G099 !== _H01) && (_H03 !== 1'b0) );
docheck4 = 1;
end
always @( posedge _H02 )
begin
docheck5 = ( (_G099 !== _H01) && (_H03 !== 1'b0) );
docheck4 = ( _H03 !== 1'b0 );
end
always @( _G003 )
begin
if ( _H03 === 1'b1 )
docheck6 = ( _G003 !== 1'b0 );
end
always @( posedge _H03 )
begin
docheck2 = ( _H01 !== 1'b0 );
docheck6 = ( _G003 !== 1'b0 );
end
specify
specparam DMY_SPC=1;
$setup ( posedge H01, negedge H02 &&& _docheck1, DMY_SPC, notifier );
$setup ( negedge H01, negedge H02 &&& _docheck1, DMY_SPC, notifier );
$hold ( negedge H02, posedge H01 &&& _docheck1, DMY_SPC, notifier );
$hold ( negedge H02, negedge H01 &&& _docheck1, DMY_SPC, notifier );
$setup ( posedge H03, negedge H02 &&& _docheck2, DMY_SPC, notifier );
$hold ( negedge H02, posedge H03 &&& _docheck3, DMY_SPC, notifier );
$width ( posedge H02 &&& _docheck4, DMY_SPC, 0, notifier );
$width ( negedge H02 &&& _docheck5, DMY_SPC, 0, notifier );
$width ( negedge H03 &&& _docheck6, DMY_SPC, 0, notifier );
if ( H03 )
( negedge H02 => ( N01 +: H01 )) = ( DMY_SPC, DMY_SPC );
( negedge H03 => ( N01 +: 1'b0 )) = ( 0:0:0, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine