cvmask.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: cvmask.v,v 1.1 2002/03/28 00:26:13 berndt Exp $
/* Project Reality
MDP
Created by Mike M. Cai 6/3/94
*/
module cvmask( // outputs
mask_out,
// inputs
eq_xmax, less_xmax, xmin_eq, xmin_less, x_val,
xmax0_fr, xmax1_fr, xmax2_fr, xmax3_fr,
xmin0_fr, xmin1_fr, xmin2_fr, xmin3_fr);
output [15:0] mask_out;
input [3:0] eq_xmax, less_xmax;
input [3:0] xmin_eq, xmin_less;
input [3:0] x_val;
input [2:0] xmax0_fr, xmax1_fr, xmax2_fr, xmax3_fr,
xmin0_fr, xmin1_fr, xmin2_fr, xmin3_fr;
reg [15:0] mask_l, mask_r;
wire [15:0] mask_out;
always @( xmin_eq or xmin_less or xmin0_fr or xmin1_fr or xmin2_fr or xmin3_fr)
begin
if (xmin_eq[0] == 1'h0)
mask_l[15:12] = {4{xmin_less[0]}};
else
case ({xmin0_fr[0],xmin0_fr[2:1]})
3'h0: mask_l[15:12] = 4'hf;
3'h1: mask_l[15:12] = 4'h7;
3'h2: mask_l[15:12] = 4'h3;
3'h3: mask_l[15:12] = 4'h1;
3'h4: mask_l[15:12] = 4'h7;
3'h5: mask_l[15:12] = 4'h3;
3'h6: mask_l[15:12] = 4'h1;
3'h7: mask_l[15:12] = 4'h0;
endcase
if (xmin_eq[1] == 1'h0)
mask_l[11:8] = {4{xmin_less[1]}};
else
case ({xmin1_fr[0], xmin1_fr[2:1]})
3'h0: mask_l[11:8] = 4'hf;
3'h1: mask_l[11:8] = 4'h7;
3'h2: mask_l[11:8] = 4'h3;
3'h3: mask_l[11:8] = 4'h1;
3'h4: mask_l[11:8] = 4'h7;
3'h5: mask_l[11:8] = 4'h3;
3'h6: mask_l[11:8] = 4'h1;
3'h7: mask_l[11:8] = 4'h0;
endcase
if (xmin_eq[2] == 1'h0)
mask_l[7:4] = {4{xmin_less[2]}};
else
case ({xmin2_fr[0], xmin2_fr[2:1]})
3'h0: mask_l[7:4] = 4'hf;
3'h1: mask_l[7:4] = 4'h7;
3'h2: mask_l[7:4] = 4'h3;
3'h3: mask_l[7:4] = 4'h1;
3'h4: mask_l[7:4] = 4'h7;
3'h5: mask_l[7:4] = 4'h3;
3'h6: mask_l[7:4] = 4'h1;
3'h7: mask_l[7:4] = 4'h0;
endcase
if (xmin_eq[3] == 1'h0)
mask_l[3:0] = {4{xmin_less[3]}};
else
case ({xmin3_fr[0], xmin3_fr[2:1]})
3'h0: mask_l[3:0] = 4'hf;
3'h1: mask_l[3:0] = 4'h7;
3'h2: mask_l[3:0] = 4'h3;
3'h3: mask_l[3:0] = 4'h1;
3'h4: mask_l[3:0] = 4'h7;
3'h5: mask_l[3:0] = 4'h3;
3'h6: mask_l[3:0] = 4'h1;
3'h7: mask_l[3:0] = 4'h0;
endcase
end
always @( eq_xmax or less_xmax or xmax0_fr or xmax1_fr or xmax2_fr or xmax3_fr)
begin
if (eq_xmax[0] == 1'h0)
mask_r[15:12] = {4{less_xmax[0]}};
else
case ({xmax0_fr[0],xmax0_fr[2:1]})
3'h0: mask_r[15:12] = 4'h0;
3'h1: mask_r[15:12] = 4'h8;
3'h2: mask_r[15:12] = 4'hc;
3'h3: mask_r[15:12] = 4'he;
3'h4: mask_r[15:12] = 4'h8;
3'h5: mask_r[15:12] = 4'hc;
3'h6: mask_r[15:12] = 4'he;
3'h7: mask_r[15:12] = 4'hf;
endcase
if (eq_xmax[1] == 1'h0)
mask_r[11:8] = {4{less_xmax[1]}};
else
case ({xmax1_fr[0], xmax1_fr[2:1]})
3'h0: mask_r[11:8] = 4'h0;
3'h1: mask_r[11:8] = 4'h8;
3'h2: mask_r[11:8] = 4'hc;
3'h3: mask_r[11:8] = 4'he;
3'h4: mask_r[11:8] = 4'h8;
3'h5: mask_r[11:8] = 4'hc;
3'h6: mask_r[11:8] = 4'he;
3'h7: mask_r[11:8] = 4'hf;
endcase
if (eq_xmax[2] == 1'h0)
mask_r[7:4] = {4{less_xmax[2]}};
else
case ({xmax2_fr[0], xmax2_fr[2:1]})
3'h0: mask_r[7:4] = 4'h0;
3'h1: mask_r[7:4] = 4'h8;
3'h2: mask_r[7:4] = 4'hc;
3'h3: mask_r[7:4] = 4'he;
3'h4: mask_r[7:4] = 4'h8;
3'h5: mask_r[7:4] = 4'hc;
3'h6: mask_r[7:4] = 4'he;
3'h7: mask_r[7:4] = 4'hf;
endcase
if (eq_xmax[3] == 1'h0)
mask_r[3:0] = {4{less_xmax[3]}};
else
case ({xmax3_fr[0], xmax3_fr[2:1]})
3'h0: mask_r[3:0] = 4'h0;
3'h1: mask_r[3:0] = 4'h8;
3'h2: mask_r[3:0] = 4'hc;
3'h3: mask_r[3:0] = 4'he;
3'h4: mask_r[3:0] = 4'h8;
3'h5: mask_r[3:0] = 4'hc;
3'h6: mask_r[3:0] = 4'he;
3'h7: mask_r[3:0] = 4'hf;
endcase
end
// generate the final mask.
assign mask_out = mask_l & mask_r & 16'ha5a5 &
{{4{x_val[3]}}, {4{x_val[2]}}, {4{x_val[1]}}, {4{x_val[0]}}};
endmodule // cvmask