pif_tasks.v
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task pif_test; // rac qsim testbed
begin
test_selected <= HIGH;
repeat (10) @(posedge clock);
config_rdram;
repeat (10) @(posedge clock);
$finish;
end
endtask
task pif_interrupt;
// test interrupt generation and clearing logic
begin
test_selected <= HIGH;
repeat (10) @(posedge clock);
config_rdram;
// 64 byte transfer pif to dram
write_word(BUS_ADDRESS_SI_DRAM_ADDRESS, 3, BUS_ADDRESS_DRAM);
write_word(BUS_ADDRESS_SI_PIF_AD_RD64B, 3, 32'h1fc007c0);
read_word(BUS_ADDRESS_SI_STATUS, 3); // read status word
while (data[0] & 32'h0fff) begin
// wait for dma status to go to idle and read busy to clear
if (data[0] & 32'h1000 == 1)
$display ("ERROR task pif_interrupt interrupt set during dma_busy");
read_word(BUS_ADDRESS_SI_STATUS, 3); // get next status for while eval
end
// dma busy fell through, check for interrupt being set
read_word(BUS_ADDRESS_SI_STATUS, 3);
if (data[0] & 32'h1000 != 32'h1000)
$display ("ERROR task pif_interrupt interrupt should be set");
// now clear out the interrrupt
write_word(BUS_ADDRESS_SI_STATUS, 3, 0);
read_word(BUS_ADDRESS_SI_STATUS, 3);
if (data[0] & 32'h1000 == 32'h1000)
$display ("ERROR task pif_interrupt interrupt should be cleared");
$finish;
end
endtask
task pif_rd_lap1;
// dma/ io overlap conflict test bed
begin
test_selected <= HIGH;
repeat (10) @(posedge clock);
// set up a dma, try to line up an io_read with end of dma active
config_rdram;
// io request during 2nd to last cycle of!dma_state !- idle
// 64 byte transfer pif to dram
write_word(BUS_ADDRESS_SI_DRAM_ADDRESS, 3, BUS_ADDRESS_DRAM);
write_word(BUS_ADDRESS_SI_PIF_AD_RD64B, 3, 32'h1fc007c0);
read_word(BUS_ADDRESS_SI_STATUS, 3); // read status word
while ((data[0] & 32'h0f00) != 32'h300) begin // dma_state 3 is near end
read_word(BUS_ADDRESS_SI_STATUS, 3); // get next status for while eval
end
// do overlapping read request
// with no delays, 1 ck of dma_!idle after write
// repeat (1) @(posedge clock); // write during last clock;
read_word(32'h1fc007c0,3);
// now delay the io read request by 1 clock, during last clock of dmastate !idle
// 64 byte transfer pif to dram
write_word(BUS_ADDRESS_SI_DRAM_ADDRESS, 3, BUS_ADDRESS_DRAM);
write_word(BUS_ADDRESS_SI_PIF_AD_RD64B, 3, 32'h1fc007c0);
read_word(BUS_ADDRESS_SI_STATUS, 3); // read status word
while ((data[0] & 32'h0f00) != 32'h300) begin // dma_state 3 is near end
read_word(BUS_ADDRESS_SI_STATUS, 3); // get next status for while eval
end
// do overlapping read request
// with no delays, 1 ck of dma_!idle after write
repeat (1) @(posedge clock); // write during last clock;
read_word(32'h1fc007c0,3);
// now delay the io read request by 2 clock, 1st clock of idle
write_word(BUS_ADDRESS_SI_DRAM_ADDRESS, 3, BUS_ADDRESS_DRAM);
write_word(BUS_ADDRESS_SI_PIF_AD_RD64B, 3, 32'h1fc007c0);
read_word(BUS_ADDRESS_SI_STATUS, 3); // read status word
while ((data[0] & 32'h0f00) != 32'h300) begin // dma_state 3 is near end
read_word(BUS_ADDRESS_SI_STATUS, 3); // get next status for while eval
end
// do overlapping read request
// with no delays, 1 ck of dma_!idle after write
repeat (2) @(posedge clock); // write during 1st clock of idll
read_word(32'h1fc007c0,3);
$finish;
end
endtask
task pif_rd_lap2;
// dma/ io overlap conflict test bed
begin
test_selected <= HIGH;
repeat (10) @(posedge clock);
// set up a dma, try to line up an io_read with end of dma active
config_rdram;
// io request during 2nd to last cycle of!dma_state !- idle
// 64 byte transfer pif to dram
write_word(BUS_ADDRESS_SI_DRAM_ADDRESS, 3, BUS_ADDRESS_DRAM);
write_word(BUS_ADDRESS_SI_PIF_AD_RD64B, 3, 32'h1fc007c0);
read_word(BUS_ADDRESS_SI_STATUS, 3); // read status word
while ((data[0] & 32'h0f00) != 32'h300) begin // dma_state 3 is near end
read_word(BUS_ADDRESS_SI_STATUS, 3); // get next status for while eval
end
// do overlapping read request
// with no delays, 1 ck of dma_!idle after write
repeat (1) @(posedge clock); // write during last clock;
read_word(32'h1fc007c0,3);
$finish;
end
endtask
task pif_rd_lap3;
// dma/ io overlap conflict test bed
begin
test_selected <= HIGH;
repeat (10) @(posedge clock);
// set up a dma, try to line up an io_read with end of dma active
config_rdram;
// io request during 2nd to last cycle of!dma_state !- idle
// 64 byte transfer pif to dram
write_word(BUS_ADDRESS_SI_DRAM_ADDRESS, 3, BUS_ADDRESS_DRAM);
write_word(BUS_ADDRESS_SI_PIF_AD_RD64B, 3, 32'h1fc007c0);
read_word(BUS_ADDRESS_SI_STATUS, 3); // read status word
while ((data[0] & 32'h0f00) != 32'h300) begin // dma_state 3 is near end
read_word(BUS_ADDRESS_SI_STATUS, 3); // get next status for while eval
end
// now delay the io read request by 2 clock, 1st clock of idle
// do overlapping read request
// with no delays, 1 ck of dma_!idle after write
repeat (2) @(posedge clock); // write during 1st clock of idll
read_word(32'h1fc007c0,3);
$finish;
end
endtask
task pif_rd64B;
begin
test_selected <= HIGH;
repeat (10) @(posedge clock);
config_rdram;
// 64 bit transfer pif to dram
write_word(BUS_ADDRESS_SI_DRAM_ADDRESS, 3, BUS_ADDRESS_DRAM);
write_word(BUS_ADDRESS_SI_PIF_AD_RD64B, 3, 32'h1fc007c0);
// repeat (800) @(posedge clock);
read_word(BUS_ADDRESS_SI_STATUS, 3); // read status word
while (data[0] & 32'hfff) begin
read_word(BUS_ADDRESS_SI_STATUS, 3); // get next status for while eval
end
// dma status (data[0]) is done, so read data from dram
// assumes pif is loaded with data = address
read_word(BUS_ADDRESS_DRAM, 3);
// read data is left shifted 2 bits from write address
if (data[0] !== 32'h1f0)
$display ("ERROR task pif_read64B read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+4, 3);
if (data[0] !== 32'h1f1)
$display ("ERROR task pif_read64B read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+8, 3);
if (data[0] !== 32'h1f2)
$display ("ERROR task pif_read64B read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+12, 3);
if (data[0] !== 32'h1f3)
$display ("ERROR task pif_read64B read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+16, 3);
if (data[0] !== 32'h1f4)
$display ("ERROR task pif_read64B read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+20, 3);
if (data[0] !== 32'h1f5)
$display ("ERROR task pif_read64B read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+24, 3);
if (data[0] !== 32'h1f6)
$display ("ERROR task pif_read64B read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+28, 3);
if (data[0] !== 32'h1f7)
$display ("ERROR task pif_read64B read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+32, 3);
if (data[0] !== 32'h1f8)
$display ("ERROR task pif_read64B read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+36, 3);
if (data[0] !== 32'h1f9)
$display ("ERROR task pif_read64B read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+40, 3);
if (data[0] !== 32'h1fa)
$display ("ERROR task pif_read64B read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+44, 3);
if (data[0] !== 32'h1fb)
$display ("ERROR task pif_read64B read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+48, 3);
if (data[0] !== 32'h1fc)
$display ("ERROR task pif_read64B read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+52, 3);
if (data[0] !== 32'h1fd)
$display ("ERROR task pif_read64B read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+56, 3);
if (data[0] !== 32'h1fe)
$display ("ERROR task pif_read64B read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+60, 3);
if (data[0] !== 32'h1ff)
$display ("ERROR task pif_read64B read data is %h ",data[0]);
$finish;
end
endtask
task pif_wr64B;
begin
test_selected <= HIGH;
repeat (10) @(posedge clock);
config_rdram;
// load rdram
write_word(BUS_ADDRESS_DRAM, 3, 32'h0ad00da0);
write_word(BUS_ADDRESS_DRAM+4, 3, 32'h1ad11da1);
write_word(BUS_ADDRESS_DRAM+8, 3, 32'h2ad22da2);
write_word(BUS_ADDRESS_DRAM+12, 3, 32'h3ad33da3);
write_word(BUS_ADDRESS_DRAM+16, 3, 32'h4ad00004);
write_word(BUS_ADDRESS_DRAM+20, 3, 32'h5ad00005);
write_word(BUS_ADDRESS_DRAM+24, 3, 32'h6ad00006);
write_word(BUS_ADDRESS_DRAM+28, 3, 32'h7ad00007);
write_word(BUS_ADDRESS_DRAM+32, 3, 32'h8ad00008);
write_word(BUS_ADDRESS_DRAM+36, 3, 32'h9ad00009);
write_word(BUS_ADDRESS_DRAM+40, 3, 32'haad0000a);
write_word(BUS_ADDRESS_DRAM+44, 3, 32'hbad0000b);
write_word(BUS_ADDRESS_DRAM+48, 3, 32'hcad0000c);
write_word(BUS_ADDRESS_DRAM+52, 3, 32'hdad0000d);
write_word(BUS_ADDRESS_DRAM+56, 3, 32'head0000e);
write_word(BUS_ADDRESS_DRAM+60, 3, 32'hfadfffff);
// 64 bit transfer dram to pif
write_word(BUS_ADDRESS_SI_DRAM_ADDRESS, 3, BUS_ADDRESS_DRAM);
// writing to pif word address 7f0
write_word(BUS_ADDRESS_SI_PIF_AD_WR64B, 3, 32'h1fc007c0);
read_word(BUS_ADDRESS_SI_STATUS, 3); // read status word
while (data[0] & 32'hfff) begin
read_word(BUS_ADDRESS_SI_STATUS, 3); // get next status for while eval
end
$finish;
end
endtask
task pif_wr_rd;
begin
test_selected <= HIGH;
$display(`CLOCK_COUNT, " : timer function ");
repeat (10) @(posedge clock);
config_rdram;
// load rdram
write_word(BUS_ADDRESS_DRAM, 3, 32'h0ad00da0);
write_word(BUS_ADDRESS_DRAM+4, 3, 32'h1ad11da1);
write_word(BUS_ADDRESS_DRAM+8, 3, 32'h2ad22da2);
write_word(BUS_ADDRESS_DRAM+12, 3, 32'h3ad33da3);
write_word(BUS_ADDRESS_DRAM+16, 3, 32'h4ad44da4);
write_word(BUS_ADDRESS_DRAM+20, 3, 32'h5ad55da5);
write_word(BUS_ADDRESS_DRAM+24, 3, 32'h6ad66da6);
write_word(BUS_ADDRESS_DRAM+28, 3, 32'h7ad77da7);
write_word(BUS_ADDRESS_DRAM+32, 3, 32'h8ad88da8);
write_word(BUS_ADDRESS_DRAM+36, 3, 32'h9ad99da9);
write_word(BUS_ADDRESS_DRAM+40, 3, 32'haadaadaa);
write_word(BUS_ADDRESS_DRAM+44, 3, 32'hbadbbdab);
write_word(BUS_ADDRESS_DRAM+48, 3, 32'hcadccdac);
write_word(BUS_ADDRESS_DRAM+52, 3, 32'hdaddddad);
write_word(BUS_ADDRESS_DRAM+56, 3, 32'headeedae);
write_word(BUS_ADDRESS_DRAM+60, 3, 32'hfadffdaf);
// 64 bit transfer dram to pif
write_word(BUS_ADDRESS_SI_DRAM_ADDRESS, 3, BUS_ADDRESS_DRAM);
// write to pif word address 1f0
write_word(BUS_ADDRESS_SI_PIF_AD_WR64B, 3, 32'h1fc007c0);
read_word(BUS_ADDRESS_SI_STATUS, 3); // read status word
while (data[0] & 32'hfff) begin
read_word(BUS_ADDRESS_SI_STATUS, 3);
end
// done with write, now do read of pif
// read back from pif to dram
write_word(BUS_ADDRESS_SI_DRAM_ADDRESS, 3, BUS_ADDRESS_DRAM);
write_word(BUS_ADDRESS_SI_PIF_AD_RD64B, 3, 32'h1fc007c0);
// monitor status
read_word(BUS_ADDRESS_SI_STATUS, 3); // read status word
while (data[0] & 32'hfff) begin
read_word(BUS_ADDRESS_SI_STATUS, 3);
end
// did it make it to dram?
read_word(BUS_ADDRESS_DRAM, 3);
if (data[0] !== 32'h0ad00da0)
$display ("ERROR task pif_wr_rd read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+4, 3);
if (data[0] !== 32'h1ad11da1)
$display ("ERROR task pif_wr_rd read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+8, 3);
if (data[0] !== 32'h2ad22da2)
$display ("ERROR task pif_wr_rd read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+12, 3);
if (data[0] !== 32'h3ad33da3)
$display ("ERROR task pif_wr_rd read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+16, 3);
if (data[0] !== 32'h4ad44da4)
$display ("ERROR task pif_wr_rd read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+20, 3);
if (data[0] !== 32'h5ad55da5)
$display ("ERROR task pif_wr_rd read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+24, 3);
if (data[0] !== 32'h6ad66da6)
$display ("ERROR task pif_wr_rd read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+28, 3);
if (data[0] !== 32'h7ad77da7)
$display ("ERROR task pif_wr_rd read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+32, 3);
if (data[0] !== 32'h8ad88da8)
$display ("ERROR task pif_wr_rd read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+36, 3);
if (data[0] !== 32'h9ad99da9)
$display ("ERROR task pif_wr_rd read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+40, 3);
if (data[0] !== 32'haadaadaa)
$display ("ERROR task pif_wr_rd read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+44, 3);
if (data[0] !== 32'hbadbbdab)
$display ("ERROR task pif_wr_rd read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+48, 3);
if (data[0] !== 32'hcadccdac)
$display ("ERROR task pif_wr_rd read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+52, 3);
if (data[0] !== 32'hdaddddad)
$display ("ERROR task pif_wr_rd read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+56, 3);
if (data[0] !== 32'headeedae)
$display ("ERROR task pif_wr_rd read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+60, 3);
if (data[0] !== 32'hfadffdaf)
$display ("ERROR task pif_wr_rd read data is %h ",data[0]);
$display(`CLOCK_COUNT, " : timer function ");
$finish;
end
endtask
task pif_wr4B;
begin
test_selected <= HIGH;
repeat (10) @(posedge clock);
config_rdram;
// load rdram
write_word(BUS_ADDRESS_DRAM, 3, 32'h0ad00da0);
write_word(BUS_ADDRESS_DRAM+4, 3, 32'h1ad11da1);
//write_word(BUS_ADDRESS_DRAM+8, 3, 32'h2ad22da2);
//write_word(BUS_ADDRESS_DRAM+12, 3, 32'h3ad33da3);
//write_word(BUS_ADDRESS_DRAM+16, 3, 32'h4ad00004);
//write_word(BUS_ADDRESS_DRAM+20, 3, 32'h5ad00005);
//write_word(BUS_ADDRESS_DRAM+24, 3, 32'h6ad00006);
//write_word(BUS_ADDRESS_DRAM+28, 3, 32'h7ad00007);
//write_word(BUS_ADDRESS_DRAM+32, 3, 32'h8ad00008);
//write_word(BUS_ADDRESS_DRAM+36, 3, 32'h9ad00009);
//write_word(BUS_ADDRESS_DRAM+40, 3, 32'haad0000a);
//write_word(BUS_ADDRESS_DRAM+44, 3, 32'hbad0000b);
//write_word(BUS_ADDRESS_DRAM+48, 3, 32'hcad0000c);
//write_word(BUS_ADDRESS_DRAM+52, 3, 32'hdad0000d);
//write_word(BUS_ADDRESS_DRAM+56, 3, 32'head0000e);
//write_word(BUS_ADDRESS_DRAM+60, 3, 32'hfadfffff);
// 4 Byte io write to pif
// writing to pif word address 1f0
write_word( 32'h1fc007c0, 3, 32'h0ad00da0);
read_word(BUS_ADDRESS_SI_STATUS, 3); // read status word
while (data[0] & 32'hfff) begin
read_word(BUS_ADDRESS_SI_STATUS, 3); // get next status for while eval
end
// read back the pif data to insure it is correct
read_word( 32'h1fc007c0, 3);
if (data[0] !== 32'h0ad00da0)
$display ("\t ERROR task pif_wr4B read data is %h ",data[0]);
$finish;
end
endtask
task pif_rd4Bcpu;
begin
test_selected <= HIGH;
repeat (10) @(posedge clock);
// 4 bit io read pif to cpu
// cpu should stall on this request.
// assumes loaded pif memory with content = address
read_word( 32'h1fc00000, 3);
if (data[0] !== 0)
$display ("ERROR task pif_rd4Bcpu read data is %h ",data[0]);
read_word( 32'h1fc00004, 3);
if (data[0] !== 32'h1)
$display ("ERROR task pif_rd4Bcpu read data is %h ",data[0]);
read_word( 32'h1fc007bc, 3);
if (data[0] !== 32'h1ef)
$display ("ERROR task pif_rd4Bcpu read data is %h ",data[0]);
read_word( 32'h1fc007c0, 3);
if (data[0] !== 32'h1f0)
$display ("ERROR task pif_rd4Bcpu read data is %h ",data[0]);
read_word( 32'h1fc007fc, 3);
if (data[0] !== 32'h1ff)
$display ("ERROR task pif_rd4Bcpu read data is %h ",data[0]);
$finish;
end
endtask
task pif_io_read_conflict;
// perform a dma transfer, while it is in progress
// issue a read to the reset exception vector
begin
test_selected <= HIGH;
repeat (10) @(posedge clock);
config_rdram;
// 64 bit transfer pif to dram
write_word(BUS_ADDRESS_SI_DRAM_ADDRESS, 3, BUS_ADDRESS_DRAM);
write_word(BUS_ADDRESS_SI_PIF_AD_RD64B, 3, 32'h1fc007c0);
// wait a while
p_valid <= LOW; // return p_valid to 0
repeat (200) @(posedge clock);
// read reset exception address
read_word( 32'h1fc00000, 3);
if (data[0] !== 0)
$display ("ERROR task pif_io_read_conflict read data is %h ",data[0]);
// confirm dma completed also
// assumes pif is loaded with data = address
read_word(BUS_ADDRESS_DRAM, 3);
// read data is left shifted 2 bits from write address
if (data[0] !== 32'h1f0)
$display ("ERROR task pif_io_read_conflict read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+4, 3);
if (data[0] !== 32'h1f1)
$display ("ERROR task pif_io_read_conflict read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+8, 3);
if (data[0] !== 32'h1f2)
$display ("ERROR task pif_io_read_conflict read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+12, 3);
if (data[0] !== 32'h1f3)
$display ("ERROR task pif_io_read_conflict read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+16, 3);
if (data[0] !== 32'h1f4)
$display ("ERROR task pif_io_read_conflict read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+20, 3);
if (data[0] !== 32'h1f5)
$display ("ERROR task pif_io_read_conflict read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+24, 3);
if (data[0] !== 32'h1f6)
$display ("ERROR task pif_io_read_conflict read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+28, 3);
if (data[0] !== 32'h1f7)
$display ("ERROR task pif_io_read_conflict read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+32, 3);
if (data[0] !== 32'h1f8)
$display ("ERROR task pif_io_read_conflict read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+36, 3);
if (data[0] !== 32'h1f9)
$display ("ERROR task pif_io_read_conflict read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+40, 3);
if (data[0] !== 32'h1fa)
$display ("ERROR task pif_io_read_conflict read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+44, 3);
if (data[0] !== 32'h1fb)
$display ("ERROR task pif_io_read_conflict read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+48, 3);
if (data[0] !== 32'h1fc)
$display ("ERROR task pif_io_read_conflict read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+52, 3);
if (data[0] !== 32'h1fd)
$display ("ERROR task pif_io_read_conflict read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+56, 3);
if (data[0] !== 32'h1fe)
$display ("ERROR task pif_io_read_conflict read data is %h ",data[0]);
read_word(BUS_ADDRESS_DRAM+60, 3);
if (data[0] !== 32'h1ff)
$display ("ERROR task pif_io_read_conflict read data is %h ",data[0]);
$finish;
end
endtask
task nmi_test;
begin
test_selected <= HIGH;
repeat (10) @(posedge clock);
config_rdram;
// must be run with +enable_nmi
// first transfer deaddead to 1fc007c0
// then rd64B 1fc007c0
write_word(32'h1fc007c0, 3, 32'hdeaddead);
read_word(BUS_ADDRESS_SI_STATUS, 3); // read status word
while (data[0] & 32'hfff) begin
read_word(BUS_ADDRESS_SI_STATUS, 3); // get next status for while eval
end
// pif is loaded, read the data to generate nmi
read_word(32'h1fc007c0, 3);
if (data[0] != 32'hdeaddead) begin
$display ("ERROR pif not properly loaded for nmi generation");
$finish;
end
// cause nmi to happen
write_word(BUS_ADDRESS_SI_DRAM_ADDRESS, 3, BUS_ADDRESS_DRAM);
write_word(BUS_ADDRESS_SI_PIF_AD_RD64B, 3, 32'h1fc007c0);
read_word(BUS_ADDRESS_SI_STATUS, 3); // read status word
while (data[0] & 32'hfff) begin
read_word(BUS_ADDRESS_SI_STATUS, 3); // get next status for
end
$finish;
end
endtask