rcp_attest_tab.v
20 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
///////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: rcp_attest_tab.v
// description: dumps out attest vector file
//
// designer: Tatsuya Fujii (NEC)
//
// modified: Tony DeLaurier
//
// date: 9/11/95
//
////////////////////////////////////////////////////////////////////////
module rcp_attest_tab();
`include "rdpcmd.vh"
`define rac_path reality.rcp_0.pad_0.left_pads.rac_0
integer tab_file_ptr; // output file pointer
integer idx; // bus bit counter
integer vector_count; // vector counter
reg smp_clk; // sample clock
reg gclk_smp_clk; // gclk sample clock
reg gclk_sample; // sampled gclk
reg freeze_vclk; // freeze_vclk flag
// delayed signals
reg pif_clock_curr;
reg reset_l_curr;
reg test_curr;
reg ad16_aleh_curr;
reg ad16_alel_curr;
reg ad16_read_curr;
reg ad16_write_curr;
reg [15:0] ad16_data_curr;
reg tst_ad16_enable_l_curr;
reg pif_rsp_curr;
reg pif_cmd_curr;
reg abus_data_curr;
reg abus_word_curr;
reg abus_clock_curr;
reg vbus_sync_curr;
reg vclk_enable_l_curr;
reg [6:0] vbus_data_curr;
reg int_curr;
reg p_valid_curr;
reg e_valid_curr;
reg e_ok_curr;
reg [31:0] sys_ad_curr;
reg sys_ad_enable_l_curr;
reg [4:0] sys_cmd_curr;
reg testckt_clk_curr;
reg testckt_dir_curr;
reg testckt_data_curr;
// delayed rac signals
reg [9:0] RData7_curr;
reg [9:0] RData6_curr;
reg [9:0] RData5_curr;
reg [9:0] RData4_curr;
reg [9:0] RData3_curr;
reg [9:0] RData2_curr;
reg [9:0] RData1_curr;
reg [9:0] RData0_curr;
reg BISTFlag_curr;
reg SCANOut_curr;
reg [3:0] BDSel_curr;
reg [3:0] BCSel_curr;
reg [3:0] BESel_curr;
reg [3:0] RDSel_curr;
reg [3:0] RCSel_curr;
reg Reset_curr;
reg [10:0] TData7_curr;
reg [10:0] TData6_curr;
reg [10:0] TData5_curr;
reg [10:0] TData4_curr;
reg [10:0] TData3_curr;
reg [10:0] TData2_curr;
reg [10:0] TData1_curr;
reg [10:0] TData0_curr;
reg BISTMode_curr;
reg IOSTMode_curr;
reg SCANMode_curr;
reg SCANClk_curr;
reg SCANEn_curr;
reg SCANIn_curr;
reg CCtlEn_curr;
reg CCtlLd_curr;
reg [5:0] CCtlI_curr;
reg PwrUp_curr;
reg ExtBE_curr;
reg StopR_curr;
reg StopT_curr;
reg ByPass_curr;
reg ByPSel_curr;
reg rclkASIC_curr;
reg tclkASIC_curr;
reg PhStall_curr;
initial vector_count = 0;
// freeze vclk
// initial
// begin
// if (!$test$plusargs("freeze_vclk_false") && $test$plusargs("rcp_attest_tab"))
// begin
// wait(`SYSTEM_READY);
// @(posedge reality.vbus_clock);
// $display($time," Freezing vclk");
// reality.cg_0.freeze_vclk = 1;
// end
// end
// define sample clock
initial
begin
smp_clk = 0;
@(negedge reality.rcp_0.mclock_pad);
if ($test$plusargs("rcp_attest_tab"))
forever @(posedge reality.rcp_0.mclock_pad)
begin
#14 smp_clk = 1;
#1 smp_clk = 0;
end
end // initial
// define gclk sample clock
initial
begin
gclk_smp_clk = 0;
@(negedge reality.rcp_0.mclock_pad);
if ($test$plusargs("rcp_attest_tab"))
forever @(posedge reality.rcp_0.mclock_pad)
begin
#4 gclk_smp_clk = 1;
#1 gclk_smp_clk = 0;
end
end // initial
// input write task
task printInput;
input value;
if (value === 0)
$fwrite(tab_file_ptr, "0");
else if (value === 1)
$fwrite(tab_file_ptr, "1");
else
$fwrite(tab_file_ptr, "0");
endtask // printInput
// output write task
task printOutput;
input value;
if (vector_count > 25) begin
if (value === 0)
$fwrite(tab_file_ptr, "L");
else if (value === 1)
$fwrite(tab_file_ptr, "H");
else
$fwrite(tab_file_ptr, "X");
end else
$fwrite(tab_file_ptr, "X");
endtask // printOutput
// bidir write task
task printBidir;
input value;
input curr_oe;
input next_oe;
if (((curr_oe === 0) && (next_oe === 1)) || (curr_oe === 1'bx) || (next_oe === 1'bx))
$fwrite(tab_file_ptr, "F");
else begin
if (curr_oe === 1) // chip driving
begin
if (value === 0)
$fwrite(tab_file_ptr, "L");
else if (value === 1)
$fwrite(tab_file_ptr, "H");
else
$fwrite(tab_file_ptr, "F");
end
else if (curr_oe === 0) // tester driving
begin
if (value === 0)
$fwrite(tab_file_ptr, "0");
else if (value === 1)
$fwrite(tab_file_ptr, "1");
else
$fwrite(tab_file_ptr, "0");
end
else // curr_oe unknown
$fwrite(tab_file_ptr, "F");
end // else
endtask // printBidir
initial begin
vclk_enable_l_curr <= 1'b1;
sys_ad_enable_l_curr <= 1'b1;
tst_ad16_enable_l_curr <= 1'b1;
end
// delay all signals of interest by one cycle
always @(posedge smp_clk)
begin
pif_clock_curr <= reality.pif_clock;
reset_l_curr <= reality.reset_l;
test_curr <= reality.test;
ad16_aleh_curr <= reality.ad16_aleh;
ad16_alel_curr <= reality.ad16_alel;
ad16_read_curr <= reality.ad16_read;
ad16_write_curr <= reality.ad16_write;
ad16_data_curr <= reality.ad16_data;
tst_ad16_enable_l_curr <= reality.rcp_0.tst_ad16_enable_l[0];
pif_rsp_curr <= reality.pif_rsp;
pif_cmd_curr <= reality.pif_cmd;
abus_data_curr <= reality.abus_data;
abus_word_curr <= reality.abus_word;
abus_clock_curr <= reality.abus_clock;
vbus_sync_curr <= reality.vbus_sync;
vclk_enable_l_curr <= reality.rcp_0.vclk_enable_l;
vbus_data_curr <= reality.vbus_data;
int_curr <= reality.int;
p_valid_curr <= reality.p_valid;
e_valid_curr <= reality.e_valid;
e_ok_curr <= reality.e_ok;
sys_ad_curr <= reality.sys_ad;
sys_ad_enable_l_curr <= reality.rcp_0.sys_ad_enable_l[0];
sys_cmd_curr <= reality.sys_cmd;
testckt_clk_curr <= reality.rcp_0.testckt_clk_pad;
testckt_dir_curr <= reality.rcp_0.testckt_dir_pad;
testckt_data_curr <= reality.rcp_0.testckt_data_pad;
RData7_curr <= `rac_path.RData7;
RData6_curr <= `rac_path.RData6;
RData5_curr <= `rac_path.RData5;
RData4_curr <= `rac_path.RData4;
RData3_curr <= `rac_path.RData3;
RData2_curr <= `rac_path.RData2;
RData1_curr <= `rac_path.RData1;
RData0_curr <= `rac_path.RData0;
BISTFlag_curr <= `rac_path.BISTFlag;
SCANOut_curr <= `rac_path.SCANOut;
BDSel_curr <= `rac_path.BDSel;
BCSel_curr <= `rac_path.BCSel;
BESel_curr <= `rac_path.BESel;
RDSel_curr <= `rac_path.RDSel;
RCSel_curr <= `rac_path.RCSel;
Reset_curr <= `rac_path.Reset;
TData7_curr <= `rac_path.TData7;
TData6_curr <= `rac_path.TData6;
TData5_curr <= `rac_path.TData5;
TData4_curr <= `rac_path.TData4;
TData3_curr <= `rac_path.TData3;
TData2_curr <= `rac_path.TData2;
TData1_curr <= `rac_path.TData1;
TData0_curr <= `rac_path.TData0;
BISTMode_curr <= `rac_path.BISTMode;
IOSTMode_curr <= `rac_path.IOSTMode;
SCANMode_curr <= `rac_path.SCANMode;
SCANClk_curr <= `rac_path.SCANClk;
SCANEn_curr <= `rac_path.SCANEn;
SCANIn_curr <= `rac_path.SCANIn;
CCtlEn_curr <= `rac_path.CCtlEn;
CCtlLd_curr <= `rac_path.CCtlLd;
CCtlI_curr <= `rac_path.CCtlI;
PwrUp_curr <= `rac_path.PwrUp;
ExtBE_curr <= `rac_path.ExtBE;
StopR_curr <= `rac_path.StopR;
StopT_curr <= `rac_path.StopT;
ByPass_curr <= `rac_path.ByPass;
ByPSel_curr <= `rac_path.ByPSel;
rclkASIC_curr <= `rac_path.rclkASIC;
tclkASIC_curr <= `rac_path.tclkASIC;
PhStall_curr <= `rac_path.PhStall;
end // always
// sample gclk
always @(posedge gclk_smp_clk)
begin
gclk_sample <= reality.rcp_0.rdp_0.cs.gclk;
end // always
reg [1:256*8] rcp_attest_fn;
initial
begin
if ($test$plusargs("rcp_attest_tab"))
begin
if ($getstr$plusarg("attest_name=", rcp_attest_fn) == 1)
tab_file_ptr = $fopen(rcp_attest_fn);
else
tab_file_ptr = $fopen("rcp_attest.vec");
forever @(negedge smp_clk)
begin
// dp command monitor
if ((reality.rcp_0.rdp_0.cs.start_prim || reality.rcp_0.rdp_0.cs.attr_valid) && gclk_sample)
begin
case (reality.rcp_0.rdp_0.cs.cmd)
noop : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: NOOP");
setcimg : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: SETCIMG");
setmimg : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: SETZIMG");
settimg : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: SETTIMG");
setcombine : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: SETCOMBINE");
setenvcolor : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: SETENVCOLOR");
setprimcolor : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: SETPRIMCOLOR");
setblendcolor : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: SETBLENDCOLOR");
setfogcolor : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: SETFOGCOLOR");
setfillcolor : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: SETFILLCOLOR");
fillrect : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: FILLRECT");
settile : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: SETTILE");
loadtile : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: LOADTILE");
loadblock : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: LOADBLOCK");
settilesize : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: SETTILESIZE");
loadtlut : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: LOADTLUT");
setrdpother : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: RDPSETOTHERMODE");
setprimdepth : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: SETPRIMDEPTH");
setscissor : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: SETSCISSOR");
setconvert : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: SETCONVERT");
setkeyr : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: SETKEYR");
setkeygb : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: SETKEYGB");
fullsync : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: RDPFULLSYNC");
tilesync : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: RDPTILESYNC");
pipesync : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: RDPPIPESYNC");
loadsync : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: RDPLOADSYNC");
texrectflip : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: TEXRECTFLIP");
texrect : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: TEXRECT");
trifill : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: G_TRI_FILL");
trishade : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: G_TRI_SHADE");
tritxtr : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: G_TRI_TXTR");
trishadetxtr : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: G_TRI_SHADE_TXTR");
trifillzbuff : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: G_TRI_FILL_ZBUFF");
trishadezbuff : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: G_TRI_SHADE_ZBUFF");
tritxtrzbuff : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: G_TRI_TXTR_ZBUFF");
trishadetxtrzbuff : $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: G_TRI_SHADE_TXTR_ZBUFF");
default: $fwrite(tab_file_ptr, "-- vector: %7d ", vector_count, "cmd: UNKNOWN %h", reality.rcp_0.rdp_0.cs.cmd);
endcase
$fdisplay(tab_file_ptr);
end
// The following order is same as pin definition of rcp_inner.
// mclock is (not) omitted.
printOutput(1'bx); // mclock_pad
printInput(reset_l_curr); // reset_l_pad
printInput(test_curr); // test_pad
printInput(p_valid_curr); // p_valid_pad
printOutput(e_valid_curr); // e_valid_pad
printOutput(e_ok_curr); // e_ok_pad
printOutput(int_curr); // int_pad
$fwrite(tab_file_ptr," ");
for (idx = 31; idx >= 0; idx = idx - 1)
printBidir(sys_ad_curr[idx], (!sys_ad_enable_l_curr), (!reality.rcp_0.sys_ad_enable_l[0])); // sys_ad_pad[31:0]
$fwrite(tab_file_ptr," ");
for (idx = 4; idx >= 0; idx = idx - 1)
printBidir(sys_cmd_curr[idx], (!sys_ad_enable_l_curr), (!reality.rcp_0.sys_ad_enable_l[0])); // sys_cmd_pad[4:0]
$fwrite(tab_file_ptr," ");
printOutput(ad16_aleh_curr); // ad16_aleh_pad
printOutput(ad16_alel_curr); // ad16_alel_pad
printOutput(ad16_read_curr); // ad16_read_pad
printOutput(ad16_write_curr); // ad16_write_pad
$fwrite(tab_file_ptr," ");
for (idx = 15; idx >= 0; idx = idx - 1)
printBidir(ad16_data_curr[idx], (!tst_ad16_enable_l_curr), (!reality.rcp_0.tst_ad16_enable_l[0])); // ad16_data_pad[15:0]
$fwrite(tab_file_ptr," ");
printInput(pif_rsp_curr); // pif_rsp_pad
printOutput(pif_cmd_curr); // pif_cmd_pad
printOutput(pif_clock_curr); // pif_clock_pad
printOutput(abus_data_curr); // abus_data_pad
printOutput(abus_word_curr); // abus_word_pad
printOutput(abus_clock_curr); // abus_clock_pad
$fwrite(tab_file_ptr," ");
for (idx = 6; idx >= 0; idx = idx - 1)
printOutput(vbus_data_curr[idx]); // vbus_data_pad[6:0]
$fwrite(tab_file_ptr," ");
printOutput(vbus_sync_curr); // vbus_sync_pad
printInput(1'b1); // vbus_clock_pad
// rbus_data_inAAA63 - rbus_data_inAAA0
$fwrite(tab_file_ptr," ");
for (idx = 7; idx >= 0; idx = idx - 1) printInput(RData0_curr[idx]);
$fwrite(tab_file_ptr," ");
for (idx = 7; idx >= 0; idx = idx - 1) printInput(RData1_curr[idx]);
$fwrite(tab_file_ptr," ");
for (idx = 7; idx >= 0; idx = idx - 1) printInput(RData2_curr[idx]);
$fwrite(tab_file_ptr," ");
for (idx = 7; idx >= 0; idx = idx - 1) printInput(RData3_curr[idx]);
$fwrite(tab_file_ptr," ");
for (idx = 7; idx >= 0; idx = idx - 1) printInput(RData4_curr[idx]);
$fwrite(tab_file_ptr," ");
for (idx = 7; idx >= 0; idx = idx - 1) printInput(RData5_curr[idx]);
$fwrite(tab_file_ptr," ");
for (idx = 7; idx >= 0; idx = idx - 1) printInput(RData6_curr[idx]);
$fwrite(tab_file_ptr," ");
for (idx = 7; idx >= 0; idx = idx - 1) printInput(RData7_curr[idx]);
$fwrite(tab_file_ptr," ");
// rbus_extend_inAAA7 - rbus_extend_inAAA0
printInput(RData0_curr[8]);
printInput(RData1_curr[8]);
printInput(RData2_curr[8]);
printInput(RData3_curr[8]);
printInput(RData4_curr[8]);
printInput(RData5_curr[8]);
printInput(RData6_curr[8]);
printInput(RData7_curr[8]);
$fwrite(tab_file_ptr," ");
printInput(RData0_curr[9]); // rbus_control_inAAA7
printInput(RData1_curr[9]); // pad_0_rbus_control_in_6_
printInput(RData2_curr[9]); // pad_0_rbus_control_in_5_
printInput(RData3_curr[9]); // pad_0_rbus_control_in_4_
printInput(RData4_curr[9]); // pad_0_rbus_control_in_3_
printInput(RData5_curr[9]); // rbus_control_inAAA6
printInput(RData6_curr[9]); // pad_0_rbus_control_in_1_
printInput(RData7_curr[9]); // pad_0_rbus_control_in_0_
$fwrite(tab_file_ptr," ");
// rac_sel_inAAA3 - rac_sel_inAAA0
for (idx = 3; idx >= 0; idx = idx - 1) printOutput(RDSel_curr[idx]);
$fwrite(tab_file_ptr," ");
// rbus_data_outAAA63 - rbus_data_outAAA0
for (idx = 7; idx >= 0; idx = idx - 1) printOutput(TData0_curr[idx]);
$fwrite(tab_file_ptr," ");
for (idx = 7; idx >= 0; idx = idx - 1) printOutput(TData1_curr[idx]);
$fwrite(tab_file_ptr," ");
for (idx = 7; idx >= 0; idx = idx - 1) printOutput(TData2_curr[idx]);
$fwrite(tab_file_ptr," ");
for (idx = 7; idx >= 0; idx = idx - 1) printOutput(TData3_curr[idx]);
$fwrite(tab_file_ptr," ");
for (idx = 7; idx >= 0; idx = idx - 1) printOutput(TData4_curr[idx]);
$fwrite(tab_file_ptr," ");
for (idx = 7; idx >= 0; idx = idx - 1) printOutput(TData5_curr[idx]);
$fwrite(tab_file_ptr," ");
for (idx = 7; idx >= 0; idx = idx - 1) printOutput(TData6_curr[idx]);
$fwrite(tab_file_ptr," ");
for (idx = 7; idx >= 0; idx = idx - 1) printOutput(TData7_curr[idx]);
$fwrite(tab_file_ptr," ");
// rbus_extend_outAAA7 - rbus_extend_outAAA0
printOutput(TData0_curr[8]);
printOutput(TData1_curr[8]);
printOutput(TData2_curr[8]);
printOutput(TData3_curr[8]);
printOutput(TData4_curr[8]);
printOutput(TData5_curr[8]);
printOutput(TData6_curr[8]);
printOutput(TData7_curr[8]);
$fwrite(tab_file_ptr," ");
// rbus_control_outAAA7 - rbus_control_outAAA0
printOutput(TData0_curr[9]);
printOutput(TData1_curr[9]);
printOutput(TData2_curr[9]);
printOutput(TData3_curr[9]);
printOutput(TData4_curr[9]);
printOutput(TData5_curr[9]);
printOutput(TData6_curr[9]);
printOutput(TData7_curr[9]);
$fwrite(tab_file_ptr," ");
// rbus_enable_outAAA7 - rbus_enable_outAAA0
printOutput(TData0_curr[10]);
printOutput(TData1_curr[10]);
printOutput(TData2_curr[10]);
printOutput(TData3_curr[10]);
printOutput(TData4_curr[10]);
printOutput(TData5_curr[10]);
printOutput(TData6_curr[10]);
printOutput(TData7_curr[10]);
$fwrite(tab_file_ptr," ");
// rac_sel_outAAA3 - rac_sel_outAAA0
for (idx = 3; idx >= 0; idx = idx - 1) printOutput(BDSel_curr[idx]);
$fwrite(tab_file_ptr," ");
// c_ctl_iAAA5 - c_ctl_iAAA0
for (idx = 5; idx >= 0; idx = idx - 1) printOutput(CCtlI_curr[idx]);
$fwrite(tab_file_ptr," ");
printOutput(CCtlEn_curr); // c_ctl_en
printOutput(CCtlLd_curr); // c_ctl_ld
printOutput(StopR_curr); // stop_r
printOutput(StopT_curr); // stop_t
printOutput(Reset_curr); // rac_reset
printOutput(PwrUp_curr); // pwr_up
printOutput(ExtBE_curr); // ext_be
printOutput(ByPass_curr); // by_pass
printOutput(BISTMode_curr); // bist_mode
printOutput(IOSTMode_curr); // iost_mode
printInput(BISTFlag_curr); // bist_flag
printInput(testckt_clk_curr); // testckt_clk_pad
printInput(testckt_dir_curr); // testckt_dir_pad
printBidir(testckt_data_curr, (!testckt_dir_curr), (!reality.rcp_0.testckt_dir_pad)); // testckt_data_pad
printInput(1'b1); // syn_clk
printInput(1'b1); // syn_clk_fd
printOutput(1'bx); // syn_clk_in
$fwrite(tab_file_ptr, " -- %d ", vector_count);
vector_count = vector_count + 1;
$fwrite(tab_file_ptr, $realtime, " ");
$fdisplay(tab_file_ptr);
end // forever
end // if
end // initial
endmodule // rcp_attest_tab