rcp_full_tssi.v
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////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: rcp_full_tssi.v
// description: dumps out rcp tssi file
//
// designer: Tony DeLaurier
// date: 4/25/95
//
////////////////////////////////////////////////////////////////////////
module rcp_full_tssi();
integer tab_file_ptr; // output file pointer
integer idx; // bus bit counter
integer vector_count; // vector counter
reg smp_clk; // sample clock
// delayed signals
reg pif_clock_curr;
reg reset_l_curr;
reg test_curr;
reg ad16_aleh_curr;
reg ad16_alel_curr;
reg ad16_read_curr;
reg ad16_write_curr;
reg [15:0] ad16_data_curr;
reg tst_ad16_enable_l_curr;
reg pif_rsp_curr;
reg pif_cmd_curr;
reg abus_data_curr;
reg abus_word_curr;
reg abus_clock_curr;
reg vbus_sync_curr;
reg vclk_enable_l_curr;
reg [6:0] vbus_data_curr;
reg int_curr;
reg p_valid_curr;
reg e_valid_curr;
reg e_ok_curr;
reg [31:0] sys_ad_curr;
reg sys_ad_enable_l_curr;
reg [4:0] sys_cmd_curr;
initial vector_count = 0;
// define sample clock
initial
begin
smp_clk = 0;
@(negedge reality.rcp_0.mclock_pad);
if ($test$plusargs("rcp_full_tssi"))
forever @(posedge reality.rcp_0.mclock_pad)
begin
#14 smp_clk = 1;
#1 smp_clk = 0;
end
end // initial
// input write task
task printInput;
input value;
if (value === 0)
$fwrite(tab_file_ptr, "D");
else if (value === 1)
$fwrite(tab_file_ptr, "U");
else
$fwrite(tab_file_ptr, "D");
endtask // printInput
// output write task
task printOutput;
input value;
if (vector_count > 25) begin
if (value === 0)
$fwrite(tab_file_ptr, "L");
else if (value === 1)
$fwrite(tab_file_ptr, "H");
else
$fwrite(tab_file_ptr, "X");
end else
$fwrite(tab_file_ptr, "X");
endtask // printOutput
// bidir write task
task printBidir;
input value;
input curr_oe;
input next_oe;
if (((curr_oe === 0) && (next_oe === 1)) || (curr_oe === 1'bx) || (next_oe === 1'bx))
$fwrite(tab_file_ptr, "Z");
else begin
if (curr_oe === 1) // chip driving
begin
if (value === 0)
$fwrite(tab_file_ptr, "L");
else if (value === 1)
$fwrite(tab_file_ptr, "H");
else
$fwrite(tab_file_ptr, "X");
end
else if (curr_oe === 0) // tester driving
begin
if (value === 0)
$fwrite(tab_file_ptr, "D");
else if (value === 1)
$fwrite(tab_file_ptr, "U");
else
$fwrite(tab_file_ptr, "D");
end
else // curr_oe unknown
$fwrite(tab_file_ptr, "Z");
end // else
endtask // printBidir
initial begin
vclk_enable_l_curr <= 1'b1;
sys_ad_enable_l_curr <= 1'b1;
tst_ad16_enable_l_curr <= 1'b1;
end
// delay all signals of interest by one cycle
always @(posedge smp_clk)
begin
pif_clock_curr <= reality.pif_clock;
reset_l_curr <= reality.reset_l;
test_curr <= reality.test;
ad16_aleh_curr <= reality.ad16_aleh;
ad16_alel_curr <= reality.ad16_alel;
ad16_read_curr <= reality.ad16_read;
ad16_write_curr <= reality.ad16_write;
ad16_data_curr <= reality.ad16_data;
tst_ad16_enable_l_curr <= reality.rcp_0.tst_ad16_enable_l[0];
pif_rsp_curr <= reality.pif_rsp;
pif_cmd_curr <= reality.pif_cmd;
abus_data_curr <= reality.abus_data;
abus_word_curr <= reality.abus_word;
abus_clock_curr <= reality.abus_clock;
vbus_sync_curr <= reality.vbus_sync;
vclk_enable_l_curr <= reality.rcp_0.vclk_enable_l;
vbus_data_curr <= reality.vbus_data;
int_curr <= reality.int;
p_valid_curr <= reality.p_valid;
e_valid_curr <= reality.e_valid;
e_ok_curr <= reality.e_ok;
sys_ad_curr <= reality.sys_ad;
sys_ad_enable_l_curr <= reality.rcp_0.sys_ad_enable_l[0];
sys_cmd_curr <= reality.sys_cmd;
end // always
reg [1:256*8] rcp_tssi_fn;
initial
begin
if ($test$plusargs("rcp_full_tssi"))
begin
if ($getstr$plusarg("tssi_name=", rcp_tssi_fn) == 1)
tab_file_ptr = $fopen(rcp_tssi_fn);
else
tab_file_ptr = $fopen("rcp_full_tssi.slf");
forever @(posedge smp_clk)
begin
$fwrite(tab_file_ptr, "%d.0 ", vector_count * 100);
vector_count = vector_count + 1;
printInput(1'b1); // mclock clock
printInput(1'b1); // vclk_pad
printInput(test_curr); // test_pad
printInput(reset_l_curr); // reset_l_pad
printOutput(pif_clock_curr); // pif_clock_pad
printOutput(ad16_aleh_curr); // ad16_aleh_pad
printOutput(ad16_alel_curr); // ad16_alel_pad
printOutput(ad16_read_curr); // ad16_read_pad
printOutput(ad16_write_curr); // ad16_write_pad
for (idx = 15; idx >= 0; idx = idx - 1) printBidir( ad16_data_curr[idx],
!tst_ad16_enable_l_curr,
!reality.rcp_0.tst_ad16_enable_l[0]); // ad16_data_pad[15:0]
printInput(pif_rsp_curr); // pif_rsp_pad
printOutput(pif_cmd_curr); // pif_cmd_pad
printOutput(abus_data_curr); // abus_data_pad
printOutput(abus_word_curr); // abus_word_pad
printOutput(abus_clock_curr); // abus_clock_pad
printOutput(vbus_sync_curr); // vbus_sync_pad
for (idx = 6; idx >= 0; idx = idx - 1) printOutput(vbus_data_curr[idx]); // vbus_data_pad[6:0]
printOutput(int_curr); // int_pad
printInput(p_valid_curr); // p_valid_pad
printOutput(e_valid_curr); // e_valid_pad
printOutput(e_ok_curr); // e_ok_pad
for (idx = 31; idx >= 0; idx = idx - 1) printBidir( sys_ad_curr[idx],
!sys_ad_enable_l_curr,
!reality.rcp_0.sys_ad_enable_l[0]); // sys_ad_pad[31:0]
for (idx = 4; idx >= 0; idx = idx - 1) printBidir( sys_cmd_curr[idx],
!sys_ad_enable_l_curr,
!reality.rcp_0.sys_ad_enable_l[0]); // sys_cmd_pad[4:0]
$fdisplay(tab_file_ptr);
end // forever
end // if
end // initial
endmodule // rcp_full_tssi