rcp_test_tab.v
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module rcp_test_tab();
`define RDRAM0 reality.rdram_0.rdram_near_model_0
`define RDRAM1 reality.rdram_1.rdram_near_model_0
integer tab_file_ptr;
integer vector_count;
integer idx;
initial vector_count = 0;
reg [31:0] sys_ad;
reg [4:0] sys_cmd;
reg [15:0] ad16_data;
reg bus_ctrl_rac_enable;
reg [8:0] bus_data_rac_enable;
reg smp_clk;
initial
begin
smp_clk = 1;
#1.8 smp_clk = 0;
forever
begin
#2 smp_clk = ~smp_clk;
end // forever
end // initial
reg sample;
initial sample = 1;
always @(smp_clk) sample = #0.1 smp_clk;
wire rdram_drive_ctrl;
wire [8:0] rdram_drive_data;
reg rdram_drive_ctrl_d1;
reg [8:0] rdram_drive_data_d1;
initial
begin
rdram_drive_ctrl_d1 <= 0;
rdram_drive_data_d1[0] <= 0; rdram_drive_data_d1[1] <= 0; rdram_drive_data_d1[2] <= 0;
rdram_drive_data_d1[3] <= 0; rdram_drive_data_d1[4] <= 0; rdram_drive_data_d1[5] <= 0;
rdram_drive_data_d1[6] <= 0; rdram_drive_data_d1[7] <= 0; rdram_drive_data_d1[8] <= 0;
end
`ifdef RDRAM_1_PRESENT
assign rdram_drive_ctrl = (`RDRAM0.BusCtrl_drive ===1 & `RDRAM1.BusCtrl_drive ===1) ? 0 : 1;
assign rdram_drive_data[0] = (`RDRAM0.BusData_drive[0]===1 & `RDRAM1.BusData_drive[0]===1) ? 0 : 1;
assign rdram_drive_data[1] = (`RDRAM0.BusData_drive[1]===1 & `RDRAM1.BusData_drive[1]===1) ? 0 : 1;
assign rdram_drive_data[2] = (`RDRAM0.BusData_drive[2]===1 & `RDRAM1.BusData_drive[2]===1) ? 0 : 1;
assign rdram_drive_data[3] = (`RDRAM0.BusData_drive[3]===1 & `RDRAM1.BusData_drive[3]===1) ? 0 : 1;
assign rdram_drive_data[4] = (`RDRAM0.BusData_drive[4]===1 & `RDRAM1.BusData_drive[4]===1) ? 0 : 1;
assign rdram_drive_data[5] = (`RDRAM0.BusData_drive[5]===1 & `RDRAM1.BusData_drive[5]===1) ? 0 : 1;
assign rdram_drive_data[6] = (`RDRAM0.BusData_drive[6]===1 & `RDRAM1.BusData_drive[6]===1) ? 0 : 1;
assign rdram_drive_data[7] = (`RDRAM0.BusData_drive[7]===1 & `RDRAM1.BusData_drive[7]===1) ? 0 : 1;
assign rdram_drive_data[8] = (`RDRAM0.BusData_drive[8]===1 & `RDRAM1.BusData_drive[8]===1) ? 0 : 1;
`else
assign rdram_drive_ctrl = (`RDRAM0.BusCtrl_drive ===1) ? 0 : 1;
assign rdram_drive_data[0] = (`RDRAM0.BusData_drive[0]===1) ? 0 : 1;
assign rdram_drive_data[1] = (`RDRAM0.BusData_drive[1]===1) ? 0 : 1;
assign rdram_drive_data[2] = (`RDRAM0.BusData_drive[2]===1) ? 0 : 1;
assign rdram_drive_data[3] = (`RDRAM0.BusData_drive[3]===1) ? 0 : 1;
assign rdram_drive_data[4] = (`RDRAM0.BusData_drive[4]===1) ? 0 : 1;
assign rdram_drive_data[5] = (`RDRAM0.BusData_drive[5]===1) ? 0 : 1;
assign rdram_drive_data[6] = (`RDRAM0.BusData_drive[6]===1) ? 0 : 1;
assign rdram_drive_data[7] = (`RDRAM0.BusData_drive[7]===1) ? 0 : 1;
assign rdram_drive_data[8] = (`RDRAM0.BusData_drive[8]===1) ? 0 : 1;
`endif
always @(sample)
begin
rdram_drive_ctrl_d1 <= rdram_drive_ctrl;
rdram_drive_data_d1[0] <= rdram_drive_data[0];
rdram_drive_data_d1[1] <= rdram_drive_data[1];
rdram_drive_data_d1[2] <= rdram_drive_data[2];
rdram_drive_data_d1[3] <= rdram_drive_data[3];
rdram_drive_data_d1[4] <= rdram_drive_data[4];
rdram_drive_data_d1[5] <= rdram_drive_data[5];
rdram_drive_data_d1[6] <= rdram_drive_data[6];
rdram_drive_data_d1[7] <= rdram_drive_data[7];
rdram_drive_data_d1[8] <= rdram_drive_data[8];
end
always @(smp_clk)
begin
for (idx=0; idx<32; idx=idx+1)
if ((reality.sys_ad[idx]===1'bx || reality.sys_ad[idx]===1'bz) &&
reality.rcp_0.sys_ad_enable_l[0])
sys_ad[idx] = 1'b0;
else
sys_ad[idx] = reality.sys_ad[idx];
for (idx=0; idx<5; idx=idx+1)
if ((reality.sys_cmd[idx]===1'bx || reality.sys_cmd[idx]===1'bz) &&
reality.rcp_0.sys_ad_enable_l[0])
sys_cmd[idx] = 1'b0;
else
sys_cmd[idx] = reality.sys_cmd[idx];
for (idx=0; idx<16; idx=idx+1)
if ((reality.ad16_data[idx]===1'bx || reality.ad16_data[idx]===1'bz) &&
reality.rcp_0.tst_ad16_enable_l[0])
ad16_data[idx] = 1'b0;
else
ad16_data[idx] = reality.ad16_data[idx];
bus_ctrl_rac_enable = !(rdram_drive_ctrl || rdram_drive_ctrl_d1);
for (idx=0; idx<9; idx=idx+1)
bus_data_rac_enable[idx] = !(rdram_drive_data[idx] || rdram_drive_data_d1[idx]);
end
initial
begin
if ($test$plusargs("qsim_test_capture_rcp"))
begin
tab_file_ptr = $fopen("test_capture_rcp.tab");
// dump out header
$fwrite(tab_file_ptr,
"clock @DC 1(50) 0(50) \n",
"tx_clk @C 1(100) 0(100) \n",
"# \n",
"# \n",
"reset_l_pad @I @E 20 @C clock \n",
"test_pad @I @E 20 @C clock \n",
"# \n",
"p_valid_pad @I @E 20 @C clock \n",
"v_ref @I @E 20 @C clock \n",
"c_ctl_pgm @I @E 20 @C clock \n",
"pif_rsp_pad @I @E 20 @C clock \n",
"# \n",
"mclock_pad @O @S 90 @C clock \n",
"e_valid_pad @O @S 90 @C clock \n",
"e_ok_pad @O @S 90 @C clock \n",
"int_pad @O @S 90 @C clock \n",
"rx_clk @O @S 90 @C clock \n",
"ad16_aleh_pad @O @S 90 @C clock \n",
"ad16_alel_pad @O @S 90 @C clock \n",
"ad16_read_pad @O @S 90 @C clock \n",
"ad16_write_pad @O @S 90 @C clock \n",
"pif_cmd_pad @O @S 90 @C clock \n",
"pif_clock_pad @O @S 90 @C clock \n",
"abus_data_pad @O @S 90 @C clock \n",
"abus_word_pad @O @S 90 @C clock \n",
"abus_clock_pad @O @S 90 @C clock \n",
"vbus_data_pad[6:0] @O @S 90 @C clock \n",
"vbus_sync_pad @O @S 90 @C clock \n",
"# \n",
"sys_ad_pad[31:0] @B sys_ad_oe_l_dummy 0 @E 20 @S 90 @C clock \n",
"sys_ad_enable_l[4:0] @O @S 90 @C clock \n",
"sys_ad_oe_l_dummy @I @E 0 @C clock \n",
"# \n",
"sys_cmd_pad[4:0] @B sys_cmd_oe_l_dummy 0 @E 20 @S 90 @C clock \n",
"sys_cmd_oe_l_dummy @I @E 0 @C clock \n",
"# \n",
"ad16_data_pad[15:0] @B ad16_oe_l_dummy 0 @E 20 @S 90 @C clock \n",
"tst_ad16_enable_l[1:0] @O @S 90 @C clock \n",
"ad16_oe_l_dummy @I @E 0 @C clock \n",
"# \n",
"vclk_pad @B vclk_oe_l_dummy 0 @E 30 @S 90 @C clock \n",
"vclk_enable_l @O @S 90 @C clock \n",
"vclk_oe_l_dummy @I @E 0 @C clock \n",
"# rambus interface \n",
"bus_ctrl_rac @I @E 20 @C clock \n",
"bus_data_rac[8] @I @E 20 @C clock \n",
"bus_data_rac[7] @I @E 20 @C clock \n",
"bus_data_rac[6] @I @E 20 @C clock \n",
"bus_data_rac[5] @I @E 20 @C clock \n",
"bus_data_rac[4] @I @E 20 @C clock \n",
"bus_data_rac[3] @I @E 20 @C clock \n",
"bus_data_rac[2] @I @E 20 @C clock \n",
"bus_data_rac[1] @I @E 20 @C clock \n",
"bus_data_rac[0] @I @E 20 @C clock \n",
"# \n",
"bus_enable_rac @O @S 90 @C clock \n",
"bus_ctrl_rac_o @O @S 90 @C clock \n",
"bus_data_rac_o[8:0] @O @S 90 @C clock \n",
"# \n",
"bus_ctrl_enable @I @E 5 @C clock \n",
"bus_data_enable[8:0] @I @E 5 @C clock \n"
);
$fdisplay(tab_file_ptr);
forever @(sample) begin
if (vector_count >= 0 && !(vector_count % 100))
$fdisplayh(tab_file_ptr, "# vector %0d", vector_count);
vector_count = vector_count + 1;
$fwrite(tab_file_ptr,
"%b ", reality.reset_l,
"%b ", reality.test,
"%b ", reality.p_valid,
"%b ", reality.v_ref,
"%b ", reality.c_ctl_pgm,
"%b ", reality.pif_rsp,
"%b ", reality.clock,
"%b ", reality.e_valid,
"%b ", reality.e_ok,
"%b ", reality.int,
"%b ", reality.tx_clk,
"%b ", reality.ad16_aleh,
"%b ", reality.ad16_alel,
"%b ", reality.ad16_read,
"%b ", reality.ad16_write,
"%b ", reality.pif_cmd,
"%b ", reality.pif_clock,
"%b ", reality.abus_data,
"%b ", reality.abus_word,
"%b ", reality.abus_clock,
"0x%h ", reality.vbus_data[6:0],
"%b ", reality.vbus_sync,
"0x%h ", sys_ad[31:0],
"0x%h ", reality.rcp_0.sys_ad_enable_l[4:0],
"%b ", reality.rcp_0.sys_ad_enable_l[0],
"0x%h ", sys_cmd[4:0],
"%b ", reality.rcp_0.sys_ad_enable_l[0],
"0x%h ", ad16_data[15:0],
"0x%h ", reality.rcp_0.tst_ad16_enable_l[1:0],
"%b ", reality.rcp_0.tst_ad16_enable_l[0],
"%b ", reality.vbus_clock,
"%b ", reality.rcp_0.vclk_enable_l,
"%b ", reality.rcp_0.vclk_enable_l,
`ifdef RDRAM_1_PRESENT
"%s ", `RDRAM0.BusCtrl_drive & `RDRAM1.BusCtrl_drive ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[8] & `RDRAM1.BusData_drive[8] ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[7] & `RDRAM1.BusData_drive[7] ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[6] & `RDRAM1.BusData_drive[6] ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[5] & `RDRAM1.BusData_drive[5] ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[4] & `RDRAM1.BusData_drive[4] ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[3] & `RDRAM1.BusData_drive[3] ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[2] & `RDRAM1.BusData_drive[2] ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[1] & `RDRAM1.BusData_drive[1] ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[0] & `RDRAM1.BusData_drive[0] ? "z" : "0"," ",
`else
"%s ", `RDRAM0.BusCtrl_drive ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[8] ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[7] ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[6] ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[5] ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[4] ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[3] ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[2] ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[1] ? "z" : "0",
"%s ", `RDRAM0.BusData_drive[0] ? "z" : "0"," ",
`endif
"%b ", reality.bus_enable,
"%b ", reality.bus_ctrl,
"0x%h ", reality.bus_data," ",
"%b ", bus_ctrl_rac_enable,
"0x%h ", bus_data_rac_enable
);
$fdisplay(tab_file_ptr);
end //forever
end //if
end // initial
endmodule