si_tab.v
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////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: si_tab.v
// description: dumps out si i/o .tab file
//
// designer: Tony DeLaurier
// date: 12/05/94
//
////////////////////////////////////////////////////////////////////////
module si_tab();
integer tab_file_ptr;
// open tab file and dump header
initial
begin
tab_file_ptr = $fopen("si000.tab");
// dump out header
$fwriteh(tab_file_ptr, "#\n");
$fwriteh(tab_file_ptr, "# si tab file\n");
$fwriteh(tab_file_ptr, "#\n");
$fwriteh(tab_file_ptr, "clk @C 1(8) 0(8)\n");
$fwriteh(tab_file_ptr, "reset_l @I @E 2 @C clk\n");
$fwriteh(tab_file_ptr, "cbus_read_enable @I @E 2 @C clk\n");
$fwriteh(tab_file_ptr, "cbus_write_enable @I @E 2 @C clk\n");
$fwriteh(tab_file_ptr, "cbus_select[1:0] @I @E 2 @C clk\n");
$fwriteh(tab_file_ptr, "cbus_command[2:0] @I @E 2 @C clk\n");
$fwriteh(tab_file_ptr, "dma_start @I @E 2 @C clk\n");
$fwriteh(tab_file_ptr, "dbus_enable @I @E 2 @C clk\n");
$fwriteh(tab_file_ptr, "dma_grant @I @E 2 @C clk\n");
$fwriteh(tab_file_ptr, "read_grant @I @E 2 @C clk\n");
$fwriteh(tab_file_ptr, "pif_rsp @I @E 2 @C clk\n");
$fwriteh(tab_file_ptr, "dma_request @O @S 15 @C clk\n");
$fwriteh(tab_file_ptr, "read_request @O @S 15 @C clk\n");
$fwriteh(tab_file_ptr, "interrupt @O @S 15 @C clk\n");
$fwriteh(tab_file_ptr, "pif_cmd @O @S 15 @C clk\n");
$fwriteh(tab_file_ptr, "pif_clk @O @S 15 @C clk\n");
$fwriteh(tab_file_ptr, "cbus_data[31:0] @B cbus_data_oe 1 @E 5 @S 15 @C clk\n");
$fwriteh(tab_file_ptr, "cbus_data_oe @O @S 15 @C clk\n");
$fwriteh(tab_file_ptr, "cbus_dummy @I @E 0 @C clk\n");
$fwriteh(tab_file_ptr, "dbus_data[63:0] @B dbus_data_oe 1 @E 5 @S 15 @C clk\n");
$fwriteh(tab_file_ptr, "dbus_data_oe @O @S 15 @C clk\n");
$fwriteh(tab_file_ptr, "dbus_dummy @I @E 0 @C clk\n");
$fwriteh(tab_file_ptr, "\n");
end // initial
// dump si at pos edge of clk
always @(posedge reality.rcp_0.si_0.clk)
begin
$fwriteh(tab_file_ptr,
reality.rcp_0.si_0.reset_l,," ",
reality.rcp_0.si_0.cbus_read_enable,,
reality.rcp_0.si_0.cbus_write_enable,,
"0x", reality.rcp_0.si_0.cbus_select,,
"0x", reality.rcp_0.si_0.cbus_command,,
reality.rcp_0.si_0.dma_start,,
reality.rcp_0.si_0.dbus_enable,,
reality.rcp_0.si_0.dma_grant,,
reality.rcp_0.si_0.read_grant,,
reality.rcp_0.si_0.pif_rsp,," ",
reality.rcp_0.si_0.dma_request,,
reality.rcp_0.si_0.read_request,,
reality.rcp_0.si_0.interrupt,,
reality.rcp_0.si_0.pif_cmd,,
reality.rcp_0.si_0.pif_clk,," ",
"0x", reality.rcp_0.si_0.cbus_data,,
reality.rcp_0.si_0.cbus_write_enable,,
reality.rcp_0.si_0.cbus_write_enable,,
"0x", reality.rcp_0.si_0.dbus_data,,
reality.rcp_0.si_0.dbus_enable,,
reality.rcp_0.si_0.dbus_enable,,
"\n");
end // always
endmodule // si_tab