task config_rdram;
	begin
		// set reset mode
		@(posedge clock);
		write_word(BUS_ADDRESS_RI_MODE, 3, {LOW, LOW, RDRAM_RESET_MODE});
		// write the RI current control register
		//write_word(BUS_ADDRESS_RI_CONFIG, 3, 'b0_001000);
		write_word(BUS_ADDRESS_RI_CONFIG, 3, 'b0_011111); // By Kishor to make full speed test work on HP. 

		// wait for the current register to propogate
		p_valid <= LOW;
		repeat (32) @(posedge clock);

		// load current control register
		write_word(BUS_ADDRESS_RI_CURRENT_LOAD, 3, 0);

		// set RAC transmit and receive selects
		write_word(BUS_ADDRESS_RI_SELECT, 3, {4'b0001, 4'b0100});

		// wait for reset_l to take hold
		p_valid <= LOW;
		repeat (80) @(posedge clock);

		// set standby mode
		write_word(BUS_ADDRESS_RI_MODE, 3, {HIGH, HIGH, RDRAM_STANDBY_MODE});

		// use the MI init mode to init the RDRAM delay register
		write_word(BUS_ADDRESS_MI_INIT_MODE, 3, {2'b10, 7'd15});
		write_word(BUS_ADDRESS_RDRAM_DELAY | RDRAM_GLOBAL_CONFIG, 3,
		  'h18_08_28_38);

		write_rdram_reg(BUS_ADDRESS_RDRAM_RAS_INTERVAL | RDRAM_GLOBAL_CONFIG,
		  {8'd1, 8'd7, 8'd10, 8'd4} );

		`ifdef RDRAM_1_PRESENT
		// initialize RDRAM 1
		write_rdram_reg(BUS_ADDRESS_RDRAM_DEVICE_ID,
		  {RDRAM_1_DEVICE_ID, 2'b0, 8'b0, 8'b0, 8'b0} );

		write_rdram_reg(BUS_ADDRESS_RDRAM_MODE + RDRAM_1_CONFIG,
		  {8'b0000_0010, 8'b0, 8'b0, 8'b0} );

		// validate the banks before refreshing begins
		read_word(BUS_ADDRESS_DRAM + 'h20_0000, 3);
		read_word(BUS_ADDRESS_DRAM + 'h30_0000, 3);
		`endif

		`ifdef RDRAM_1MBYTE_PRESENT
		// initialize RDRAM 5 (1 Mbyte)
		write_rdram_reg(BUS_ADDRESS_RDRAM_DEVICE_ID,
		  {RDRAM_5_DEVICE_ID, 2'b0, 8'b0, 8'b0, 8'b0} );

		write_rdram_reg(BUS_ADDRESS_RDRAM_MODE + RDRAM_5_CONFIG,
		  {8'b1100_0110, 8'b1000_0000, 8'b0, 8'b0} );

		// validate the banks before refreshing begins
		read_word(BUS_ADDRESS_DRAM + 'h50_0000, 3);

		// initialize RDRAM 4 (1 Mbyte)
		write_rdram_reg(BUS_ADDRESS_RDRAM_DEVICE_ID,
		  {RDRAM_4_DEVICE_ID, 2'b0, 8'b0, 8'b0, 8'b0} );

		write_rdram_reg(BUS_ADDRESS_RDRAM_MODE + RDRAM_4_CONFIG,
		  {8'b1100_0110, 8'b1000_0000, 8'b0, 8'b0} );

		// validate the banks before refreshing begins
		read_word(BUS_ADDRESS_DRAM + 'h40_0000, 3);
		`endif

		`ifdef RDRAM_0_PRESENT
		// initialize RDRAM 0
		write_rdram_reg(BUS_ADDRESS_RDRAM_DEVICE_ID,
		  {RDRAM_0_DEVICE_ID, 2'b0, 8'b0, 8'b0, 8'b0} );

		write_rdram_reg(BUS_ADDRESS_RDRAM_MODE + RDRAM_0_CONFIG,
		  {8'b0000_0010, 8'b0, 8'b0, 8'b0} );

		// validate the banks before refreshing begins
		read_word(BUS_ADDRESS_DRAM + 'h00_0000, 3);
		read_word(BUS_ADDRESS_DRAM + 'h10_0000, 3);
		`endif

		// enable refresh
		write_word(BUS_ADDRESS_RI_REFRESH, 3, 'b0011_1_1_0_00110100_00110010);

		// wait for the post-write-reg delay
		p_valid <= LOW;
		repeat (10) @(posedge clock);
		end
	endtask


/*** support tasks ***/

task write_rdram_reg;
	input [31:0] address;
	input [31:0] data;

	begin
		write_word(address, 3, data);
		p_valid <= LOW;
		@(posedge clock);
		end
	endtask


task write_word;
	input [31:0] address;
	input [1:0] size;
	input [31:0] data;

	begin
		p_valid <= HIGH;
		sys_cmd_out <= SYS_CMD_WRITE_WORD | size;
		sys_ad_out <= address;
		@(posedge clock);
		while (!e_ok) @(posedge clock);

		sys_cmd_out <= SYS_CMD_DATA_LAST;
		sys_ad_out <= data;

		if (monitor) begin
			$display(`CLOCK_COUNT, " : R4200 write - %h @ %h",
				data, address);
			end
		@(posedge clock);

		while (!e_ok) begin
			// canceled cycle
			sys_cmd_out <= SYS_CMD_WRITE_WORD | size;
			sys_ad_out <= address;

			if (monitor) begin
				$display(`CLOCK_COUNT, " : R4200 write - canceled");
				end

			@(posedge clock);

			while (!e_ok) @(posedge clock);

			sys_cmd_out <= SYS_CMD_DATA_LAST;
			sys_ad_out <= data;

			if (monitor) begin
				$display(`CLOCK_COUNT, " : R4200 write - %h @ %h",
					data, address);
				end

			@(posedge clock);
			end
		end
	endtask


task write_block;
	input [31:0] address;
	input [1:0] size;

	integer i;
	begin
		p_valid <= HIGH;
		sys_cmd_out <= SYS_CMD_WRITE_BLOCK | size;
		sys_ad_out <= address;
		@(posedge clock);

		while (!e_ok) @(posedge clock);

		sys_cmd_out <= SYS_CMD_DATA_NEXT;
		sys_ad_out <= data[0];

		if (monitor) begin
			$display(`CLOCK_COUNT, " : R4200 write[%h] - %h @ %h",
				4'd0, data[0], address);
			end

		@(posedge clock);

		while (!e_ok) begin
			// canceled cycle
			sys_cmd_out <= SYS_CMD_WRITE_BLOCK | size;
			sys_ad_out <= address;

			if (monitor) begin
				$display(`CLOCK_COUNT, " : R4200 write - canceled");
				end

			@(posedge clock);

			while (!e_ok) @(posedge clock);

			sys_cmd_out <= SYS_CMD_DATA_NEXT;
			sys_ad_out <= data[0];

			if (monitor) begin
				$display(`CLOCK_COUNT, " : R4200 write[%h] - %h @ %h",
					4'h0, data[0], address);
				end

			@(posedge clock);
			end

		// finish sending data
		for (i = 1; i < (2 << size) - 1; i = i + 1) begin
			sys_ad_out <= data[i];

			if (monitor) begin
				$display(`CLOCK_COUNT, " : R4200 write[%h] - %h @ %h",
					i[3:0], data[i], address + (i * 4));
				end

			@(posedge clock);
			end

		sys_cmd_out <= SYS_CMD_DATA_LAST;
		sys_ad_out <= data[i];

		if (monitor) begin
			$display(`CLOCK_COUNT, " : R4200 write[%h] - %h @ %h",
				i[3:0], data[i], address + (i * 4));
			end

		@(posedge clock);
		end
	endtask

task read_word;
	input [31:0] address;
	input [1:0] size;

	begin
		p_valid <= HIGH;
		sys_cmd_out <= SYS_CMD_READ_WORD | size;
		sys_ad_out <= address;
		@(posedge clock);

		while (!e_ok) @(posedge clock);

		sys_ad_enable <= LOW;
		p_valid <= LOW;
		@(posedge clock);

		while (!e_ok) begin
			// canceled cycle
			sys_ad_enable <= HIGH;
			p_valid <= HIGH;
			sys_cmd_out <= SYS_CMD_READ_WORD | size;
			sys_ad_out <= address;

			if (monitor) begin
				$display(`CLOCK_COUNT, " : R4200 read	- canceled");
				end

			@(posedge clock);

			while (!e_ok) @(posedge clock);

			sys_ad_enable <= LOW;
			p_valid <= LOW;
			end

		while (!e_valid) @(posedge clock);

		data[0] = sys_ad_in;
		if (monitor) begin
			$display(`CLOCK_COUNT, " : R4200 read	- %h @ %h",
				sys_ad_in, address);
			end

		sys_ad_enable <= HIGH;
		end
	endtask



task read_block;
	input [31:0] address;
	input [1:0] size;

	integer i;
	begin
		p_valid <= HIGH;
		sys_cmd_out <= SYS_CMD_READ_BLOCK | size;
		sys_ad_out <= address;
		@(posedge clock);

		while (!e_ok) @(posedge clock);

		sys_ad_enable <= LOW;
		p_valid <= LOW;
		@(posedge clock);

		while (!e_ok) begin
			// canceled cycle
			sys_ad_enable <= HIGH;
			p_valid <= HIGH;
			sys_cmd_out <= SYS_CMD_READ_BLOCK | size;
			sys_ad_out <= address;

			if (monitor) begin
				$display(`CLOCK_COUNT, " : R4200 read	- canceled");
				end

			@(posedge clock);

			while (!e_ok) @(posedge clock);

			sys_ad_enable <= LOW;
			p_valid <= LOW;
			@(posedge clock);
			end

		// read data
		for (i = 0; i < (2 << size) - 1; i = i + 1) begin
			while (!e_valid) @(posedge clock);
			data[i] = sys_ad_in;

			if (monitor) begin
				$display(`CLOCK_COUNT, " : R4200 read[%h]	 - %h @ %h",
					i[3:0], sys_ad_in, address + (i * 4));
				end

			@(posedge clock);
			end

		while (!e_valid) @(posedge clock);
		data[i] = sys_ad_in;

		if (monitor) begin
			$display(`CLOCK_COUNT, " : R4200 read[%h]	 - %h @ %h",
				i[3:0], sys_ad_in, address + (i * 4));
			end

		sys_ad_enable <= HIGH;
		end
	endtask


task sp_dma_write;
	input [31:0] master_address;
	input [31:0] slave_address;
	input [11:0] skip;
	input [7:0] count;
	input [11:0] length;

	integer status;
	begin
		// while busy
		read_word(BUS_ADDRESS_SP_STATUS, 3);
		status = data[0];
		while (status[3]) begin
			read_word(BUS_ADDRESS_SP_STATUS, 3);
			status = data[0];
			end

		write_word(BUS_ADDRESS_SP_MASTER, 3, master_address);
		write_word(BUS_ADDRESS_SP_SLAVE, 3, slave_address);
		write_word(BUS_ADDRESS_SP_WRITE, 3, {skip, count, length});
		p_valid <= LOW;
		@(posedge clock);
		end
	endtask


task sp_dma_read;
	input [31:0] master_address;
	input [31:0] slave_address;
	input [11:0] skip;
	input [7:0] count;
	input [11:0] length;

	integer status;
	begin
		// while busy
		read_word(BUS_ADDRESS_SP_STATUS, 3);
		status = data[0];
		while (status[3]) begin
			read_word(BUS_ADDRESS_SP_STATUS, 3);
			status = data[0];
			end

		write_word(BUS_ADDRESS_SP_MASTER, 3, master_address);
		write_word(BUS_ADDRESS_SP_SLAVE, 3, slave_address);
		write_word(BUS_ADDRESS_SP_READ, 3, {skip, count, length});
		p_valid <= LOW;
		@(posedge clock);
		end
	endtask


task sp_mem_write;
	input [31:0] address;
	input [31:0] write_data;

	integer status;
	begin
		// while busy
		read_word(BUS_ADDRESS_SP_STATUS, 3);
		status = data[0];
		while (status[4]) begin
			read_word(BUS_ADDRESS_SP_STATUS, 3);
			status = data[0];
			end

		write_word(BUS_ADDRESS_SP_DMEM+address, 3, write_data);
		p_valid <= LOW;
		@(posedge clock);
		end
	endtask


task sp_mem_read;
	input [31:0] address;

	integer status;
	begin
		// while busy
		read_word(BUS_ADDRESS_SP_STATUS, 3);
		status = data[0];
		while (status[4]) begin
			read_word(BUS_ADDRESS_SP_STATUS, 3);
			status = data[0];
			end

		read_word(BUS_ADDRESS_SP_DMEM+address, 3);
		end
	endtask