vi_tab.v
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////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: vi_tab.v
// description: dumps out vi i/o .tab file
//
// designer: Tony DeLaurier
// date: 12/31/94
//
////////////////////////////////////////////////////////////////////////
module vi_tab();
integer tab_file_ptr;
wire clk_dly;
// open tab file and dump header
initial
begin
tab_file_ptr = $fopen("vi.tab");
// dump out header
$fwriteh(tab_file_ptr, "#\n");
$fwriteh(tab_file_ptr, "# vi tab file\n");
$fwriteh(tab_file_ptr, "#\n");
$fwriteh(tab_file_ptr, "clk_2x @DC 1(4) 0(4)\n");
$fwriteh(tab_file_ptr, "vclk @C 1(8) 0(8)\n");
$fwriteh(tab_file_ptr, "clk @I @E 0 @C clk_2x\n");
$fwriteh(tab_file_ptr, "reset_l @I @E 2 @C vclk\n");
$fwriteh(tab_file_ptr, "cbus_read_enable @I @E 2 @C vclk\n");
$fwriteh(tab_file_ptr, "cbus_write_enable @I @E 2 @C vclk\n");
$fwriteh(tab_file_ptr, "cbus_select[1:0] @I @E 2 @C vclk\n");
$fwriteh(tab_file_ptr, "cbus_command[2:0] @I @E 2 @C vclk\n");
$fwriteh(tab_file_ptr, "dma_start @I @E 2 @C vclk\n");
$fwriteh(tab_file_ptr, "dma_last @I @E 2 @C vclk\n");
$fwriteh(tab_file_ptr, "dma_grant @I @E 2 @C vclk\n");
$fwriteh(tab_file_ptr, "read_grant @I @E 2 @C vclk\n");
$fwriteh(tab_file_ptr, "dbus_data[63:0] @I @E 2 @C vclk\n");
$fwriteh(tab_file_ptr, "ebus_data[7:0] @I @E 2 @C vclk\n");
$fwriteh(tab_file_ptr, "dma_request @O @S 15 @C vclk\n");
$fwriteh(tab_file_ptr, "read_request @O @S 15 @C vclk\n");
$fwriteh(tab_file_ptr, "vbus_data[6:0] @O @S 15 @C vclk @V dv\n");
$fwriteh(tab_file_ptr, "vbus_sync @O @S 15 @C vclk @V dv\n");
$fwriteh(tab_file_ptr, "vbus_clock_enable_l @O @S 15 @C vclk\n");
$fwriteh(tab_file_ptr, "vi_int @O @S 15 @C vclk\n");
$fwriteh(tab_file_ptr, "refresh_strobe @O @S 15 @C vclk\n");
$fwriteh(tab_file_ptr, "cbus_data[31:0] @B cbus_data_oe 1 @E 5 @S 15 @C vclk\n");
$fwriteh(tab_file_ptr, "cbus_data_oe @O @S 15 @C vclk\n");
$fwriteh(tab_file_ptr, "cbus_dummy @I @E 0 @C vclk\n");
$fwriteh(tab_file_ptr, "dv @V @C vclk\n");
$fwriteh(tab_file_ptr, "\n");
end // initial
// delay clk for sampling
assign #1 clk_dly = reality.rcp_0.vi_0.clk;
reg reset_l_1d;
reg reset_l_2d;
reg reset_l_3d;
reg reset_l_4d;
reg reset_l_5d;
reg reset_l_6d;
reg reset_l_7d;
reg reset_l_8d;
reg reset_l_9d;
reg reset_l_10d;
reg reset_l_11d;
reg reset_l_12d;
reg reset_l_13d;
reg reset_l_14d;
reg dv;
// determine data valid
always @(posedge reality.rcp_0.vi_0.vclk)
begin
reset_l_1d <= reality.rcp_0.vi_0.reset_l;
reset_l_2d <= reset_l_1d;
reset_l_3d <= reset_l_2d;
reset_l_4d <= reset_l_3d;
reset_l_5d <= reset_l_4d;
reset_l_6d <= reset_l_5d;
reset_l_7d <= reset_l_6d;
reset_l_8d <= reset_l_7d;
reset_l_9d <= reset_l_8d;
reset_l_10d <= reset_l_9d;
reset_l_11d <= reset_l_10d;
reset_l_12d <= reset_l_11d;
reset_l_13d <= reset_l_12d;
reset_l_14d <= reset_l_13d;
end
initial
begin
dv <= 0;
end
always @(posedge reality.rcp_0.vi_0.vclk)
begin
dv <= ({reality.rcp_0.vi_0.reset_l, reset_l_1d, reset_l_2d, reset_l_3d, reset_l_4d,
reset_l_5d, reset_l_6d, reset_l_7d, reset_l_8d, reset_l_9d,
reset_l_10d, reset_l_11d, reset_l_12d, reset_l_13d, reset_l_14d} === 11'b0) || dv;
end
// dump vi at both edges of clk
integer vector_count;
initial vector_count = -1;
always @(reality.rcp_0.vi_0.vclk)
begin
if (vector_count >= 0)
begin
$fwriteh(tab_file_ptr,
clk_dly,,
reality.rcp_0.vi_0.reset_l,," ",
reality.rcp_0.vi_0.cbus_read_enable,,
reality.rcp_0.vi_0.cbus_write_enable,,
"0x", reality.rcp_0.vi_0.cbus_select,,
"0x", reality.rcp_0.vi_0.cbus_command,,
reality.rcp_0.vi_0.dma_start,,
reality.rcp_0.vi_0.dma_last,,
reality.rcp_0.vi_0.dma_grant,,
reality.rcp_0.vi_0.read_grant,,
"0x", reality.rcp_0.vi_0.dbus_data,,
"0x", reality.rcp_0.vi_0.ebus_data,," ",
reality.rcp_0.vi_0.dma_request,,
reality.rcp_0.vi_0.read_request,,
"0x", reality.rcp_0.vi_0.vbus_data,,
reality.rcp_0.vi_0.vbus_sync,,
reality.rcp_0.vi_0.vbus_clock_enable_l,,
reality.rcp_0.vi_0.vi_int,,
reality.rcp_0.vi_0.refresh_strobe,," ",
"0x", reality.rcp_0.vi_0.cbus_data,,
reality.rcp_0.vi_0.cbus_write_enable,,
reality.rcp_0.vi_0.cbus_write_enable,," ",
dv,,
"\n");
end // if
else
begin
vector_count = vector_count + 1;
end // else
end // always
endmodule // vi_tab