// bb.v v1 Frank Berndt
// bb chip top level;
// this is the die, not the package;
// :set tabstop=4

// naming restrictions for synthesis;
// names of pad IOs must begin with PAD_ ;
// names of instantiated io buffers must begin with pad_ ;

`timescale 1ns/1ns

module bb (
	PAD_RST_L,
	PAD_SYSCLK,
	PAD_USBCLKI,
	PAD_USBCLKO,
	PAD_VCLKI,
	PAD_VCLKO,
	PAD_BUTTON,
	PAD_VCLOCK,
	PAD_VDATA0,
	PAD_VDATA1,
	PAD_VDATA2,
	PAD_VDATA3,
	PAD_VDATA4,
	PAD_VDATA5,
	PAD_VDATA6,
	PAD_VSYNC,
	PAD_VOA,
	PAD_VOB,
	PAD_VOC,
	PAD_ACLOCK,
	PAD_ADATA,
	PAD_AWORD,
	PAD_JCHAN1,
	PAD_JCHAN2,
	PAD_JCHAN3,
	PAD_LX0,
	PAD_LX1,
	PAD_LY0,
	PAD_LY1,
	PAD_IO_RST,
	PAD_IO_AD0,
	PAD_IO_AD1,
	PAD_IO_AD2,
	PAD_IO_AD3,
	PAD_IO_AD4,
	PAD_IO_AD5,
	PAD_IO_AD6,
	PAD_IO_AD7,
	PAD_IO_AD8,
	PAD_IO_AD9,
	PAD_IO_AD10,
	PAD_IO_AD11,
	PAD_IO_AD12,
	PAD_IO_AD13,
	PAD_IO_AD14,
	PAD_IO_AD15,
	PAD_IO_ALE,
	PAD_IO_CS0,
	PAD_IO_CS1,
	PAD_IO_CS2,
	PAD_IO_CS3,
	PAD_IO_IOR,
	PAD_IO_IOW,
	PAD_IO_DMARQ,
	PAD_IO_DMACK,
	PAD_IO_INTR,
	PAD_NRING_ENL,
	PAD_FL_CE0,
	PAD_FL_CE1,
	PAD_FL_CE2,
	PAD_FL_CE3,
	PAD_FL_ALE,
	PAD_FL_CLE,
	PAD_FL_RE,
	PAD_FL_WE,
	PAD_FL_WP,
	PAD_FL_RYBY,
	PAD_FL_MD,
	PAD_GPIO0,
	PAD_GPIO1,
	PAD_GPIO2,
	PAD_GPIO3,
	PAD_MCLK0,
	PAD_MCLK1,
	PAD_MCKE,
	PAD_MADDR0,
	PAD_MADDR1,
	PAD_MADDR2,
	PAD_MADDR3,
	PAD_MADDR4,
	PAD_MADDR5,
	PAD_MADDR6,
	PAD_MADDR7,
	PAD_MADDR8,
	PAD_MADDR9,
	PAD_MADDR10,
	PAD_MADDR11,
	PAD_MADDR12,
	PAD_MBANK0,
	PAD_MBANK1,
	PAD_MDATA0,
	PAD_MDATA1,
	PAD_MDATA2,
	PAD_MDATA3,
	PAD_MDATA4,
	PAD_MDATA5,
	PAD_MDATA6,
	PAD_MDATA7,
	PAD_MDATA8,
	PAD_MDATA9,
	PAD_MDATA10,
	PAD_MDATA11,
	PAD_MDATA12,
	PAD_MDATA13,
	PAD_MDATA14,
	PAD_MDATA15,
	PAD_MDATA16,
	PAD_MDATA17,
	PAD_MDATA18,
	PAD_MDATA19,
	PAD_MDATA20,
	PAD_MDATA21,
	PAD_MDATA22,
	PAD_MDATA23,
	PAD_MDATA24,
	PAD_MDATA25,
	PAD_MDATA26,
	PAD_MDATA27,
	PAD_MDATA28,
	PAD_MDATA29,
	PAD_MDATA30,
	PAD_MDATA31,
	PAD_MRAS,
	PAD_MCAS,
	PAD_MWE,
	PAD_MDQM0,
	PAD_MDQM1,
	PAD_MDQM2,
	PAD_MDQM3,
	PAD_MDQS0,
	PAD_MDQS1,
	PAD_MDQS2,
	PAD_MDQS3,
	PAD_USB_DPLUS0,
	PAD_USB_DPLUS1,
	PAD_USB_DMINUS0,
	PAD_USB_DMINUS1,
	PAD_USB_DP_HIGH0,
	PAD_USB_DP_HIGH1,
	PAD_USB_D_LOW_N0,
	PAD_USB_D_LOW_N1,
	PAD_USB_VBUS_VLD0,
	PAD_USB_VBUS_VLD1,
	PAD_USB_ID0,
	PAD_USB_ID1,
	PAD_USB_VBUS_ON0,
	PAD_USB_VBUS_ON1,
	PAD_TRST,
	PAD_TDI,
	PAD_TMS,
	PAD_TCK,
	PAD_TDO,
	PAD_PLLX2_AVDD,
	PAD_PLLX2_AGND,
	PAD_PLLC_AVDD,
	PAD_PLLC_AGND,
	PAD_PLLV_AVDD,
	PAD_PLLV_AGND,
	PAD_JTAG_EN,
	PAD_MVREF1,
	PAD_MVREF2,
	PAD_TMC,
	PAD_TMC1,
	PAD_TMC2,
	PAD_NECTRST,
	PAD_AVDD3,
	PAD_AVDD2,
	PAD_AVDD1,
	PAD_AGND3,
	PAD_AGND2,
	PAD_AGND1
	);

	input			PAD_RST_L;		// chip reset input;
	input			PAD_SYSCLK;		// chip system clock input;
	input			PAD_USBCLKI;	// usb clock input;
	output			PAD_USBCLKO;	// usb clock output;
	input			PAD_VCLKI;		// video clock input;
	output			PAD_VCLKO;		// video clock output;
	input			PAD_BUTTON;		// button input;
	inout			PAD_VCLOCK;		// video data;
	inout			PAD_VDATA0;		// video data;
	inout			PAD_VDATA1;		// video data;
	inout			PAD_VDATA2;		// video data;
	inout			PAD_VDATA3;		// video data;
	inout			PAD_VDATA4;		// video data;
	inout			PAD_VDATA5;		// video data;
	inout			PAD_VDATA6;		// video data;
	inout			PAD_VSYNC;		// video sync;
	output			PAD_VOA;		// analog video, chroma;
	output			PAD_VOB;		// analog video, composite;
	output			PAD_VOC;		// analog video, luminance;
	inout			PAD_ACLOCK;		// audio clock;
	inout			PAD_ADATA;		// audio data;
	inout			PAD_AWORD;		// audio word clock;
	inout			PAD_JCHAN1;		// joy channel ports;
	inout			PAD_JCHAN2;		// joy channel ports;
	inout			PAD_JCHAN3;		// joy channel ports;
	input			PAD_LX0;		// stick x inputs;
	input			PAD_LX1;		// stick x inputs;
	input			PAD_LY0;		// stick y inputs;
	input			PAD_LY1;		// stick y inputs;
	inout			PAD_IO_RST;		// io bus reset;
	inout			PAD_IO_AD0;		// io data bus;
	inout			PAD_IO_AD1;		// io data bus;
	inout			PAD_IO_AD2;		// io data bus;
	inout			PAD_IO_AD3;		// io data bus;
	inout			PAD_IO_AD4;		// io data bus;
	inout			PAD_IO_AD5;		// io data bus;
	inout			PAD_IO_AD6;		// io data bus;
	inout			PAD_IO_AD7;		// io data bus;
	inout			PAD_IO_AD8;		// io data bus;
	inout			PAD_IO_AD9;		// io data bus;
	inout			PAD_IO_AD10;	// io data bus;
	inout			PAD_IO_AD11;	// io data bus;
	inout			PAD_IO_AD12;	// io data bus;
	inout			PAD_IO_AD13;	// io data bus;
	inout			PAD_IO_AD14;	// io data bus;
	inout			PAD_IO_AD15;	// io data bus;
	inout			PAD_IO_ALE;		// io address latch enable;
	inout			PAD_IO_CS0;		// io pio chip selects;
	inout			PAD_IO_CS1;		// io pio chip selects;
	inout			PAD_IO_CS2;		// io pio chip selects;
	inout			PAD_IO_CS3;		// io pio chip selects;
	inout			PAD_IO_IOR;		// io read pulse;
	inout			PAD_IO_IOW;		// io write pulse;
	input			PAD_IO_DMARQ;	// io dma request;
	output			PAD_IO_DMACK;	// io dma acknowledge;
	input			PAD_IO_INTR;	// io device interrupt;
	input			PAD_NRING_ENL;	// nand ring enable (1=normal operation)
	inout			PAD_FL_CE0;		// chip enables;
	inout			PAD_FL_CE1;		// chip enables;
	inout			PAD_FL_CE2;		// chip enables;
	inout			PAD_FL_CE3;		// chip enables;
	inout			PAD_FL_ALE;		// address latch enable;
	inout			PAD_FL_CLE;		// command latch enable;
	inout			PAD_FL_RE;		// read eanble;
	inout			PAD_FL_WE;		// write eanble;
	inout			PAD_FL_WP;		// write protect;
	input			PAD_FL_RYBY;	// ready/busy;
	input			PAD_FL_MD;		// module detect;
	inout			PAD_GPIO0;		// general purpose io;
	inout			PAD_GPIO1;		// general purpose io;
	inout			PAD_GPIO2;		// general purpose io;
	inout			PAD_GPIO3;		// general purpose io;
	inout			PAD_MCLK0;
	inout			PAD_MCLK1;
	inout			PAD_MCKE;
	inout			PAD_MADDR0;
	inout			PAD_MADDR1;
	inout			PAD_MADDR2;
	inout			PAD_MADDR3;
	inout			PAD_MADDR4;
	inout			PAD_MADDR5;
	inout			PAD_MADDR6;
	inout			PAD_MADDR7;
	inout			PAD_MADDR8;
	inout			PAD_MADDR9;
	inout			PAD_MADDR10;
	inout			PAD_MADDR11;
	inout			PAD_MADDR12;
	inout			PAD_MBANK0;
	inout			PAD_MBANK1;
	inout			PAD_MDATA0;	
	inout			PAD_MDATA1;	
	inout			PAD_MDATA2;	
	inout			PAD_MDATA3;	
	inout			PAD_MDATA4;	
	inout			PAD_MDATA5;	
	inout			PAD_MDATA6;	
	inout			PAD_MDATA7;	
	inout			PAD_MDATA8;	
	inout			PAD_MDATA9;	
	inout			PAD_MDATA10;	
	inout			PAD_MDATA11;	
	inout			PAD_MDATA12;	
	inout			PAD_MDATA13;	
	inout			PAD_MDATA14;	
	inout			PAD_MDATA15;	
	inout			PAD_MDATA16;	
	inout			PAD_MDATA17;	
	inout			PAD_MDATA18;	
	inout			PAD_MDATA19;	
	inout			PAD_MDATA20;	
	inout			PAD_MDATA21;	
	inout			PAD_MDATA22;	
	inout			PAD_MDATA23;	
	inout			PAD_MDATA24;	
	inout			PAD_MDATA25;	
	inout			PAD_MDATA26;	
	inout			PAD_MDATA27;	
	inout			PAD_MDATA28;	
	inout			PAD_MDATA29;	
	inout			PAD_MDATA30;	
	inout			PAD_MDATA31;	
	inout			PAD_MRAS;
	inout			PAD_MCAS;
	inout			PAD_MWE;
	inout			PAD_MDQM0;
	inout			PAD_MDQM1;
	inout			PAD_MDQM2;
	inout			PAD_MDQM3;
	inout			PAD_MDQS0;
	inout			PAD_MDQS1;
	inout			PAD_MDQS2;
	inout			PAD_MDQS3;
	inout			PAD_USB_DPLUS0;	  	// usb D+;
	inout			PAD_USB_DPLUS1;	  	// usb D+;
	inout			PAD_USB_DMINUS0;  	// usb D-;
	inout			PAD_USB_DMINUS1;  	// usb D-;
	inout	 		PAD_USB_DP_HIGH0;  	// pull up controls;
	inout	 		PAD_USB_DP_HIGH1;  	// pull up controls;
	inout	 		PAD_USB_D_LOW_N0;  	// pull down controls;
	inout	 		PAD_USB_D_LOW_N1;  	// pull down controls;
	input			PAD_USB_VBUS_VLD0;	// vbus valid
	input			PAD_USB_VBUS_VLD1;	// vbus valid
	input			PAD_USB_ID0;	  	// Id pin
	input			PAD_USB_ID1;	  	// Id pin
	inout			PAD_USB_VBUS_ON0;	// host mode 
	inout			PAD_USB_VBUS_ON1;	// host mode 
	input			PAD_TRST;			// jtag
	input			PAD_TDI;
	input			PAD_TMS;
	input			PAD_TCK;
	inout			PAD_TDO;
	input			PAD_PLLX2_AVDD;		// ddr pll ananlog power;
	input			PAD_PLLX2_AGND;		// ddr pll ananlog ground;
	input			PAD_PLLC_AVDD;		// Cpu pll ananlog power;
	input			PAD_PLLC_AGND;		// Cpu pll ananlog ground;
	input			PAD_PLLV_AVDD;		// Video pll ananlog power;
	input			PAD_PLLV_AGND;		// Video pll ananlog ground;
	input			PAD_JTAG_EN;		// force enable of jtag;
	input			PAD_MVREF1;			// SSTL2 VREF
	input			PAD_MVREF2;			// SSTL2 VREF
	input			PAD_TMC;		// NEC Test Mode Control
	input			PAD_TMC1;		// NEC Test Mode Control 1: no bonding wire
	input			PAD_TMC2;		// NEC Test Mode Control 2: no bonding wire
	input			PAD_NECTRST;	// NEC tap reset
	input			PAD_AVDD3;		// analog video power
	input			PAD_AVDD2;		// analog video power
	input			PAD_AVDD1;		// analog video power
	input			PAD_AGND3;		// analog video ground
	input			PAD_AGND2;		// analog video ground
	input			PAD_AGND1;		// analog video ground

`include "syn.vh"
`include "define.vh"
`include "jctrl.vh"

	wire	tena;
	wire	tmc_in, tmc;

	// NEC test tmc;

	TDIPAC33D pad_mc ( .H01(PAD_TMC), .N01(tmc_in) );

	assign tmc = tmc_in & tena;
 
	// NEC test tmc1 : NO BONDING WIRE : NO PACKAGE PIN
	// NEC test tmc2  : NO BONDING WIRE : NO PACKAGE PIN

	wire tmc1, tmc2;

	TDTEC33D1 pad_mc1 ( .H01(PAD_TMC1), .N01(tmc1) );
	TDTEC33D2 pad_mc2 ( .H01(PAD_TMC2), .N01(tmc2) );

	// NEC test NEC tap reset

	wire nectrst;		// TRST for nec tap controller;

	TDIPAC33U pad_nec_trst ( .H01(PAD_NECTRST), .N01(nectrst) );

	// bcp outputs

	wire			mcke;
	wire	[12:0]	maddr;
	wire	[1:0]	mbank;
	wire			mdin_ena;
	wire			mdout_ena;
	wire	[4:0]	strobe_rev;
	wire	[63:0]	mdout;
	wire			mras;
	wire			mcas;
	wire			mwe;
	wire	[7:0]	mdqm;

	// video interface;

	wire [25:0] avctrl;			// audio/video control;
	wire vclock;				// video clock;
	wire [6:0] vdata;			// video data;
	wire vsync;					// video sync;
	wire vdac_clk;				// video dac clock;
	wire vdac_pd;				// video dac power-down;
	wire [7:0] vda;				// video chroma;
	wire [7:0] vdb;				// video composite;
	wire [7:0] vdc;				// video luminance;
	wire vntpl;					// ntsc/pal mode;
	wire vmpal;					// pal/mpal mode;
	wire vtrap;					// trap filter mode;
	wire venc_test;				// video encoder test mode;

	assign vdac_pd = avctrl[19];
	assign vntpl = avctrl[20];
	assign vmpal = avctrl[21];
	assign vtrap = avctrl[22];
	assign venc_test = avctrl[23];

	// audio DAC interface;

	wire aclock;				// audio clock;
	wire adata;					// audio data;
	wire aword;					// audio word;

	// joy channel interface;

	reg [3:1] jchan_in;			// output of input register;
	wire [3:1] jchan_ena;		// input reg clock enables;
	wire [3:1] jchan_oe;		// output enable;

	// local controller joystick;

	wire [1:0] lctrl_x;			// stick x inputs;
	wire [1:0] lctrl_y;			// stick y inputs;

	// generic io bus controller;

	wire io_rst;				// io bus reset;
	reg [15:0] io_in;			// io input data;
	wire io_ena;				// io input clock enables;
	wire [15:0] io_out;			// io output data;
	wire [1:0] io_oe;			// io data output enables;
	wire io_ale;				// io address latch enable;
	wire [3:0] io_cs;			// io pio chip selects;
	wire io_ior;				// io read pulse;
	wire io_iow;				// io write pulse;
	reg io_dmarq;				// io dma request;
	wire io_dmack;				// io dma acknowledge;
	reg io_intr;				// io device interrupt;

	// nand flash controls;

	wire [3:0] fl_ce;			// chip enables;
	wire fl_ale;				// address latch enable;
	wire fl_cle;				// command latch enable;
	wire fl_re;					// read eanble;
	wire fl_we;					// write eanble;
	wire fl_wp;					// write protect;
	wire fl_ryby;				// ready/busy;
	wire fl_md;					// module detect;

	// usb xcr control
	wire [1:0] usb_dp;
	wire [1:0] usb_dpo;
	wire [1:0] usb_dm;
	wire [1:0] usbxr_ose;
	wire [1:0] usbxr_y1;
	wire [1:0] usbxr_oen;
	wire [1:0] usbxr_ien;
	wire [1:0] usbxr_fl;
	wire [1:0] usb_dp_high;
	wire [1:0] usb_d_low_n;
	wire [1:0] usb_vbus_vld;
	wire [1:0] usb_id;
	wire [1:0] usb_vbus_on_n;

	// test/jtag interface;

	wire porst;					// sum of on-chip power-on resets;
	wire jtag_ena;				// enable test/jtag logic;
	wire jtag_force;			// force enable of test/jtag;
	wire pll_bypass;			// cpu/x2 pll bypass;
	wire trst;
	wire tdi;
	wire tms;
	wire tck;
	wire tdo;
	wire tdoen;

	// analog powers;

	wire pllc_avdd1;			// cpu pll analog power;
	wire pllc_agnd1;			// cpu pll analog ground;

	// general purpose io;

	wire [3:0] gpio_oe;			// output enables;
	wire [3:0] gpio_out;		// output values;
	wire [3:0] gpio_in;			// input values;


	// important global signals;

	wire sysclk;				// system clock;
	wire usbclk;				// usb clock;
	wire memclk;				// memory clock;
	wire rst_l;					// chip reset;
	wire reset_l;				// system reset to pads;
	wire avrst_l;				// audio/video reset;
	wire pllc_lock;				// cpu pll lock;
	wire [1:0] pll_lock;		// important plls are locked;
	wire usb_sel_sys;			// usb select sysclk/2;

	// buffer up reset from pin;

	wire rst_l_in ;
	reg rst_l_reg;

	TDIPAC33N pad_rst ( .H01(PAD_RST_L), .N01(rst_l_in) );

	always @(posedge sysclk)
	begin
		rst_l_reg <= rst_l_in;
	end

	TBBUFX16 rst_buf1 ( .H01(rst_l_reg), .N01(rst_l) );

	// clock input buffer;

	wire sysclk_in ;

	TDIPAC33N pad_sclk ( .H01(PAD_SYSCLK), .N01(sysclk_in) );
	TBCTS sysclk_tree ( .H01(sysclk_in), .N01(sysclk) );

	// SSTL2 VREF

	TDIPAST2R pad_vref1 ( .H01(PAD_MVREF1) );
	TDIPAST2R pad_vref2 ( .H01(PAD_MVREF2) );

	// button input buffer

	wire button;			// external button;

	TDIPAC33N pad_bttn ( .H01(PAD_BUTTON), .N01(button) );

	// usb clocking;
	// from io pins to usb clock oscillator;

	wire usbclk_in;			// output of oscillator;

	TDOSAC33N50M usbclk_osc (
		.H01(PAD_USBCLKI),	// XT1
		.H02(1'b1),			// Enable
		.N01(usbclk_in),	// OSCOUT
		.N02(PAD_USBCLKO)	// XT2
	);

	// can either use oscillator of sysclk/2 if running at 96MHz;

	reg	sysclkdiv2;

	always @(posedge sysclk)
			sysclkdiv2 <=  reset_l & ~sysclkdiv2;

	wire usbclk_sel;		// oscillator or sysclk/2;
	wire usbclk_tmc;		// sysclk for NEC test mode;

	assign usbclk_sel = usb_sel_sys? sysclkdiv2 : usbclk_in;
	assign usbclk_tmc = tmc? sysclk_in : usbclk_sel;

	TBCTS usbclk_tree ( .H01(usbclk_tmc), .N01(usbclk) );

	// video clock oscillator;

	wire vclk_in;			// output of oscillator; video clock;

	TDOSAC33N16M vclk_osc (
		.H01(PAD_VCLKI),	// XT1
		.H02(1'b1),			// Enable
		.N01(vclk_in),		// OSCOUT
		.N02(PAD_VCLKO)		// XT2
	);

	// instantiate x2 pll;
	// creates ddr clock x2, and aligns memclk with sysclk;
	// vco runs from 250...400Mhz (sysclk 62.5...100);

	wire pllx2_m;			// M divider;
	wire [3:0] pllx2_n;		// N divider;
	wire [3:0] pllx2_pa;	// PA divider;
	wire [3:0] pllx2_pb;	// PB divider;
	wire [3:0] pllx2_pc;	// PC divider;
	wire [2:0] pllx2_stby;	// standby controls;
	wire pllx2_lock;		// x2 pll is locked;
	wire pllx2_clk;			// x2 clock output;
	wire pllx2_mode;		// test mode;
	wire pllx2_atbi0;		// test mode;
	wire pllx2_test;		// test mode;
	wire pllx2_bunri;		// test mode;
	wire pllx2_avdd1;		// pll analog power
	wire pllx2_agnd1;		// pll analog ground

	assign pllx2_m  = 1'b1;		// rclk / 2 = 31.25...50Mhz;
	assign pllx2_n  = 4'd3;		// vco / pa / 4 = 31.25...50Mhz;
	assign pllx2_pa = 4'd1;		// clk A = vco / 2;
	assign pllx2_pb = 4'd1;		// clk B = vco / 2;
	assign pllx2_pc = 4'd1;		// clk C = vco / 2;
	assign pllx2_stby[0] = ~rst_l;
	assign pllx2_stby[1] = 1'b1;	// turn off port B;
	assign pllx2_stby[2] = 1'b1;	// turn off port C;
	assign pllx2_mode = 1'b0;
	assign pllx2_atbi0 = 1'b0;
	assign pllx2_test = 1'b0;
	assign pllx2_bunri = 1'b0;

	assign pll_lock[1] = pllx2_lock | pll_bypass;
	assign pll_lock[0] = pllc_lock | pll_bypass;

	ABPLSSCH pllx2 (
		.RCLK(sysclk),
		.CLKI(memclk),
		.M0(pllx2_m),
		.N0(pllx2_n[0]),
		.N1(pllx2_n[1]),
		.N2(pllx2_n[2]),
		.N3(pllx2_n[3]),
		.PA0(pllx2_pa[0]),
		.PA1(pllx2_pa[1]),
		.PA2(pllx2_pa[2]),
		.PA3(pllx2_pa[3]),
		.PB0(pllx2_pb[0]),
		.PB1(pllx2_pb[1]),
		.PB2(pllx2_pb[2]),
		.PB3(pllx2_pb[3]),
		.PC0(pllx2_pc[0]),
		.PC1(pllx2_pc[1]),
		.PC2(pllx2_pc[2]),
		.PC3(pllx2_pc[3]),
		.STBY(pllx2_stby[0]),
		.PBSTBY(pllx2_stby[1]),
		.PCSTBY(pllx2_stby[2]),
		.CLKOA(pllx2_clk),
		.CLKOB(),
		.CLKOC(),
		.PLOCK(pllx2_lock),
		.MODE(pllx2_mode),
		.ATBI0(pllx2_atbi0),
		.TEST(pllx2_test),
		.BUNRI(pllx2_bunri),
		.TBI0(1'b0),
		.TBI1(1'b0),
		.TBI2(1'b0),
		.TBI3(1'b0),
		.TBI4(1'b0),
		.TBI5(1'b0),
		.TBI6(1'b0),
		.TBI7(1'b0),
		.TBI8(1'b0),
		.TBI9(1'b0),
		.TBI10(1'b0),
		.TBI11(1'b0),
		.TBI12(1'b0),
		.TBI13(1'b0),
		.TBI14(1'b0),
		.TBI15(1'b0),
		.TBI16(1'b0),
		.TBI17(1'b0),
		.TBI18(1'b0),
		.TBI19(1'b0),
		.TBI20(1'b0),
		.TBI21(1'b0),
		.TBO0(),
		.TBO1(),
		.TBO2(),
		.TBO3(),
		.TBO4(),
		.AVDD1(pllx2_avdd1),
		.AGND1(pllx2_agnd1)
	);

	// pllx2_clk feeds the memclk tree;
	// in case of pll problems we can bypass memclk pll and 
	// use gpio pin for memclk

	wire	pllx2_clk_bypass = pll_bypass ? gpio_in[3] : pllx2_clk;

	wire	pllx2_clk_tmc = tmc ? sysclk_in : pllx2_clk_bypass;

	TBCTS memclk_tree ( .H01(pllx2_clk_tmc), .N01(memclk) );

	// instantiate video pll;
	// most of the pll controls come from the vi control register;
 
	wire pllv_stby;			// stand-by;
	wire pllv_rst;			// P reset;
	wire pllv_byp;			// bypass video pll;
	wire [1:0] pllv_s;		// frequency select;
	wire [4:0] pllv_m;		// M divider;
	wire [6:0] pllv_n;		// N divider;
	wire [2:0] pllv_p;		// P (output) divider;
	wire pllv_clk;			// pll clock output;
	wire pllv_vclk;			// pll or bypassed clock;
	wire pllv_atbi0;		// test;
	wire pllv_mode;			// pll through mode, atbi0 -> fo;
	wire pllv_test;			// test;
	wire pllv_bunri;		// test;

	assign pllv_stby = avctrl[0] | pllv_byp;
	assign pllv_rst = avctrl[1];
	assign pllv_s = avctrl[3:2];
	assign pllv_m = avctrl[8:4];
	assign pllv_n = avctrl[15:9];
	assign pllv_p = avctrl[18:16];
	assign pllv_byp = avctrl[24];

	// drive av reset through reset buffer tree;

	wire avrst_l_in;

	assign avrst_l_in = avctrl[25];

/*XXX
	TBCTSRS avrst_l_tree ( .H01(avrst_l_in), .N01(avrst_l) );
*/
assign avrst_l = avrst_l_in;

	assign pllv_atbi0 = 1'b0;
	assign pllv_mode = 1'b0;
	assign pllv_test = 1'b0;
	assign pllv_bunri = 1'b0;

	wire pllv_avdd1;		// pll analog power;
	wire pllv_agnd1;		// pll analog ground;
	wire pllv_dvdd1;		// pll digital power;
	wire pllv_dgnd1;		// pll digital ground;

	AAPLSVRH pllv (
		.RESETP(pllv_rst),
		.FR(vclk_in),
		.FO(pllv_clk),
		.STBY(pllv_stby),
		.S0(pllv_s[0]),
		.S1(pllv_s[1]),
		.M0(pllv_m[0]),
		.M1(pllv_m[1]),
		.M2(pllv_m[2]),
		.M3(pllv_m[3]),
		.M4(pllv_m[4]),
		.N0(pllv_n[0]),
		.N1(pllv_n[1]),
		.N2(pllv_n[2]),
		.N3(pllv_n[3]),
		.N4(pllv_n[4]),
		.N5(pllv_n[5]),
		.N6(pllv_n[6]),
		.P0(pllv_p[0]),
		.P1(pllv_p[1]),
		.P2(pllv_p[2]),
		.ATBI0(pllv_atbi0),
		.MODE(pllv_mode),
		.TEST(pllv_test),
		.BUNRI(pllv_bunri),
		.TBI0(1'b0),
		.TBI1(1'b0),
		.TBI2(1'b0),
		.TBI3(1'b0),
		.TBI4(1'b0),
		.TBI5(1'b0),
		.TBI6(1'b0),
		.TBI7(1'b0),
		.TBI8(1'b0),
		.TBI9(1'b0),
		.TBI10(1'b0),
		.TBI11(1'b0),
		.TBI12(1'b0),
		.TBI13(1'b0),
		.TBI14(1'b0),
		.TBI15(1'b0),
		.TBI16(1'b0),
		.TBI17(1'b0),
		.TBI18(1'b0),
		.TBI19(1'b0),
		.TBI20(1'b0),
		.TBI21(1'b0),
		.TBO0(),
		.TBO1(),
		.TBO2(),
		.AVDD1(pllv_avdd1),
		.AGND1(pllv_agnd1),
		.DVDD1(pllv_dvdd1),
		.DGND1(pllv_dgnd1)
	);

	// avctrl controls video pll bypass;
	// pllv_vclk feeds the vclock tree;

	assign	pllv_vclk = pllv_byp ? vclk_in : pllv_clk;

	wire	pllv_vclk_tmc = tmc ? sysclk_in : pllv_vclk;

	TBCTS vclk_tree ( .H01(pllv_vclk_tmc), .N01(vclock) );
 
	// ddr pll power interface;                            

	AAPLAIOH33 pad_ddr_pll (
		.AVDD(PAD_PLLX2_AVDD),
		.AGND(PAD_PLLX2_AGND),
		.AVDD1(pllx2_avdd1),
		.AGND1(pllx2_agnd1)
	);                           

	// cpu pll power interface;
 
	AAPLAIOH33 pad_cpu_pll (
		.AVDD(PAD_PLLC_AVDD),
		.AGND(PAD_PLLC_AGND),
		.AVDD1(pllc_avdd1),
		.AGND1(pllc_agnd1)
	);            

	// video pll power interface;
 
	AAPLSIOH33 pad_video_pll (
		.AVDD(PAD_PLLV_AVDD),
		.AGND(PAD_PLLV_AGND),
		.AVDD1(pllv_avdd1),
		.AGND1(pllv_agnd1),
		.DVDD1(pllv_dvdd1),
		.DGND1(pllv_dgnd1)
	);              

	// NAND ring enable logic;

	wire	nring_enl;
	wire	nring_en = ~nring_enl ;

	TDIPAC33U pad_nring ( .H01(PAD_NRING_ENL), .N01(nring_enl) );

	// ddr differential clock output;
	// tap off memclk tree only once to eliminate memclk tree skew;
	// TBINVX8 has balanced drives and is strong enough for io cell capacitance;

	wire mclk_minus;		// output of tap inverter;
	wire mclk_plus;			// input of MCLK0 io cell;

	TBINVX8 mclk_tap ( .H01(memclk), .N01(mclk_minus) );
	TBINVX8 mclk_buf ( .H01(mclk_minus), .N01(mclk_plus) );

	TDBIAST2NNC2
		pad_mck0 ( .H01(mclk_plus),  .H02(nring_enl), .H04(1'b1), .N01(PAD_MCLK0), .N02(mclk0_in) ),
		pad_mck1 ( .H01(mclk_minus), .H02(nring_enl), .H04(1'b1), .N01(PAD_MCLK1), .N02(mclk1_in) );

	// ddr io cells and registers;
	// synthesis requires all strobe names that are dont_touch
	// to start with the string 'ddr_strobe_*";

	wire [3:0] ddr_strobe_in;			// strobe from pin;
	wire [3:0] ddr_strobe_neg;		// inverted from pin;
	wire [3:0] ddr_strobe_mux;	// output of strobe reversal mux;
	wire [3:0] ddr_strobe_inv;	// output of inverter to buffer;
	wire ddr_strobe_p0;
	wire ddr_strobe_p1;
	wire ddr_strobe_p2;
	wire ddr_strobe_p3;
	wire ddr_strobe_n0;
	wire ddr_strobe_n1;
	wire ddr_strobe_n2;
	wire ddr_strobe_n3;

	//	assign	ddr_strobe_p = strobe_rev ? ~ddr_strobe_in :  ddr_strobe_in;
	//	assign	ddr_strobe_n = strobe_rev ? ~ddr_strobe_in :  ddr_strobe_in;

	TBINVX8 
		ddr_strbinv0	( .H01(ddr_strobe_in[0]), .N01(ddr_strobe_neg[0]) ),
		ddr_strbinv1	( .H01(ddr_strobe_in[1]), .N01(ddr_strobe_neg[1]) ),
		ddr_strbinv2	( .H01(ddr_strobe_in[2]), .N01(ddr_strobe_neg[2]) ),
		ddr_strbinv3	( .H01(ddr_strobe_in[3]), .N01(ddr_strobe_neg[3]) );

	TBMXI2X4
		ddr_strbmux0 ( .H01(ddr_strobe_neg[0]), .H02(ddr_strobe_in[0]),  .H03(strobe_rev[0]), .N01(ddr_strobe_mux[0]) ),
		ddr_strbmux1 ( .H01(ddr_strobe_neg[1]), .H02(ddr_strobe_in[1]),  .H03(strobe_rev[0]), .N01(ddr_strobe_mux[1]) ),
		ddr_strbmux2 ( .H01(ddr_strobe_neg[2]), .H02(ddr_strobe_in[2]),  .H03(strobe_rev[0]), .N01(ddr_strobe_mux[2]) ),
		ddr_strbmux3 ( .H01(ddr_strobe_neg[3]), .H02(ddr_strobe_in[3]),  .H03(strobe_rev[0]), .N01(ddr_strobe_mux[3]) );

	// drive output of muxes through inverter
	// before fanning out into 2 groups of 8;

	TBINVX8
		ddr_strbfan0 ( .H01(ddr_strobe_mux[0]), .N01(ddr_strobe_inv[0]) ),
		ddr_strbfan1 ( .H01(ddr_strobe_mux[1]), .N01(ddr_strobe_inv[1]) ),
		ddr_strbfan2 ( .H01(ddr_strobe_mux[2]), .N01(ddr_strobe_inv[2]) ),
		ddr_strbfan3 ( .H01(ddr_strobe_mux[3]), .N01(ddr_strobe_inv[3]) );

	// fanout drivers for each load of 8 registers;

	TBINVX16
		ddr_strbclk0 ( .H01(ddr_strobe_inv[0]), .N01(ddr_strobe_n0) ),
		ddr_strbclk1 ( .H01(ddr_strobe_inv[1]), .N01(ddr_strobe_n1) ),
		ddr_strbclk2 ( .H01(ddr_strobe_inv[2]), .N01(ddr_strobe_n2) ),
		ddr_strbclk3 ( .H01(ddr_strobe_inv[3]), .N01(ddr_strobe_n3) ),
		ddr_strbclk4 ( .H01(ddr_strobe_inv[0]), .N01(ddr_strobe_p0) ),
		ddr_strbclk5 ( .H01(ddr_strobe_inv[1]), .N01(ddr_strobe_p1) ),
		ddr_strbclk6 ( .H01(ddr_strobe_inv[2]), .N01(ddr_strobe_p2) ),
		ddr_strbclk7 ( .H01(ddr_strobe_inv[3]), .N01(ddr_strobe_p3) );

	// ddr strobe output;
	// ddr output enables;

	reg [7:0] ddr_moe;
	wire [3:0] ddr_strobe_out;

	TDBIAST2NNC1
		pad_dqs0 ( .H01(ddr_strobe_out[0]), .H02(ddr_moe[0]), .H04(1'b1), .N01(PAD_MDQS0), .N02(ddr_strobe_in[0]) ),
		pad_dqs1 ( .H01(ddr_strobe_out[1]), .H02(ddr_moe[2]), .H04(1'b1), .N01(PAD_MDQS1), .N02(ddr_strobe_in[1]) ),
		pad_dqs2 ( .H01(ddr_strobe_out[2]), .H02(ddr_moe[4]), .H04(1'b1), .N01(PAD_MDQS2), .N02(ddr_strobe_in[2]) ),
		pad_dqs3 ( .H01(ddr_strobe_out[3]), .H02(ddr_moe[6]), .H04(1'b1), .N01(PAD_MDQS3), .N02(ddr_strobe_in[3]) );

	// ddr io buffers;
	// contain input buffer, output buffer and nand ring logic;

	wire [31:24] ddr_mb3in;		// ddr input byte group 0;
	wire [23:16] ddr_mb2in;		// ddr input byte group 1;
	wire [15:8] ddr_mb1in;		// ddr input byte group 2;
	wire [7:0] ddr_mb0in;		// ddr input byte group 3;
	wire [31:0] mdata_out;		// ddr output data;

	TDBIAST2NNC1
		pad_dq0  ( .H01(mdata_out[0]),  .H02(ddr_moe[0]), .H04(1'b1), .N01(PAD_MDATA0),  .N02(ddr_mb0in[0])  ),
		pad_dq1  ( .H01(mdata_out[1]),  .H02(ddr_moe[0]), .H04(1'b1), .N01(PAD_MDATA1),  .N02(ddr_mb0in[1])  ),
		pad_dq2  ( .H01(mdata_out[2]),  .H02(ddr_moe[0]), .H04(1'b1), .N01(PAD_MDATA2),  .N02(ddr_mb0in[2])  ),
		pad_dq3  ( .H01(mdata_out[3]),  .H02(ddr_moe[0]), .H04(1'b1), .N01(PAD_MDATA3),  .N02(ddr_mb0in[3])  ),
		pad_dq4  ( .H01(mdata_out[4]),  .H02(ddr_moe[1]), .H04(1'b1), .N01(PAD_MDATA4),  .N02(ddr_mb0in[4])  ),
		pad_dq5  ( .H01(mdata_out[5]),  .H02(ddr_moe[1]), .H04(1'b1), .N01(PAD_MDATA5),  .N02(ddr_mb0in[5])  ),
		pad_dq6  ( .H01(mdata_out[6]),  .H02(ddr_moe[1]), .H04(1'b1), .N01(PAD_MDATA6),  .N02(ddr_mb0in[6])  ),
		pad_dq7  ( .H01(mdata_out[7]),  .H02(ddr_moe[1]), .H04(1'b1), .N01(PAD_MDATA7),  .N02(ddr_mb0in[7])  ),
		pad_dq8  ( .H01(mdata_out[8]),  .H02(ddr_moe[2]), .H04(1'b1), .N01(PAD_MDATA8),  .N02(ddr_mb1in[8])  ),
		pad_dq9  ( .H01(mdata_out[9]),  .H02(ddr_moe[2]), .H04(1'b1), .N01(PAD_MDATA9),  .N02(ddr_mb1in[9])  ),
		pad_dq10 ( .H01(mdata_out[10]), .H02(ddr_moe[2]), .H04(1'b1), .N01(PAD_MDATA10), .N02(ddr_mb1in[10]) ),
		pad_dq11 ( .H01(mdata_out[11]), .H02(ddr_moe[2]), .H04(1'b1), .N01(PAD_MDATA11), .N02(ddr_mb1in[11]) ),
		pad_dq12 ( .H01(mdata_out[12]), .H02(ddr_moe[3]), .H04(1'b1), .N01(PAD_MDATA12), .N02(ddr_mb1in[12]) ),
		pad_dq13 ( .H01(mdata_out[13]), .H02(ddr_moe[3]), .H04(1'b1), .N01(PAD_MDATA13), .N02(ddr_mb1in[13]) ),
		pad_dq14 ( .H01(mdata_out[14]), .H02(ddr_moe[3]), .H04(1'b1), .N01(PAD_MDATA14), .N02(ddr_mb1in[14]) ),
		pad_dq15 ( .H01(mdata_out[15]), .H02(ddr_moe[3]), .H04(1'b1), .N01(PAD_MDATA15), .N02(ddr_mb1in[15]) ),
		pad_dq16 ( .H01(mdata_out[16]), .H02(ddr_moe[4]), .H04(1'b1), .N01(PAD_MDATA16), .N02(ddr_mb2in[16]) ),
		pad_dq17 ( .H01(mdata_out[17]), .H02(ddr_moe[4]), .H04(1'b1), .N01(PAD_MDATA17), .N02(ddr_mb2in[17]) ),
		pad_dq18 ( .H01(mdata_out[18]), .H02(ddr_moe[4]), .H04(1'b1), .N01(PAD_MDATA18), .N02(ddr_mb2in[18]) ),
		pad_dq19 ( .H01(mdata_out[19]), .H02(ddr_moe[4]), .H04(1'b1), .N01(PAD_MDATA19), .N02(ddr_mb2in[19]) ),
		pad_dq20 ( .H01(mdata_out[20]), .H02(ddr_moe[5]), .H04(1'b1), .N01(PAD_MDATA20), .N02(ddr_mb2in[20]) ),
		pad_dq21 ( .H01(mdata_out[21]), .H02(ddr_moe[5]), .H04(1'b1), .N01(PAD_MDATA21), .N02(ddr_mb2in[21]) ),
		pad_dq22 ( .H01(mdata_out[22]), .H02(ddr_moe[5]), .H04(1'b1), .N01(PAD_MDATA22), .N02(ddr_mb2in[22]) ),
		pad_dq23 ( .H01(mdata_out[23]), .H02(ddr_moe[5]), .H04(1'b1), .N01(PAD_MDATA23), .N02(ddr_mb2in[23]) ),
		pad_dq24 ( .H01(mdata_out[24]), .H02(ddr_moe[6]), .H04(1'b1), .N01(PAD_MDATA24), .N02(ddr_mb3in[24]) ),
		pad_dq25 ( .H01(mdata_out[25]), .H02(ddr_moe[6]), .H04(1'b1), .N01(PAD_MDATA25), .N02(ddr_mb3in[25]) ),
		pad_dq26 ( .H01(mdata_out[26]), .H02(ddr_moe[6]), .H04(1'b1), .N01(PAD_MDATA26), .N02(ddr_mb3in[26]) ),
		pad_dq27 ( .H01(mdata_out[27]), .H02(ddr_moe[6]), .H04(1'b1), .N01(PAD_MDATA27), .N02(ddr_mb3in[27]) ),
		pad_dq28 ( .H01(mdata_out[28]), .H02(ddr_moe[7]), .H04(1'b1), .N01(PAD_MDATA28), .N02(ddr_mb3in[28]) ),
		pad_dq29 ( .H01(mdata_out[29]), .H02(ddr_moe[7]), .H04(1'b1), .N01(PAD_MDATA29), .N02(ddr_mb3in[29]) ),
		pad_dq30 ( .H01(mdata_out[30]), .H02(ddr_moe[7]), .H04(1'b1), .N01(PAD_MDATA30), .N02(ddr_mb3in[30]) ),
		pad_dq31 ( .H01(mdata_out[31]), .H02(ddr_moe[7]), .H04(1'b1), .N01(PAD_MDATA31), .N02(ddr_mb3in[31]) );

	// drr address/control output registers;

	reg		emras;
	reg		emcas;
	reg		emwe;
	reg	[1:0]	embank;
	reg	[12:0]	emaddr;
	reg		emcke;

	always @(posedge memclk) begin
		emras <=  mras;
		emcas <=  mcas;
		emwe  <=  mwe;
		embank<=  mbank;
		emaddr<=  maddr;
		emcke <=  mcke;
	end

	reg		mras_out;
	reg		mcas_out;
	reg		mwe_out;
	wire	[3:0]	mdqm_out;
	reg	[1:0]	mbank_out;
	reg	[12:0]	maddr_out;
	reg		mcke_out;

	// delay by 1/2 clock to avoid hold time issues,
	// because of clock board delay of 1/4 memclk cycle;

	always @(negedge memclk) begin
		mras_out <= ~emras;
		mcas_out <= ~emcas;
		mwe_out  <= ~emwe;
		mbank_out <=  embank;
		maddr_out <=  emaddr;
	end

	always @(negedge memclk or negedge reset_l)
	begin
		if(reset_l == 1'b0)
			mcke_out <= 1'b0;
		else
			mcke_out <= emcke;
	end

	TDBIAST2NNC1
		pad_ras ( .H01(mras_out), .H02(nring_enl), .H04(1'b1), .N01(PAD_MRAS), .N02(mras_in) ),
		pad_cas ( .H01(mcas_out), .H02(nring_enl), .H04(1'b1), .N01(PAD_MCAS), .N02(mcas_in) ),
		pad_we  ( .H01(mwe_out),  .H02(nring_enl), .H04(1'b1), .N01(PAD_MWE),  .N02(mwe_in) ),
		pad_cke  ( .H01(mcke_out), .H02(nring_enl), .H04(1'b1), .N01(PAD_MCKE), .N02(mcke_in) );

	TDBIAST2NNC1
		pad_bk0  ( .H01(mbank_out[0]), .H02(nring_enl), .H04(1'b1), .N01(PAD_MBANK0), .N02(mbank0_in) ),
		pad_bk1  ( .H01(mbank_out[1]), .H02(nring_enl), .H04(1'b1), .N01(PAD_MBANK1), .N02(mbank1_in) );

	TDBIAST2NNC1
		pad_addr0  ( .H01(maddr_out[0]),  .H02(nring_enl), .H04(1'b1), .N01(PAD_MADDR0),  .N02(maddr0_in) ),
		pad_addr1  ( .H01(maddr_out[1]),  .H02(nring_enl), .H04(1'b1), .N01(PAD_MADDR1),  .N02(maddr1_in) ),
		pad_addr2  ( .H01(maddr_out[2]),  .H02(nring_enl), .H04(1'b1), .N01(PAD_MADDR2),  .N02(maddr2_in) ),
		pad_addr3  ( .H01(maddr_out[3]),  .H02(nring_enl), .H04(1'b1), .N01(PAD_MADDR3),  .N02(maddr3_in) ),
		pad_addr4  ( .H01(maddr_out[4]),  .H02(nring_enl), .H04(1'b1), .N01(PAD_MADDR4),  .N02(maddr4_in) ),
		pad_addr5  ( .H01(maddr_out[5]),  .H02(nring_enl), .H04(1'b1), .N01(PAD_MADDR5),  .N02(maddr5_in) ),
		pad_addr6  ( .H01(maddr_out[6]),  .H02(nring_enl), .H04(1'b1), .N01(PAD_MADDR6),  .N02(maddr6_in) ),
		pad_addr7  ( .H01(maddr_out[7]),  .H02(nring_enl), .H04(1'b1), .N01(PAD_MADDR7),  .N02(maddr7_in) ),
		pad_addr8  ( .H01(maddr_out[8]),  .H02(nring_enl), .H04(1'b1), .N01(PAD_MADDR8),  .N02(maddr8_in) ),
		pad_addr9  ( .H01(maddr_out[9]),  .H02(nring_enl), .H04(1'b1), .N01(PAD_MADDR9),  .N02(maddr9_in) ),
		pad_addr10 ( .H01(maddr_out[10]), .H02(nring_enl), .H04(1'b1), .N01(PAD_MADDR10), .N02(maddr10_in)),
		pad_addr11 ( .H01(maddr_out[11]), .H02(nring_enl), .H04(1'b1), .N01(PAD_MADDR11), .N02(maddr11_in)),
		pad_addr12 ( .H01(maddr_out[12]), .H02(nring_enl), .H04(1'b1), .N01(PAD_MADDR12), .N02(maddr12_in));

	// ddr output enable logic;
	// instantiate for fast timing;
	// reset disables all output drivers;

	reg	Write;
	reg	ddr_wr_n;

	always @(posedge memclk)
		Write <= mdout_ena;

	// below two flops need async reset to remove reset path
	// from output enable logic; combine async reset with nand
	// ring enable to avoid yet another gate;

	wire moe_clr = reset_l & nring_enl;

	always @(negedge memclk or negedge moe_clr)
	begin
		if(moe_clr == 1'b0)
			ddr_wr_n <= 1'd0;
		else
			ddr_wr_n <= Write;
	end

	always @(posedge memclk or negedge moe_clr)
	begin
		if(moe_clr == 1'b0)
			ddr_moe <= 8'd0;
		else
			ddr_moe <= {8{mdout_ena | Write}};
	end


	// ddr strobe output;
	// driven like a data pin, except for the 1 select,
	// which must consider the write data phase;
	// assign ddr_strobe_out = {4{memclk ? ddr_wr_n : 1'b0}};

	// inverter is part of glitch avoidance logic, that consists of
	// clock->Q delay of flop and elay through the inverter;

	wire [3:0] ddr_strobe_on;

	TBINVX4
		ddr_d4inv0 ( .H01(ddr_wr_n), .N01(ddr_strobe_on[0]) ),
		ddr_d4inv1 ( .H01(ddr_wr_n), .N01(ddr_strobe_on[1]) ),
		ddr_d4inv2 ( .H01(ddr_wr_n), .N01(ddr_strobe_on[2]) ),
		ddr_d4inv3 ( .H01(ddr_wr_n), .N01(ddr_strobe_on[3]) );

	TBMXI2X4
		ddr_somux0 ( .H01(1'b1), .H02(ddr_strobe_on[0]), .H03(memclk), .N01(ddr_strobe_out[0])),
		ddr_somux1 ( .H01(1'b1), .H02(ddr_strobe_on[1]), .H03(memclk), .N01(ddr_strobe_out[1])),
		ddr_somux2 ( .H01(1'b1), .H02(ddr_strobe_on[2]), .H03(memclk), .N01(ddr_strobe_out[2])), 
		ddr_somux3 ( .H01(1'b1), .H02(ddr_strobe_on[3]), .H03(memclk), .N01(ddr_strobe_out[3])); 

	// ddr data mask output registers;

	reg	[3:0]	mout_01;
	reg	[3:0]	mout_23;
	reg	[3:0]	ddr_dqm_n;
	reg	[3:0]	ddr_dqm_p;

	wire	[3:0]	nxt_mout_01 = mdout_ena ? mdqm[7:4] : mout_01;
	wire	[3:0]	nxt_mout_23 = mdout_ena ? mdqm[3:0] : mout_23;

	always @(posedge memclk) begin
			mout_01 <= nxt_mout_01;
			mout_23 <= nxt_mout_23;
	end

	always @(negedge memclk) 
			ddr_dqm_n <= ~mout_01;

	always @(posedge memclk) 
			ddr_dqm_p <= ~mout_23;

	// data mask output mux;
	// muxes are clocked by memclk, equivalent logic is:
	// assign mdqm_out = memclk ? ~ddr_dqm_n : ~ddr_dqm_p;
	// H01=D0, H02=D1, H03=select, N01=output;

	TBMXI2X4
		ddr_momux0 ( .H01(ddr_dqm_p[0]), .H02(ddr_dqm_n[0]), .H03(memclk), .N01(mdqm_out[0]) ),
		ddr_momux1 ( .H01(ddr_dqm_p[1]), .H02(ddr_dqm_n[1]), .H03(memclk), .N01(mdqm_out[1]) ),
		ddr_momux2 ( .H01(ddr_dqm_p[2]), .H02(ddr_dqm_n[2]), .H03(memclk), .N01(mdqm_out[2]) ),
		ddr_momux3 ( .H01(ddr_dqm_p[3]), .H02(ddr_dqm_n[3]), .H03(memclk), .N01(mdqm_out[3]) );

	// data mask io cells;
	// contain input buffer, output buffer and nand ring logic;

	TDBIAST2NNC1
		pad_dqm0 ( .H01(mdqm_out[0]), .H02(nring_enl), .H04(1'b1), .N01(PAD_MDQM0), .N02(mdqm0_in)  ),
		pad_dqm1 ( .H01(mdqm_out[1]), .H02(nring_enl), .H04(1'b1), .N01(PAD_MDQM1), .N02(mdqm1_in) ),
		pad_dqm2 ( .H01(mdqm_out[2]), .H02(nring_enl), .H04(1'b1), .N01(PAD_MDQM2), .N02(mdqm2_in)  ),
		pad_dqm3 ( .H01(mdqm_out[3]), .H02(nring_enl), .H04(1'b1), .N01(PAD_MDQM3), .N02(mdqm3_in) );

	reg	[31:0]	dout_01;
	reg	[31:0]	dout_23;
	reg	[31:0]	ddr_do_n;
	reg	[31:0]	ddr_do_p;

	wire	[31:0]	nxt_dout_01 = mdout_ena ? mdout[63:32] : dout_01;
	wire	[31:0]	nxt_dout_23 = mdout_ena ? mdout[31:0] : dout_23;

	always @(posedge memclk) begin
			dout_01 <= nxt_dout_01;
			dout_23 <= nxt_dout_23;
	end

	always @(negedge memclk) 
			ddr_do_n <= ~dout_01;

	always @(posedge memclk) 
			ddr_do_p <= ~dout_23;

	// instantiate 2->1 muxes to create rising/falling strobe data;
	// muxes are clocked by memclk, equivalent logic is:
	// assign mdata_out = memclk ? ~ddr_do_n : ~ddr_do_p;
	// H01=D0, H02=D1, H03=select, N01=output;

	TBMXI2X4
		ddr_domux0  ( .H01(ddr_do_p[0]),  .H02(ddr_do_n[0]),  .H03(memclk), .N01(mdata_out[0])  ),
		ddr_domux1  ( .H01(ddr_do_p[1]),  .H02(ddr_do_n[1]),  .H03(memclk), .N01(mdata_out[1])  ),
		ddr_domux2  ( .H01(ddr_do_p[2]),  .H02(ddr_do_n[2]),  .H03(memclk), .N01(mdata_out[2])  ),
		ddr_domux3  ( .H01(ddr_do_p[3]),  .H02(ddr_do_n[3]),  .H03(memclk), .N01(mdata_out[3])  ),
		ddr_domux4  ( .H01(ddr_do_p[4]),  .H02(ddr_do_n[4]),  .H03(memclk), .N01(mdata_out[4])  ),
		ddr_domux5  ( .H01(ddr_do_p[5]),  .H02(ddr_do_n[5]),  .H03(memclk), .N01(mdata_out[5])  ),
		ddr_domux6  ( .H01(ddr_do_p[6]),  .H02(ddr_do_n[6]),  .H03(memclk), .N01(mdata_out[6])  ),
		ddr_domux7  ( .H01(ddr_do_p[7]),  .H02(ddr_do_n[7]),  .H03(memclk), .N01(mdata_out[7])  ),
		ddr_domux8  ( .H01(ddr_do_p[8]),  .H02(ddr_do_n[8]),  .H03(memclk), .N01(mdata_out[8])  ),
		ddr_domux9  ( .H01(ddr_do_p[9]),  .H02(ddr_do_n[9]),  .H03(memclk), .N01(mdata_out[9])  ),
		ddr_domux10 ( .H01(ddr_do_p[10]), .H02(ddr_do_n[10]), .H03(memclk), .N01(mdata_out[10]) ),
		ddr_domux11 ( .H01(ddr_do_p[11]), .H02(ddr_do_n[11]), .H03(memclk), .N01(mdata_out[11]) ),
		ddr_domux12 ( .H01(ddr_do_p[12]), .H02(ddr_do_n[12]), .H03(memclk), .N01(mdata_out[12]) ),
		ddr_domux13 ( .H01(ddr_do_p[13]), .H02(ddr_do_n[13]), .H03(memclk), .N01(mdata_out[13]) ),
		ddr_domux14 ( .H01(ddr_do_p[14]), .H02(ddr_do_n[14]), .H03(memclk), .N01(mdata_out[14]) ),
		ddr_domux15 ( .H01(ddr_do_p[15]), .H02(ddr_do_n[15]), .H03(memclk), .N01(mdata_out[15]) ),
		ddr_domux16 ( .H01(ddr_do_p[16]), .H02(ddr_do_n[16]), .H03(memclk), .N01(mdata_out[16]) ),
		ddr_domux17 ( .H01(ddr_do_p[17]), .H02(ddr_do_n[17]), .H03(memclk), .N01(mdata_out[17]) ),
		ddr_domux18 ( .H01(ddr_do_p[18]), .H02(ddr_do_n[18]), .H03(memclk), .N01(mdata_out[18]) ),
		ddr_domux19 ( .H01(ddr_do_p[19]), .H02(ddr_do_n[19]), .H03(memclk), .N01(mdata_out[19]) ),
		ddr_domux20 ( .H01(ddr_do_p[20]), .H02(ddr_do_n[20]), .H03(memclk), .N01(mdata_out[20]) ),
		ddr_domux21 ( .H01(ddr_do_p[21]), .H02(ddr_do_n[21]), .H03(memclk), .N01(mdata_out[21]) ),
		ddr_domux22 ( .H01(ddr_do_p[22]), .H02(ddr_do_n[22]), .H03(memclk), .N01(mdata_out[22]) ),
		ddr_domux23 ( .H01(ddr_do_p[23]), .H02(ddr_do_n[23]), .H03(memclk), .N01(mdata_out[23]) ),
		ddr_domux24 ( .H01(ddr_do_p[24]), .H02(ddr_do_n[24]), .H03(memclk), .N01(mdata_out[24]) ),
		ddr_domux25 ( .H01(ddr_do_p[25]), .H02(ddr_do_n[25]), .H03(memclk), .N01(mdata_out[25]) ),
		ddr_domux26 ( .H01(ddr_do_p[26]), .H02(ddr_do_n[26]), .H03(memclk), .N01(mdata_out[26]) ),
		ddr_domux27 ( .H01(ddr_do_p[27]), .H02(ddr_do_n[27]), .H03(memclk), .N01(mdata_out[27]) ),
		ddr_domux28 ( .H01(ddr_do_p[28]), .H02(ddr_do_n[28]), .H03(memclk), .N01(mdata_out[28]) ),
		ddr_domux29 ( .H01(ddr_do_p[29]), .H02(ddr_do_n[29]), .H03(memclk), .N01(mdata_out[29]) ),
		ddr_domux30 ( .H01(ddr_do_p[30]), .H02(ddr_do_n[30]), .H03(memclk), .N01(mdata_out[30]) ),
		ddr_domux31 ( .H01(ddr_do_p[31]), .H02(ddr_do_n[31]), .H03(memclk), .N01(mdata_out[31]) );

	// ddr input data delay, inserted to center set-up and hold at pins of bb

	wire [31:24] ddr_mb3in_i;	// inverted ddr input byte group 0;
	wire [23:16] ddr_mb2in_i;	// inverted ddr input byte group 1;
	wire [15:8] ddr_mb1in_i;	// inverted ddr input byte group 2;
	wire [7:0] ddr_mb0in_i;		// inverted ddr input byte group 3;

	TBINVX8
		ddr_diinv0  ( .H01(ddr_mb0in[0]),  .N01(ddr_mb0in_i[0]) ),
		ddr_diinv1  ( .H01(ddr_mb0in[1]),  .N01(ddr_mb0in_i[1]) ),
		ddr_diinv2  ( .H01(ddr_mb0in[2]),  .N01(ddr_mb0in_i[2]) ),
		ddr_diinv3  ( .H01(ddr_mb0in[3]),  .N01(ddr_mb0in_i[3]) ),
		ddr_diinv4  ( .H01(ddr_mb0in[4]),  .N01(ddr_mb0in_i[4]) ),
		ddr_diinv5  ( .H01(ddr_mb0in[5]),  .N01(ddr_mb0in_i[5]) ),
		ddr_diinv6  ( .H01(ddr_mb0in[6]),  .N01(ddr_mb0in_i[6]) ),
		ddr_diinv7  ( .H01(ddr_mb0in[7]),  .N01(ddr_mb0in_i[7]) ),
		ddr_diinv8  ( .H01(ddr_mb1in[8]),  .N01(ddr_mb1in_i[8]) ),
		ddr_diinv9  ( .H01(ddr_mb1in[9]),  .N01(ddr_mb1in_i[9]) ),
		ddr_diinv10 ( .H01(ddr_mb1in[10]), .N01(ddr_mb1in_i[10]) ),
		ddr_diinv11 ( .H01(ddr_mb1in[11]), .N01(ddr_mb1in_i[11]) ),
		ddr_diinv12 ( .H01(ddr_mb1in[12]), .N01(ddr_mb1in_i[12]) ),
		ddr_diinv13 ( .H01(ddr_mb1in[13]), .N01(ddr_mb1in_i[13]) ),
		ddr_diinv14 ( .H01(ddr_mb1in[14]), .N01(ddr_mb1in_i[14]) ),
		ddr_diinv15 ( .H01(ddr_mb1in[15]), .N01(ddr_mb1in_i[15]) ),
		ddr_diinv16 ( .H01(ddr_mb2in[16]), .N01(ddr_mb2in_i[16]) ),
		ddr_diinv17 ( .H01(ddr_mb2in[17]), .N01(ddr_mb2in_i[17]) ),
		ddr_diinv18 ( .H01(ddr_mb2in[18]), .N01(ddr_mb2in_i[18]) ),
		ddr_diinv19 ( .H01(ddr_mb2in[19]), .N01(ddr_mb2in_i[19]) ),
		ddr_diinv20 ( .H01(ddr_mb2in[20]), .N01(ddr_mb2in_i[20]) ),
		ddr_diinv21 ( .H01(ddr_mb2in[21]), .N01(ddr_mb2in_i[21]) ),
		ddr_diinv22 ( .H01(ddr_mb2in[22]), .N01(ddr_mb2in_i[22]) ),
		ddr_diinv23 ( .H01(ddr_mb2in[23]), .N01(ddr_mb2in_i[23]) ),
		ddr_diinv24 ( .H01(ddr_mb3in[24]), .N01(ddr_mb3in_i[24]) ),
		ddr_diinv25 ( .H01(ddr_mb3in[25]), .N01(ddr_mb3in_i[25]) ),
		ddr_diinv26 ( .H01(ddr_mb3in[26]), .N01(ddr_mb3in_i[26]) ),
		ddr_diinv27 ( .H01(ddr_mb3in[27]), .N01(ddr_mb3in_i[27]) ),
		ddr_diinv28 ( .H01(ddr_mb3in[28]), .N01(ddr_mb3in_i[28]) ),
		ddr_diinv29 ( .H01(ddr_mb3in[29]), .N01(ddr_mb3in_i[29]) ),
		ddr_diinv30 ( .H01(ddr_mb3in[30]), .N01(ddr_mb3in_i[30]) ),
		ddr_diinv31 ( .H01(ddr_mb3in[31]), .N01(ddr_mb3in_i[31]) );

	wire [31:24] ddr_mb3in_d;	// delayed ddr input byte group 0;
	wire [23:16] ddr_mb2in_d;	// delayed ddr input byte group 1;
	wire [15:8] ddr_mb1in_d;	// delayed ddr input byte group 2;
	wire [7:0] ddr_mb0in_d;		// delayed ddr input byte group 3;

	TBINVX16
		ddr_didly0  ( .H01(ddr_mb0in_i[0]),  .N01(ddr_mb0in_d[0]) ),
		ddr_didly1  ( .H01(ddr_mb0in_i[1]),  .N01(ddr_mb0in_d[1]) ),
		ddr_didly2  ( .H01(ddr_mb0in_i[2]),  .N01(ddr_mb0in_d[2]) ),
		ddr_didly3  ( .H01(ddr_mb0in_i[3]),  .N01(ddr_mb0in_d[3]) ),
		ddr_didly4  ( .H01(ddr_mb0in_i[4]),  .N01(ddr_mb0in_d[4]) ),
		ddr_didly5  ( .H01(ddr_mb0in_i[5]),  .N01(ddr_mb0in_d[5]) ),
		ddr_didly6  ( .H01(ddr_mb0in_i[6]),  .N01(ddr_mb0in_d[6]) ),
		ddr_didly7  ( .H01(ddr_mb0in_i[7]),  .N01(ddr_mb0in_d[7]) ),
		ddr_didly8  ( .H01(ddr_mb1in_i[8]),  .N01(ddr_mb1in_d[8]) ),
		ddr_didly9  ( .H01(ddr_mb1in_i[9]),  .N01(ddr_mb1in_d[9]) ),
		ddr_didly10 ( .H01(ddr_mb1in_i[10]), .N01(ddr_mb1in_d[10]) ),
		ddr_didly11 ( .H01(ddr_mb1in_i[11]), .N01(ddr_mb1in_d[11]) ),
		ddr_didly12 ( .H01(ddr_mb1in_i[12]), .N01(ddr_mb1in_d[12]) ),
		ddr_didly13 ( .H01(ddr_mb1in_i[13]), .N01(ddr_mb1in_d[13]) ),
		ddr_didly14 ( .H01(ddr_mb1in_i[14]), .N01(ddr_mb1in_d[14]) ),
		ddr_didly15 ( .H01(ddr_mb1in_i[15]), .N01(ddr_mb1in_d[15]) ),
		ddr_didly16 ( .H01(ddr_mb2in_i[16]), .N01(ddr_mb2in_d[16]) ),
		ddr_didly17 ( .H01(ddr_mb2in_i[17]), .N01(ddr_mb2in_d[17]) ),
		ddr_didly18 ( .H01(ddr_mb2in_i[18]), .N01(ddr_mb2in_d[18]) ),
		ddr_didly19 ( .H01(ddr_mb2in_i[19]), .N01(ddr_mb2in_d[19]) ),
		ddr_didly20 ( .H01(ddr_mb2in_i[20]), .N01(ddr_mb2in_d[20]) ),
		ddr_didly21 ( .H01(ddr_mb2in_i[21]), .N01(ddr_mb2in_d[21]) ),
		ddr_didly22 ( .H01(ddr_mb2in_i[22]), .N01(ddr_mb2in_d[22]) ),
		ddr_didly23 ( .H01(ddr_mb2in_i[23]), .N01(ddr_mb2in_d[23]) ),
		ddr_didly24 ( .H01(ddr_mb3in_i[24]), .N01(ddr_mb3in_d[24]) ),
		ddr_didly25 ( .H01(ddr_mb3in_i[25]), .N01(ddr_mb3in_d[25]) ),
		ddr_didly26 ( .H01(ddr_mb3in_i[26]), .N01(ddr_mb3in_d[26]) ),
		ddr_didly27 ( .H01(ddr_mb3in_i[27]), .N01(ddr_mb3in_d[27]) ),
		ddr_didly28 ( .H01(ddr_mb3in_i[28]), .N01(ddr_mb3in_d[28]) ),
		ddr_didly29 ( .H01(ddr_mb3in_i[29]), .N01(ddr_mb3in_d[29]) ),
		ddr_didly30 ( .H01(ddr_mb3in_i[30]), .N01(ddr_mb3in_d[30]) ),
		ddr_didly31 ( .H01(ddr_mb3in_i[31]), .N01(ddr_mb3in_d[31]) );

	// ddr input capture flops;
	// enabled by fan-out strobes;
	// critical path to transfer data to internal memclk domain;

	reg [31:0] ddr_mdin_p;		// posedge data;
	reg [31:0] ddr_mdin_n;		// negedge data;

	always @(negedge ddr_strobe_n3)
		ddr_mdin_n[31:24] <= ddr_mb3in_d[31:24];
	always @(negedge ddr_strobe_n2)
		ddr_mdin_n[23:16] <= ddr_mb2in_d[23:16];
	always @(negedge ddr_strobe_n1)
		ddr_mdin_n[15:8] <= ddr_mb1in_d[15:8];
	always @(negedge ddr_strobe_n0)
		ddr_mdin_n[7:0] <= ddr_mb0in_d[7:0];

	always @(posedge ddr_strobe_p3)
		ddr_mdin_p[31:24] <= ddr_mb3in[31:24];
	always @(posedge ddr_strobe_p2)
		ddr_mdin_p[23:16] <= ddr_mb2in[23:16];
	always @(posedge ddr_strobe_p1)
		ddr_mdin_p[15:8] <= ddr_mb1in[15:8];
	always @(posedge ddr_strobe_p0)
		ddr_mdin_p[7:0] <= ddr_mb0in[7:0];

	wire	[63:0]	mdin;
	reg	[63:0]	mdin_rs;
	reg	[31:0]	mdin_p;
	reg	[31:0]	mdin_n;

	always @(posedge memclk)
		mdin_p <=  ddr_mdin_p;

	always @(negedge memclk)
		mdin_n <=  ddr_mdin_n;

	always @(negedge memclk)
		mdin_rs <=  {mdin_n,mdin_p};

	wire	[63:0]	mdin_pn = {mdin_p,mdin_n};

	assign	mdin[15: 0] = strobe_rev[1] ? mdin_rs[15: 0] : mdin_pn[15: 0];
	assign	mdin[31:16] = strobe_rev[2] ? mdin_rs[31:16] : mdin_pn[31:16];
	assign	mdin[47:32] = strobe_rev[3] ? mdin_rs[47:32] : mdin_pn[47:32];
	assign	mdin[63:48] = strobe_rev[4] ? mdin_rs[63:48] : mdin_pn[63:48];

	// video output registers;

	reg [6:0] r_vdata;
	reg r_vsync;

	always @(posedge vclock)
	begin
		if(avrst_l == 1'b0) begin
			r_vdata <= 7'd0;
			r_vsync <= 1'b0;
		end else begin
			r_vdata <= vdata;
			r_vsync <= vsync;
		end
	end

	// digital video io cells;
	// sharable by test bus;

	TDBIAC33NL03
		pad_vclk ( .N01(PAD_VCLOCK), .N02(vclock_in), .H01(vclock),     .H03(nring_enl) ),
		pad_vd0 ( .N01(PAD_VDATA0), .N02(vdata0_in), .H01(r_vdata[0]), .H03(nring_enl) ),
		pad_vd1 ( .N01(PAD_VDATA1), .N02(vdata1_in), .H01(r_vdata[1]), .H03(nring_enl) ),
		pad_vd2 ( .N01(PAD_VDATA2), .N02(vdata2_in), .H01(r_vdata[2]), .H03(nring_enl) ),
		pad_vd3 ( .N01(PAD_VDATA3), .N02(vdata3_in), .H01(r_vdata[3]), .H03(nring_enl) ),
		pad_vd4 ( .N01(PAD_VDATA4), .N02(vdata4_in), .H01(r_vdata[4]), .H03(nring_enl) ),
		pad_vd5 ( .N01(PAD_VDATA5), .N02(vdata5_in), .H01(r_vdata[5]), .H03(nring_enl) ),
		pad_vd6 ( .N01(PAD_VDATA6), .N02(vdata6_in), .H01(r_vdata[6]), .H03(nring_enl) ),
		pad_vsyn  ( .N01(PAD_VSYNC),  .N02(vsync_in),  .H01(r_vsync),    .H03(nring_enl) );

	// instantiate triple video dac;

	wire vdac_test;			// vdac test mode;
	wire vdac_bunri;		// vdac test mode;
	wire vdac_mode1;		// vdac test mode;
	wire vdac_mode2;		// vdac test mode;

	assign vdac_test  = 1'b0;
	assign vdac_bunri = 1'b0;
	assign vdac_mode1 = 1'b0;
	assign vdac_mode2 = 1'b0;

	AAD3835BM vdac (
	.AVDD3		(PAD_AVDD3),
	.AVDD2		(PAD_AVDD2),
	.AVDD1		(PAD_AVDD1),
	.AGND3		(PAD_AGND3),
	.AGND2		(PAD_AGND2),
	.AGND1		(PAD_AGND1),
	.CLKA		(vdac_clk),
	.CLKB		(vdac_clk),
	.CLKC		(vdac_clk),
	.DA7		(vda[7]),
	.DA6		(vda[6]),
	.DA5		(vda[5]),
	.DA4		(vda[4]),
	.DA3		(vda[3]),
	.DA2		(vda[2]),
	.DA1		(vda[1]),
	.DA0		(vda[0]),
	.DB7		(vdb[7]),
	.DB6		(vdb[6]),
	.DB5		(vdb[5]),
	.DB4		(vdb[4]),
	.DB3		(vdb[3]),
	.DB2		(vdb[2]),
	.DB1		(vdb[1]),
	.DB0		(vdb[0]),
	.DC7		(vdc[7]),
	.DC6		(vdc[6]),
	.DC5		(vdc[5]),
	.DC4		(vdc[4]),
	.DC3		(vdc[3]),
	.DC2		(vdc[2]),
	.DC1		(vdc[1]),
	.DC0		(vdc[0]),
	.VOA		(PAD_VOA),
	.VOB		(PAD_VOB),
	.VOC		(PAD_VOC),
	.PDB		(vdac_pd),
	.MODE1		(vdac_mode1),
	.MODE2		(vdac_mode2),
	.BUNRI		(vdac_bunri),	// test mode;
	.TEST		(vdac_test),	// normal mode;
	.TBI9		(1'b0),			// test bus inputs;
	.TBI8		(1'b0),
	.TBI7		(1'b0),
	.TBI6		(1'b0),
	.TBI5		(1'b0),
	.TBI4		(1'b0),
	.TBI3		(1'b0),
	.TBI2		(1'b0),
	.TBI1		(1'b0),
	.TBI0		(1'b0),
	.ATBO9		(),				// test bus outputs;
	.ATBO8		(),
	.ATBO7		(),
	.ATBO6		(),
	.ATBO5		(),
	.ATBO4		(),
	.ATBO3		(),
	.ATBO2		(),
	.ATBO1		(),
	.ATBO0		()
	);

	// instantiate digital audio io cells;

	TDBIAC33NL03
		pad_aclk ( .N01(PAD_ACLOCK), .N02(aclock_in), .H01(aclock), .H03(nring_enl) ),
		pad_ad  ( .N01(PAD_ADATA),  .N02(adata_in), .H01(adata),  .H03(nring_enl) ),
		pad_aw  ( .N01(PAD_AWORD),  .N02(aword_in),  .H01(aword),  .H03(nring_enl) );

	// joy channel ports;

	wire jchan1_oe = nring_enl & jchan_oe[1];
	wire jchan2_oe = nring_enl & jchan_oe[2];
	wire jchan3_oe = nring_enl & jchan_oe[3];
	wire jchan1_in, jchan2_in, jchan3_in;

	TDBIAC33NL12
		pad_jc1 ( .N01(PAD_JCHAN1), .N02(jchan1_in), .H01(1'b0), .H03(jchan1_oe) ),
		pad_jc2 ( .N01(PAD_JCHAN2), .N02(jchan2_in), .H01(1'b0), .H03(jchan2_oe) ),
		pad_jc3 ( .N01(PAD_JCHAN3), .N02(jchan3_in), .H01(1'b0), .H03(jchan3_oe) );

	// local joystick;

	TDIPAC33N
		pad_x0 ( .H01(PAD_LX0), .N01(lctrl_x[0]) ),
		pad_x1 ( .H01(PAD_LX1), .N01(lctrl_x[1]) ),
		pad_y0 ( .H01(PAD_LY0), .N01(lctrl_y[0]) ),
		pad_y1 ( .H01(PAD_LY1), .N01(lctrl_y[1]) );

	// flop with clock enable;

	always @(posedge sysclk)
	begin
		if(jchan_ena[1])
			jchan_in[1] <= jchan1_in;
		if(jchan_ena[2])
			jchan_in[2] <= jchan2_in;
		if(jchan_ena[3])
			jchan_in[3] <= jchan3_in;
	end

	// io registers;

	reg [15:0] rio_out;			// io bus output register;
	reg [1:0] rio_oe;			// registered output enables;
	reg rio_rst;				// rst output register;
	reg rio_ale;				// ale output register;
	reg [3:0] rio_cs;			// cs output registers;
	reg rio_ior;				// ior output register;
	reg rio_iow;				// iow output register;
	reg rio_dmack;				// dmack output register;

	wire	[15:0]	io_ad_in;

	wire	io_intr_in;
	wire	io_dmarq_in;

	always @(posedge sysclk)
	begin
		if(io_ena)
			io_in <=  io_ad_in;
		rio_out   <=  io_out;
		rio_oe    <=  io_oe;
		rio_rst   <= ~io_rst;
		rio_ale   <=  io_ale;
		rio_cs    <= ~io_cs;
		rio_ior   <= ~io_ior;
		rio_iow   <= ~io_iow;
		rio_dmack <= ~io_dmack;
		io_dmarq  <=  io_dmarq_in;
		io_intr   <=  io_intr_in;
	end

	wire	nr_rio_oe0 = nring_enl & rio_oe[0];
	wire	nr_rio_oe1 = nring_enl & rio_oe[1];

	TDBIAC33NL12
		pad_ioad0  ( .N01(PAD_IO_AD0),  .N02(io_ad_in[0]),  .H01(rio_out[0]),  .H03(nr_rio_oe0) ),
		pad_ioad1  ( .N01(PAD_IO_AD1),  .N02(io_ad_in[1]),  .H01(rio_out[1]),  .H03(nr_rio_oe0) ),
		pad_ioad2  ( .N01(PAD_IO_AD2),  .N02(io_ad_in[2]),  .H01(rio_out[2]),  .H03(nr_rio_oe0) ),
		pad_ioad3  ( .N01(PAD_IO_AD3),  .N02(io_ad_in[3]),  .H01(rio_out[3]),  .H03(nr_rio_oe0) ),
		pad_ioad4  ( .N01(PAD_IO_AD4),  .N02(io_ad_in[4]),  .H01(rio_out[4]),  .H03(nr_rio_oe0) ),
		pad_ioad5  ( .N01(PAD_IO_AD5),  .N02(io_ad_in[5]),  .H01(rio_out[5]),  .H03(nr_rio_oe0) ),
		pad_ioad6  ( .N01(PAD_IO_AD6),  .N02(io_ad_in[6]),  .H01(rio_out[6]),  .H03(nr_rio_oe0) ),
		pad_ioad7  ( .N01(PAD_IO_AD7),  .N02(io_ad_in[7]),  .H01(rio_out[7]),  .H03(nr_rio_oe1) ),
		pad_ioad8  ( .N01(PAD_IO_AD8),  .N02(io_ad_in[8]),  .H01(rio_out[8]),  .H03(nr_rio_oe1) ),
		pad_ioad9  ( .N01(PAD_IO_AD9),  .N02(io_ad_in[9]),  .H01(rio_out[9]),  .H03(nr_rio_oe1) ),
		pad_ioad10 ( .N01(PAD_IO_AD10), .N02(io_ad_in[10]), .H01(rio_out[10]), .H03(nr_rio_oe1) ),
		pad_ioad11 ( .N01(PAD_IO_AD11), .N02(io_ad_in[11]), .H01(rio_out[11]), .H03(nr_rio_oe1) ),
		pad_ioad12 ( .N01(PAD_IO_AD12), .N02(io_ad_in[12]), .H01(rio_out[12]), .H03(nr_rio_oe1) ),
		pad_ioad13 ( .N01(PAD_IO_AD13), .N02(io_ad_in[13]), .H01(rio_out[13]), .H03(nr_rio_oe1) ),
		pad_ioad14 ( .N01(PAD_IO_AD14), .N02(io_ad_in[14]), .H01(rio_out[14]), .H03(nr_rio_oe1) ),
		pad_ioad15 ( .N01(PAD_IO_AD15), .N02(io_ad_in[15]), .H01(rio_out[15]), .H03(nr_rio_oe1) );

	TDBIAC33NL12
		pad_iorst ( .N01(PAD_IO_RST), .N02(io_rst_in), .H01(rio_rst),   .H03(nring_enl) ),
		pad_iocs0 ( .N01(PAD_IO_CS0), .N02(io_cs0_in), .H01(rio_cs[0]), .H03(nring_enl) ),
		pad_iocs1 ( .N01(PAD_IO_CS1), .N02(io_cs1_in), .H01(rio_cs[1]), .H03(nring_enl) ),
		pad_iocs2 ( .N01(PAD_IO_CS2), .N02(io_cs2_in), .H01(rio_cs[2]), .H03(nring_enl) ),
		pad_iocs3 ( .N01(PAD_IO_CS3), .N02(io_cs3_in), .H01(rio_cs[3]), .H03(nring_enl) ),
		pad_ioale ( .N01(PAD_IO_ALE), .N02(io_ale_in), .H01(rio_ale),   .H03(nring_enl) ),
		pad_ior   ( .N01(PAD_IO_IOR), .N02(io_ior_in), .H01(rio_ior),   .H03(nring_enl) ),
		pad_iow   ( .N01(PAD_IO_IOW), .N02(io_iow_in), .H01(rio_iow),   .H03(nring_enl) );

	TDIPAC33N pad_iointr  ( .H01(PAD_IO_INTR),  .N01(io_intr_in) );
	TDIPAC33D pad_iodmarq ( .H01(PAD_IO_DMARQ), .N01(io_dmarq_in) );

	TDOPAC33NL12 pad_dmack ( .N01(PAD_IO_DMACK), .H01(rio_dmack) );

	// io bus io registers;

	reg [3:0] rfl_ce;	// ce output register;
	reg rfl_cle;		// cle output register;
	reg rfl_ale;		// ale output register;
	reg rfl_we;			// we output register;
	reg rfl_re;			// re output register;
	reg rfl_wp;			// wp output register;
	reg rfl_ryby;		// ryby input register;
	reg rfl_md;			// md input register;

	always @(posedge sysclk)
	begin
		rfl_ce   <= ~fl_ce;
		rfl_cle  <=  fl_cle;
		rfl_ale  <=  fl_ale;
		rfl_we   <= ~fl_we;
		rfl_re   <= ~fl_re;
		rfl_wp   <= ~fl_wp;
		rfl_ryby <=  fl_ryby;
		rfl_md   <=  fl_md;
	end

	TDIPAC33N pad_flryby ( .H01(PAD_FL_RYBY), .N01(fl_ryby) );
	TDIPAC33N pad_flmd   ( .H01(PAD_FL_MD),   .N01(fl_md) );

	TDBIAC33NL09
		pad_flale  ( .N01(PAD_FL_ALE), .N02(fl_ale_in), .H01(rfl_ale),   .H03(nring_enl) ),
		pad_flcle  ( .N01(PAD_FL_CLE), .N02(fl_cle_in), .H01(rfl_cle),   .H03(nring_enl) ),
		pad_flre   ( .N01(PAD_FL_RE),  .N02(fl_re_in),  .H01(rfl_re),    .H03(nring_enl) ),
		pad_flwe   ( .N01(PAD_FL_WE),  .N02(fl_we_in),  .H01(rfl_we),    .H03(nring_enl) ),
		pad_flwp   ( .N01(PAD_FL_WP),  .N02(fl_wp_in),  .H01(rfl_wp),    .H03(nring_enl) ),
		pad_flce3  ( .N01(PAD_FL_CE3), .N02(),          .H01(rfl_ce[3]), .H03(1'b1)      ),
		pad_flce2  ( .N01(PAD_FL_CE2), .N02(fl_ce2_in), .H01(rfl_ce[2]), .H03(nring_enl) ),
		pad_flce1  ( .N01(PAD_FL_CE1), .N02(fl_ce1_in), .H01(rfl_ce[1]), .H03(nring_enl) ),
		pad_flce0  ( .N01(PAD_FL_CE0), .N02(fl_ce0_in), .H01(rfl_ce[0]), .H03(nring_enl) );

	// gpio io registers;

	reg [3:0] rgpio_in;		// input register;
	reg [3:0] rgpio_oe;		// output enables;
	reg [3:0] rgpio_out;	// output register;

	always @(posedge sysclk)
	begin
		rgpio_in <= gpio_in;
		rgpio_oe <= gpio_oe;
		rgpio_out <= gpio_out;
	end

	wire	nr_rgpio_oe0 = rgpio_oe[0] & nring_enl;
	wire	nr_rgpio_oe1 = rgpio_oe[1] & nring_enl;
	wire	nr_rgpio_oe2 = rgpio_oe[2] & nring_enl;
	wire	nr_rgpio_oe3 = rgpio_oe[3] & nring_enl;

	TDBIAC33NL12
		pad_gio0 ( .N01(PAD_GPIO0), .N02(gpio_in[0]), .H01(rgpio_out[0]), .H03(nr_rgpio_oe0) ),
		pad_gio1 ( .N01(PAD_GPIO1), .N02(gpio_in[1]), .H01(rgpio_out[1]), .H03(nr_rgpio_oe1) ),
		pad_gio2 ( .N01(PAD_GPIO2), .N02(gpio_in[2]), .H01(rgpio_out[2]), .H03(nr_rgpio_oe2) ),
		pad_gio3 ( .N01(PAD_GPIO3), .N02(gpio_in[3]), .H01(rgpio_out[3]), .H03(nr_rgpio_oe3) );

	// instantiate usb tranceivers;

	usb_xcvr usb_xcvr0 (
		.usb_dpo(usb_dpo[0]),
		.usbxr_ose(usbxr_ose[0]),
		.usbxr_oen(usbxr_oen[0]),
		.usbxr_ien(usbxr_ien[0]),
		.usbxr_fl(usbxr_fl[0]),
		.usb_vbus_vld(usb_vbus_vld[0]),
		
		.usbxr_y1(usbxr_y1[0]),
		.usb_dp(usb_dp[0]),
		.usb_dm(usb_dm[0]),
		
		.dp_o(PAD_USB_DPLUS0),
		.dm_o(PAD_USB_DMINUS0) 
	);

	usb_xcvr usb_xcvr1 (
		.usb_dpo(usb_dpo[1]),
		.usbxr_ose(usbxr_ose[1]),
		.usbxr_oen(usbxr_oen[1]),
		.usbxr_ien(usbxr_ien[1]),
		.usbxr_fl(usbxr_fl[1]),
		.usb_vbus_vld(usb_vbus_vld[1]),
		
		.usbxr_y1(usbxr_y1[1]),
		.usb_dp(usb_dp[1]),
		.usb_dm(usb_dm[1]),
		
		.dp_o(PAD_USB_DPLUS1),
		.dm_o(PAD_USB_DMINUS1) 
	);

	TDIPAC33N
		pad_usbid0 ( .H01(PAD_USB_ID0), .N01(usb_id[0]) ),
		pad_usbid1 ( .H01(PAD_USB_ID1), .N01(usb_id[1]) );

	TDIPAC33N
		pad_usb_vld0 ( .H01(PAD_USB_VBUS_VLD0), .N01(usb_vbus_vld[0]) ),
		pad_usb_vld1 ( .H01(PAD_USB_VBUS_VLD1), .N01(usb_vbus_vld[1]) );

	wire usb_vbus_on1 = ~usb_vbus_on_n[1] ;
	wire usb_vbus_on0 = ~usb_vbus_on_n[0] ;

	TDBIAC33NL03
		pad_usb_on1 ( .N01(PAD_USB_VBUS_ON1), .N02(usb_vbus_on1_in), .H01(usb_vbus_on1), .H03(nring_enl) ),
		pad_usb_on0 ( .N01(PAD_USB_VBUS_ON0), .N02(usb_vbus_on0_in), .H01(usb_vbus_on0), .H03(nring_enl) );

	wire usb_dp_high_en1 = usb_dp_high[1] & nring_enl ;
	wire usb_dp_high_en0 = usb_dp_high[0] & nring_enl ;

	TDBIAC33NL03
		pad_usb_dp_h1 ( .N01(PAD_USB_DP_HIGH1), .N02(usb_dp_high1_in), .H01(1'b1), .H03(usb_dp_high_en1) ),
		pad_usb_dp_h0 ( .N01(PAD_USB_DP_HIGH0), .N02(usb_dp_high0_in), .H01(1'b1), .H03(usb_dp_high_en0) );

	wire usb_d_low_en1 = ~usb_d_low_n[1] & nring_enl ;
	wire usb_d_low_en0 = ~usb_d_low_n[0] & nring_enl ;

	TDBIAC33NL03
		pad_usb_d_l1 ( .N01(PAD_USB_D_LOW_N1), .N02(usb_d_low_n1_in), .H01(1'b0), .H03(usb_d_low_en1) ),
		pad_usb_d_l0 ( .N01(PAD_USB_D_LOW_N0), .N02(usb_d_low_n0_in), .H01(1'b0), .H03(usb_d_low_en0) );

	wire	trst_in, tdi_in, tms_in, tck_in;
	
	TDIPAC33N pad_t_rst ( .H01(PAD_TRST),    .N01(trst_in) );
	TDIPAC33N pad_t_di  ( .H01(PAD_TDI),     .N01(tdi_in) );
	TDIPAC33N pad_t_ms  ( .H01(PAD_TMS),     .N01(tms_in) );
	TDIPAC33N pad_t_ck  ( .H01(PAD_TCK),     .N01(tck_in) );
	TDIPAC33D pad_jtag    ( .H01(PAD_JTAG_EN), .N01(jtag_force) );

	assign tena = jtag_ena | jtag_force;
	assign trst = trst_in & tena;
	assign tdi = tdi_in & tena;
	assign tms = tms_in & tena;
	assign tck = tck_in & tena;

	wire	nring_out = 
  ~(mclk1_in
& ~(mclk0_in
& ~(ddr_strobe_in[3]
& ~(ddr_strobe_in[2]
& ~(ddr_strobe_in[1]
& ~(ddr_strobe_in[0]
& ~(ddr_mb3in[31]
& ~(ddr_mb3in[30]
& ~(ddr_mb3in[29]
& ~(ddr_mb3in[28]
& ~(ddr_mb3in[27]
& ~(ddr_mb3in[26]
& ~(ddr_mb3in[25]
& ~(ddr_mb3in[24]
& ~(ddr_mb2in[23]
& ~(ddr_mb2in[22]
& ~(ddr_mb2in[21]
& ~(ddr_mb2in[20]
& ~(ddr_mb2in[19]
& ~(ddr_mb2in[18]
& ~(ddr_mb2in[17]
& ~(ddr_mb2in[16]
& ~(ddr_mb1in[15]
& ~(ddr_mb1in[14]
& ~(ddr_mb1in[13]
& ~(ddr_mb1in[12]
& ~(ddr_mb1in[11]
& ~(ddr_mb1in[10]
& ~(ddr_mb1in[9]
& ~(ddr_mb1in[8]
& ~(ddr_mb0in[7]
& ~(ddr_mb0in[6]
& ~(ddr_mb0in[5]
& ~(ddr_mb0in[4]
& ~(ddr_mb0in[3]
& ~(ddr_mb0in[2]
& ~(ddr_mb0in[1]
& ~(ddr_mb0in[0]
& ~(mras_in
& ~(mcas_in
& ~(mwe_in
& ~(mbank1_in
& ~(mbank0_in
& ~(mcke_in
& ~(maddr12_in
& ~(maddr11_in
& ~(maddr10_in
& ~(maddr9_in
& ~(maddr8_in
& ~(maddr7_in
& ~(maddr6_in
& ~(maddr5_in
& ~(maddr4_in
& ~(maddr3_in
& ~(maddr2_in
& ~(maddr1_in
& ~(maddr0_in
& ~(mdqm3_in
& ~(mdqm2_in
& ~(mdqm1_in
& ~(mdqm0_in
& ~(vdata6_in
& ~(vdata5_in
& ~(vdata4_in
& ~(vdata3_in
& ~(vdata2_in
& ~(vdata1_in
& ~(vdata0_in
& ~(vclock_in
& ~(vsync_in
& ~(aclock_in
& ~(adata_in
& ~(aword_in
& ~(jchan3_in
& ~(jchan2_in
& ~(jchan1_in
& ~(lctrl_x[1]
& ~(lctrl_x[0]
& ~(lctrl_y[1]
& ~(lctrl_y[0]
& ~(io_intr_in
& ~(io_ad_in[15]
& ~(io_ad_in[14]
& ~(io_ad_in[13]
& ~(io_ad_in[12]
& ~(io_ad_in[11]
& ~(io_ad_in[10]
& ~(io_ad_in[9]
& ~(io_ad_in[8]
& ~(io_ad_in[7]
& ~(io_ad_in[6]
& ~(io_ad_in[5]
& ~(io_ad_in[4]
& ~(io_ad_in[3]
& ~(io_ad_in[2]
& ~(io_ad_in[1]
& ~(io_ad_in[0]
& ~(io_rst_in
& ~(io_cs3_in
& ~(io_cs2_in
& ~(io_cs1_in
& ~(io_cs0_in
& ~(io_ale_in
& ~(io_ior_in
& ~(io_iow_in
& ~(fl_ryby
& ~(fl_md
& ~(fl_ale_in
& ~(fl_cle_in
& ~(fl_re_in
& ~(fl_we_in
& ~(fl_wp_in
& ~(fl_ce2_in
& ~(fl_ce1_in
& ~(fl_ce0_in
& ~(gpio_in[3]
& ~(gpio_in[2]
& ~(gpio_in[1]
& ~(gpio_in[0]
& ~(usb_id[1]
& ~(usb_id[0]
& ~(usb_vbus_on1_in
& ~(usb_vbus_on0_in
& ~(usb_dp_high1_in
& ~(usb_dp_high0_in
& ~(usb_d_low_n1_in
& ~(usb_d_low_n0_in
& ~(trst_in
& ~(tdi_in
& ~(tms_in
& ~(tck_in
& ~(tmc_in
& ~(button
& ~(sysclk_in
& ~(rst_l_in
))))))))))
))))))))))
))))))))))
))))))))))
))))))))))
))))))))))
))))))))))
))))))))))
))))))))))
))))))))))
))))))))))
))))))))))
))))))))))
)))));

	wire	tdo_out = nring_enl ? tdo : nring_out;
	wire	tdo_en  = tdoen | ~nring_enl;

	TDBIAC33NL03 pad_t_do ( .N01(PAD_TDO), .N02(), .H01(tdo_out), .H03(tdo_en) );

	// either instantiate the cpu model
	// or the behavioral bus model;

	wire [2:0] divmode;			// cpu frequency mode;
	wire coldrst_l;				// cpu cold reset;
	wire warmrst_l;				// cpu wam reset;

	wire [31:0] sysad_out;		// system addr/data from cpu;
	wire [4:0] syscmd_out;		// system command from cpu;
	wire pvalid_l;				// processor data valid;
	wire [31:0] `TCO sysad_in;	// system addr/data to cpu;
	wire [4:0] `TCO syscmd_in;	// system command to cpu;
	wire `TCO eok_l;			// external agent ok;
	wire `TCO evalid_l;			// external data valid;
	wire [4:0] `TCO int_l;		// cpu interrupts;
	wire `TCO nmi_l;			// non-maskable interrupt;

	// instantiate cpu model;
	// this is either the NEC model or the behavioral bus model (ipc);
	// compile time definitions pulls model from nec or our library;
	// makeing both look the same makes gate-level ipc possible;

	NB4300V01 cpu (
		.MASTERCLOCK(sysclk),
		.ISYSCMD4(syscmd_in[4]),
		.ISYSCMD3(syscmd_in[3]),
		.ISYSCMD2(syscmd_in[2]),
		.ISYSCMD1(syscmd_in[1]),
		.ISYSCMD0(syscmd_in[0]),
		.OSYSCMD4(syscmd_out[4]),
		.OSYSCMD3(syscmd_out[3]),
		.OSYSCMD2(syscmd_out[2]),
		.OSYSCMD1(syscmd_out[1]),
		.OSYSCMD0(syscmd_out[0]),
		.ISYSAD31(sysad_in[31]),
		.ISYSAD30(sysad_in[30]),
		.ISYSAD29(sysad_in[29]),
		.ISYSAD28(sysad_in[28]),
		.ISYSAD27(sysad_in[27]),
		.ISYSAD26(sysad_in[26]),
		.ISYSAD25(sysad_in[25]),
		.ISYSAD24(sysad_in[24]),
		.ISYSAD23(sysad_in[23]),
		.ISYSAD22(sysad_in[22]),
		.ISYSAD21(sysad_in[21]),
		.ISYSAD20(sysad_in[20]),
		.ISYSAD19(sysad_in[19]),
		.ISYSAD18(sysad_in[18]),
		.ISYSAD17(sysad_in[17]),
		.ISYSAD16(sysad_in[16]),
		.ISYSAD15(sysad_in[15]),
		.ISYSAD14(sysad_in[14]),
		.ISYSAD13(sysad_in[13]),
		.ISYSAD12(sysad_in[12]),
		.ISYSAD11(sysad_in[11]),
		.ISYSAD10(sysad_in[10]),
		.ISYSAD9(sysad_in[9]),
		.ISYSAD8(sysad_in[8]),
		.ISYSAD7(sysad_in[7]),
		.ISYSAD6(sysad_in[6]),
		.ISYSAD5(sysad_in[5]),
		.ISYSAD4(sysad_in[4]),
		.ISYSAD3(sysad_in[3]),
		.ISYSAD2(sysad_in[2]),
		.ISYSAD1(sysad_in[1]),
		.ISYSAD0(sysad_in[0]),
		.OSYSAD31(sysad_out[31]),
		.OSYSAD30(sysad_out[30]),
		.OSYSAD29(sysad_out[29]),
		.OSYSAD28(sysad_out[28]),
		.OSYSAD27(sysad_out[27]),
		.OSYSAD26(sysad_out[26]),
		.OSYSAD25(sysad_out[25]),
		.OSYSAD24(sysad_out[24]),
		.OSYSAD23(sysad_out[23]),
		.OSYSAD22(sysad_out[22]),
		.OSYSAD21(sysad_out[21]),
		.OSYSAD20(sysad_out[20]),
		.OSYSAD19(sysad_out[19]),
		.OSYSAD18(sysad_out[18]),
		.OSYSAD17(sysad_out[17]),
		.OSYSAD16(sysad_out[16]),
		.OSYSAD15(sysad_out[15]),
		.OSYSAD14(sysad_out[14]),
		.OSYSAD13(sysad_out[13]),
		.OSYSAD12(sysad_out[12]),
		.OSYSAD11(sysad_out[11]),
		.OSYSAD10(sysad_out[10]),
		.OSYSAD9(sysad_out[9]),
		.OSYSAD8(sysad_out[8]),
		.OSYSAD7(sysad_out[7]),
		.OSYSAD6(sysad_out[6]),
		.OSYSAD5(sysad_out[5]),
		.OSYSAD4(sysad_out[4]),
		.OSYSAD3(sysad_out[3]),
		.OSYSAD2(sysad_out[2]),
		.OSYSAD1(sysad_out[1]),
		.OSYSAD0(sysad_out[0]),
		.SYSEN(),				// unused
		.PVALIDB(pvalid_l),
		.PREQB(),				// unused;
		.PMASTERB(),			// unused;
		.NMIB(nmi_l),
		.INTB4(int_l[4]),
		.INTB3(int_l[3]),
		.INTB2(int_l[2]),
		.INTB1(int_l[1]),
		.INTB0(int_l[0]),
		.EVALIDB(evalid_l),
		.EREQB(1'b1),			// never requested;
		.EOKB(eok_l),
		.DIVMODE2(divmode[2]),
		.DIVMODE1(divmode[1]),
		.DIVMODE0(divmode[0]),
		.COLDRESETB(coldrst_l),
		.RESETB(warmrst_l),
		.PLOCK(pllc_lock),		// cpu pll is locked;
		.SI7(1'b0),				// scan chain inputs;
		.SI6(1'b0),
		.SI5(1'b0),
		.SI4(1'b0),
		.SI3(1'b0),
		.SI2(1'b0),
		.SI1(1'b0),
		.SI0(1'b0),
		.SO7(),					// scan chain outputs;
		.SO6(),
		.SO5(),
		.SO4(),
		.SO3(),
		.SO2(),
		.SO1(),
		.SO0(),
		.BUNRI(1'b0),			// test mode;
		.TBI51(1'b0),			// test bus inputs;
		.TBI50(1'b0),
		.TBI49(1'b0),
		.TBI48(1'b0),
		.TBI47(1'b0),
		.TBI46(1'b0),
		.TBI45(1'b0),
		.TBI44(1'b0),
		.TBI43(1'b0),
		.TBI42(1'b0),
		.TBI41(1'b0),
		.TBI40(1'b0),
		.TBI39(1'b0),
		.TBI38(1'b0),
		.TBI37(1'b0),
		.TBI36(1'b0),
		.TBI35(1'b0),
		.TBI34(1'b0),
		.TBI33(1'b0),
		.TBI32(1'b0),
		.TBI31(1'b0),
		.TBI30(1'b0),
		.TBI29(1'b0),
		.TBI28(1'b0),
		.TBI27(1'b0),
		.TBI26(1'b0),
		.TBI25(1'b0),
		.TBI24(1'b0),
		.TBI23(1'b0),
		.TBI22(1'b0),
		.TBI21(1'b0),
		.TBI20(1'b0),
		.TBI19(1'b0),
		.TBI18(1'b0),
		.TBI17(1'b0),
		.TBI16(1'b0),
		.TBI15(1'b0),
		.TBI14(1'b0),
		.TBI13(1'b0),
		.TBI12(1'b0),
		.TBI11(1'b0),
		.TBI10(1'b0),
		.TBI9(1'b0),
		.TBI8(1'b0),
		.TBI7(1'b0),
		.TBI6(1'b0),
		.TBI5(1'b0),
		.TBI4(1'b0),
		.TBI3(1'b0),
		.TBI2(1'b0),
		.TBI1(1'b0),
		.TBI0(1'b0),
		.TBO39(),
		.TBO38(),
		.TBO37(),
		.TBO36(),
		.TBO35(),
		.TBO34(),
		.TBO33(),
		.TBO32(),
		.TBO31(),
		.TBO30(),
		.TBO29(),
		.TBO28(),
		.TBO27(),
		.TBO26(),
		.TBO25(),
		.TBO24(),
		.TBO23(),
		.TBO22(),
		.TBO21(),
		.TBO20(),
		.TBO19(),
		.TBO18(),
		.TBO17(),
		.TBO16(),
		.TBO15(),
		.TBO14(),
		.TBO13(),
		.TBO12(),
		.TBO11(),
		.TBO10(),
		.TBO9(),
		.TBO8(),
		.TBO7(),
		.TBO6(),
		.TBO5(),
		.TBO4(),
		.TBO3(),
		.TBO2(),
		.TBO1(),
		.TBO0(),
		.TEST(1'b0),			// test mode;
		.TEST1(1'b0),			// test mode;
		.TEST0(1'b0),			// test mode;
		.SCANSMC(1'b0),
		.SCANTMC(tmc),
		.BYPASSPLLMODE(pll_bypass),
		.BYPASSPLLPCLK(sysclk),
		.BYPASSPLLSCLK(sysclk),
		.AVDD1(pllc_avdd1),
		.AGND1(pllc_agnd1)
	);

	// instantiate bcp;

	wire v_recall;			// recall on hard reset;
	wire v_tread;			// read for test enable;
	wire v_time;			// virage time base, 1us;
	wire [2:0] v_me;		// virage enables;
	wire [2:0] v_we;		// virage write enables;
	wire [15:2] v0_addr;	// virage 0 address;
	wire [31:0] v0_in;		// virage 0 write data;
	wire [31:0] v0_out;		// virage 0 read data;
	wire [15:2] v1_addr;	// virage 1 address;
	wire [31:0] v1_in;		// virage 1 write data;
	wire [31:0] v1_out;		// virage 1 read data;
	wire [15:2] v2_addr;	// virage 2 address;
	wire [31:0] v2_in;		// virage 2 write data;
	wire [31:0] v2_out;		// virage 2 read data;
	wire [31:0] v2_nvout;	// virage 2 novea read data;

	wire dbg_rst;			// test controller reset overwrite;
	wire dbg_boot;			// boot from bram instead of brom;
	wire dbg_sena;			// debug serial enable;
	wire dbg_sclk;			// debug serial clock;
	wire dbg_swe;			// debug serial write enable;
	wire dbg_sre;			// debug serial read enable;
	wire dbg_si;			// debug serial data in;
	wire dbg_so;			// debug serial data out;

	bcp bcp (
		.sysclk(sysclk),
		.memclk(memclk),
		.rst_l(rst_l),
		.reset_l(reset_l),
		.avrst_l(avrst_l),
		.pll_lock(pll_lock),
		.pll_bypass(pll_bypass),
		.button(button),
		.divmode(divmode),
		.coldrst_l(coldrst_l),
		.warmrst_l(warmrst_l),
		.sysad_out(sysad_out),
		.sysad_in(sysad_in),
		.syscmd_out(syscmd_out),
		.syscmd_in(syscmd_in),
		.pvalid_l(pvalid_l),
		.eok_l(eok_l),
		.evalid_l(evalid_l),
		.int_l(int_l),
		.nmi_l(nmi_l),
		.v_recall(v_recall),
		.v_tread(v_tread),
		.v_time(v_time),
		.v_me(v_me),
		.v_we(v_we),
		.v0_addr(v0_addr),
		.v0_in(v0_in),
		.v0_out(v0_out),
		.v1_addr(v1_addr),
		.v1_in(v1_in),
		.v1_out(v1_out),
		.v2_addr(v2_addr),
		.v2_in(v2_in),
		.v2_out(v2_out),

		.vclock(vclock),
		.vdata(vdata),
		.vsync(vsync),
		.avctrl(avctrl),
		.aclock(aclock),
		.adata(adata),
		.aword(aword),
		.jchan_in(jchan_in),
		.jchan_ena(jchan_ena),
		.jchan_oe(jchan_oe),
		.lctrl_x(lctrl_x),
		.lctrl_y(lctrl_y),
		.io_rst(io_rst),
		.io_in(io_in),
		.io_ena(io_ena),
		.io_out(io_out),
		.io_oe(io_oe),
		.io_ale(io_ale),
		.io_cs(io_cs),
		.io_ior(io_ior),
		.io_iow(io_iow),
		.io_dmarq(io_dmarq),
		.io_dmack(io_dmack),
		.io_intr(io_intr),
		.fl_ce(fl_ce),
		.fl_ale(fl_ale),
		.fl_cle(fl_cle),
		.fl_re(fl_re),
		.fl_we(fl_we),
		.fl_wp(fl_wp),
		.fl_ryby(fl_ryby),
		.fl_md(fl_md),
		.gpio_oe(gpio_oe),
		.gpio_out(gpio_out),
		.gpio_in(rgpio_in),

		.mcke(mcke),
		.maddr(maddr),
		.mbank(mbank),
		.mdin(mdin),
		.mdin_ena(mdin_ena),
		.mdout(mdout),
		.mdout_ena(mdout_ena),
		.strobe_rev(strobe_rev),
		.mras(mras),
		.mcas(mcas),
		.mwe(mwe),
		.mdqm(mdqm),
		
		.usb_clk(usbclk),
		.usb_sel_sys(usb_sel_sys),
		.usb_dp(usb_dp),
		.usb_dm(usb_dm),
		.usb_dpo(usb_dpo),
		.usbxr_ose(usbxr_ose),
		.usbxr_y1(usbxr_y1),
		.usbxr_oen(usbxr_oen),
		.usbxr_ien(usbxr_ien),
		.usbxr_fl(usbxr_fl),
		.usb_dp_high(usb_dp_high),
		.usb_d_low_n(usb_d_low_n),
		.usb_id(usb_id),
		.usb_vbus_vld(usb_vbus_vld),
		.usb_vbus_on_n(usb_vbus_on_n),

		.dbg_rst(dbg_rst),
		.dbg_boot(dbg_boot),
		.dbg_sena(dbg_sena),
		.dbg_sclk(dbg_sclk),
		.dbg_swe(dbg_swe),
		.dbg_sre(dbg_sre),
		.dbg_si(dbg_si),
		.dbg_so(dbg_so)
	);

	// virage test mode interface;
	// only v2 uses serial interface;

	wire v_sclk;			// virage serial clock;
	wire v_sme;				// virage serial mode;
	wire v_si;				// virage serial input data;
	wire v_so;				// virage serial output data;
	wire [2:0] v_porst;		// charge-pump power-on resets;
	wire [2:0] v_vpp;		// programming voltage test pads; XXX add pads

	assign porst = |v_porst;

	// instantiate virage 0 wrapper;
	// contains store controller, charge pump and novea block;

	v16x32wrap v0 (
		.sysclk(sysclk),
		.reset_l(reset_l),
		.v_time(v_time),
		.v_me(v_me[0]),
		.v_addr(v0_addr),
		.v_in(v0_in),
		.v_we(v_we[0]),
		.v_out(v0_out),
		.v_sclk(1'b0),
		.v_sme(1'b0),
		.v_si(1'b0),
		.v_so(),
		.v_porst(v_porst[0]),
		.v_vpp(v_vpp[0])
	);

	// instantiate virage 1 wrapper;
	// contains store controller, charge pump and novea block;

	v16x32wrap v1 (
		.sysclk(sysclk),
		.reset_l(reset_l),
		.v_time(v_time),
		.v_me(v_me[1]),
		.v_addr(v1_addr),
		.v_in(v1_in),
		.v_we(v_we[1]),
		.v_out(v1_out),
		.v_sclk(1'b0),
		.v_sme(1'b0),
		.v_si(1'b0),
		.v_so(),
		.v_porst(v_porst[1]),
		.v_vpp(v_vpp[1])
	);

	// instantiate virage 2 wrapper;
	// contains store controller, charge pump and novea block;

	v64x32wrap v2 (
		.sysclk(sysclk),
		.reset_l(reset_l),
		.v_recall(v_recall),
		.v_tread(v_tread),
		.v_time(v_time),
		.v_me(v_me[2]),
		.v_addr(v2_addr),
		.v_in(v2_in),
		.v_we(v_we[2]),
		.v_out(v2_out),
		.v_nvout(v2_nvout),
		.v_sclk(v_sclk),
		.v_sme(v_sme),
		.v_si(v_si),
		.v_so(v_so),
		.v_porst(v_porst[2]),
		.v_vpp(v_vpp[2])
	);

	// instantiate test enable logic;

	vtestena vtestena (
		.sysclk(sysclk),
		.coldrst_l(coldrst_l),
		.v_tread(v_tread),
		.v_nvout(v2_nvout),
		.porst(porst),
		.ena(jtag_ena)
	);

	// instantiate video encoder;
	// triple video dac is instantiated in pad layer;

	A5C382CORE venc (
		.PTCLK(vclock),
		.SCAN_A5C(tmc),
		.TRESET_IN(1'b1),
		.PSRGB0(vdata[0]),
		.PSRGB1(vdata[1]),
		.PSRGB2(vdata[2]),
		.PSRGB3(vdata[3]),
		.PSRGB4(vdata[4]),
		.PSRGB5(vdata[5]),
		.PSRGB6(vdata[6]),
		.PTSYNCB(vsync),
		.PNTPL(vntpl),
		.PMPAL_I(vmpal),
		.PTESTI0(venc_test),
		.PTRAPB_I(vtrap),
		.PCSYNCB(),
		.CLK24DAC(vdac_clk),
		.COUT0(vda[0]),
		.COUT1(vda[1]),
		.COUT2(vda[2]),
		.COUT3(vda[3]),
		.COUT4(vda[4]),
		.COUT5(vda[5]),
		.COUT6(vda[6]),
		.COUT7(vda[7]),
		.VOUT0(vdb[0]),
		.VOUT1(vdb[1]),
		.VOUT2(vdb[2]),
		.VOUT3(vdb[3]),
		.VOUT4(vdb[4]),
		.VOUT5(vdb[5]),
		.VOUT6(vdb[6]),
		.VOUT7(vdb[7]),
		.YOUT0(vdc[0]),
		.YOUT1(vdc[1]),
		.YOUT2(vdc[2]),
		.YOUT3(vdc[3]),
		.YOUT4(vdc[4]),
		.YOUT5(vdc[5]),
		.YOUT6(vdc[6]),
		.YOUT7(vdc[7]),
		.PMPAL_O(),
		.PTRAPB_O()
	);

	// instantiate test/jtag controller;

	wire dbg_sclk_in;		// dbg_sclk from tap controller;
	wire dbg_sclk_tmc;		// dbg_sclk after TMC mux;
	wire tck_buf;			// buffered tck into broadon tap controller;

	TBBUFCKX32 tck_tree ( .H01(tck), .N01(tck_buf) );

	tap_blk tap_blk (
		.trst_i(trst),
		.tdi_i(tdi),
		.tms_i(tms),
		.tck_i(tck_buf),
		.treset(dbg_rst),
		.tbaddr(dbg_boot),
		.spath_en(dbg_sena),
		.clksram(dbg_sclk_in),
		.stdi(dbg_si),
		.stdo(dbg_so),
		.tsram_we(dbg_swe),
		.tsram_rd(dbg_sre),
		.clkflash(v_sclk),
		.rpath_en(v_sme),
		.ftdi(v_si),
		.ftdo(v_so),		
		.trom_recall(),
		.tdoen_o(tdoen),
		.tdo_o(tdo),
		.tpllbypass(pll_bypass)
	);

	// debug port clocking;
	// from tap controller for operation;
	// from sysclk input pin for test;

	assign dbg_sclk_tmc = tmc? sysclk_in : dbg_sclk_in;

	TBBUFCKX32 dbgclk_tree ( .H01(dbg_sclk_tmc), .N01(dbg_sclk) );

endmodule