sysclk.tcl
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#################################
# SYSCLK (100MHz) #
#################################
# Get delay from PAD_SYSCLK to *reg*/H02 ---------------------------
set sysclk_latency_max 100000
foreach_in_collection cur_path \
[ get_timing_paths -nworst 10000 -max_paths 10000 \
-from [get_ports PAD_SYSCLK] \
-to [get_pins *reg*/H02] \
-delay max_rise \
] {
set cur_delay [ get_attribute $cur_path arrival ]
set cur_end [ get_attribute $cur_path endpoint ]
set cur_name [ get_attribute $cur_end full_name ]
echo [ format "%s : %s" $cur_name $cur_delay ]
if {$cur_delay < $sysclk_latency_max} { set sysclk_latency_max $cur_delay }
}
echo [ format "sysclk_latency_max : %s" $sysclk_latency_max ]
# Create SYSCLK ----------------------------------------------------
create_clock \
-name SYSCLK \
-period 9.8 \
-waveform [ list [expr 0.0 + $sysclk_latency_max] [expr 4.9 + $sysclk_latency_max] ] \
[ get_ports PAD_SYSCLK ]
set_propagated_clock \
[ get_clocks SYSCLK ]
#/*
# * PAD_RST_L into all clock domains;
# * used as both synchronous and asynchronous reset;
# */
set_input_delay 1.0 -clock SYSCLK -max [list PAD_RST_L]
###set_input_delay 0.5 -clock SYSCLK -min [list PAD_RST_L]
#/*
# * delays of misc input-only ports;
# * asynchronous input, sampled with SYSCLK;
# */
set_input_delay 1.0 -clock SYSCLK -max [list PAD_BUTTON]
###set_input_delay 0.5 -clock SYSCLK -min [list PAD_BUTTON]
#/*
# * joy-channel ports;
# * bi-directional, asynchronous, sampled/driven by SYSCLK;
# * set output delay to 50% of cycle time to force flops close to pads;
# */
set_input_delay 1.0 -clock SYSCLK -max [get_ports PAD_JCHAN*]
set_output_delay 5 -clock SYSCLK -max [get_ports PAD_JCHAN*]
###set_input_delay 0.5 -clock SYSCLK -min [get_ports PAD_JCHAN*]
###set_output_delay 0.5 -clock SYSCLK -min [get_ports PAD_JCHAN*]
#/*
# * local controller x/y sticks ports;
# * input only, asynchronous, sampled by SYSCLK;
# */
set_input_delay 1.0 -clock SYSCLK -max [list PAD_LX0 PAD_LX1 PAD_LY0 PAD_LY1]
###set_input_delay 0.5 -clock SYSCLK -min [list PAD_LX0 PAD_LX1 PAD_LY0 PAD_LY1]
#/*
# * io bus;
# * inputs sampled by SYSCLK, outputs driven from SYSCLK;
# * set io delays to 50% of cycle time to force flops close to pads;
# */
set_input_delay 5 -clock SYSCLK -max [get_ports PAD_IO_AD*]
set_input_delay 5 -clock SYSCLK -max [list PAD_IO_DMARQ PAD_IO_INTR]
###set_input_delay 0.5 -clock SYSCLK -min [get_ports PAD_IO_AD*]
###set_input_delay 0.5 -clock SYSCLK -min [list PAD_IO_DMARQ PAD_IO_INTR]
set_output_delay 5 -clock SYSCLK -max [list PAD_IO_RST PAD_IO_ALE]
set_output_delay 5 -clock SYSCLK -max [list PAD_IO_IOR PAD_IO_IOW]
set_output_delay 5 -clock SYSCLK -max [get_ports PAD_IO_AD*]
set_output_delay 5 -clock SYSCLK -max [get_ports PAD_IO_CS*]
###set_output_delay 0.5 -clock SYSCLK -min [list PAD_IO_RST PAD_IO_ALE]
###set_output_delay 0.5 -clock SYSCLK -min [list PAD_IO_IOR PAD_IO_IOW]
###set_output_delay 0.5 -clock SYSCLK -min [get_ports PAD_IO_AD*]
###set_output_delay 0.5 -clock SYSCLK -min [get_ports PAD_IO_CS*]
#/*
# * flash bus, data move on PAD_IO_AD;
# * set io delays to 50% of cycle time to force flops close to pads;
# */
set_input_delay 1.0 -clock SYSCLK -max [list PAD_FL_RYBY PAD_FL_MD]
set_output_delay 5 -clock SYSCLK -max [get_ports PAD_FL_CE*]
set_output_delay 5 -clock SYSCLK -max [list PAD_FL_ALE PAD_FL_CLE]
set_output_delay 5 -clock SYSCLK -max [list PAD_FL_RE PAD_FL_WE PAD_FL_WP]
###set_input_delay 0.5 -clock SYSCLK -min [list PAD_FL_RYBY PAD_FL_MD]
###set_output_delay 0.5 -clock SYSCLK -min [get_ports PAD_FL_CE*]
###set_output_delay 0.5 -clock SYSCLK -min [list PAD_FL_ALE PAD_FL_CLE]
###set_output_delay 0.5 -clock SYSCLK -min [list PAD_FL_RE PAD_FL_WE PAD_FL_WP]
#/*
# * gpio bus;
# * bidirectional, sampled and driven by SYSCLK;
# */
set_input_delay 1.0 -clock SYSCLK -max [get_ports PAD_GPIO*]
set_output_delay 5 -clock SYSCLK -max [get_ports PAD_GPIO*]
###set_input_delay 0.5 -clock SYSCLK -min [get_ports PAD_GPIO*]
###set_output_delay 0.5 -clock SYSCLK -min [get_ports PAD_GPIO*]
#/*
# * usb pull drivers;
# */
set_output_delay 3 -clock SYSCLK -max [list PAD_USB_DP_HIGH0 PAD_USB_D_LOW_N0 PAD_USB_VBUS_ON0]
set_output_delay 3 -clock SYSCLK -max [list PAD_USB_DP_HIGH1 PAD_USB_D_LOW_N1 PAD_USB_VBUS_ON1]
set_input_delay 1.0 -clock SYSCLK -max [list PAD_USB_VBUS_VLD0 PAD_USB_ID0]
set_input_delay 1.0 -clock SYSCLK -max [list PAD_USB_VBUS_VLD1 PAD_USB_ID1]