vsram
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#!/bin/sh -x
if [ "$ROOT" = "" ]; then
echo "Please specified the ROOT "
exit
fi
usage()
{
echo "Usage: dc [-g]"
echo " Generate DC test vectors"
echo " -g use gate_level simulate instead"
exit
}
GATE=0
while getopts "g?" a
do
case $a in
g) GATE=1;;
*) usage;;
esac
done
cd ${ROOT}/PR/hw2/chip/vsim
rm -f verilog.dump
rm -f dump.v
cp -f dump.v.padio dump.v
make clean
export SIMDEFS="+nospecify +define+TEST_VECTORS +define+FLASH_BIG"
if [ "$GATE" = "1" ]; then
export SIMGATE=1
else
export SIMGATE=""
fi
make sim.ipc
./sim.ipc +sysclk=200000 +usbclk=200000 +vclk=200000 +delay_mode_zero +cbus_mon +cpu_mon +non_clk_mon&
cd ${ROOT}/PR/iosim/src/jtag_test
export CPU_AT_5MHZ=1
export JTAG_CLK_FAST=1
make clean
rm -f test_vector
make test_vector
./test_vector -t v -q