#
# This makefile has rules for making both the executables
# which make up the simulator, and for running test cases.
#

BBDEPTH = ../../..

include $(BBDEPTH)/BBdefs

# Directory to store verilog output files (sim and c files).
# User can overide this variable on make command line, ie.
# 'make SIMDIR=/tmp' or environment variable.

SIMDIR ?= .

# simulator definitions;

SIMDEFS ?= 

# run-time dump flags;

SIMDUMP ?=

# gate level;

SIMFIX ?=
SIMGATE ?=
SIMSDF ?=

# paths to vendor library;

VLIB = lib/verilog
SLIB = lib/sdf

# C include directories;

LCINCS =  
GCINCS =

# C compiler options

OPTIMIZER = -g
LCOPTS = -fullwarn

# all vcs dirt;

VCSDIRT = $(VCS_NAME).log \
	$(SIMDIR)/c.* \
	$(SIMDIR)/sim.* \
	tokens.v

# path to bcp pli library;

LIBBCPPLI = $(BBDEPTH)/lib/libbcppli

# override global vcs flags:

GVCSOPTS = -l $(VCS_NAME).log \
	-M -Mupdate \
	+define+SIM \
	$(SIMDEFS) \
	-V

# build from rtl or gate level;
# BBV is all synthesizable code;

ifdef	SIMSDF
BBSDF = +define+SIMSDF
else
BBSDF = 
endif

ifdef	SIMFIX
BBGATE = fixes
BBFIX = +define+BBFIX
else
BBGATE = syn
BBFIX = 
endif

ifdef	SIMGATE
BBV = \
	-v $(BBDEPTH)/hw/chip/$(BBGATE)/bb.v \
	-v $(BBDEPTH)/hw/chip/bcp/rsp/src/rsp_dummy.v \
	-v $(BBDEPTH)/hw/chip/bcp/rdp/src/rdp_dummy.v \
	-v $(BBDEPTH)/hw/chip/bcp/ai/src/ai_dummy.v \
	-v $(BBDEPTH)/hw/chip/bcp/vi/src/vi_dummy.v \
	-y $(BBDEPTH)/hw/chip/$(SLIB)/nec.15/memories \
	-y $(BBDEPTH)/hw/chip/$(SLIB)/nec.15/special \
	+2state \
	+optconfigfile+twostate.cfg \
	+define+SIMGATE $(BBSDF) $(BBFIX)
else
BBV = \
	-y $(BBDEPTH)/hw/chip/bcp/src \
	-y $(BBDEPTH)/hw/chip/bcp/jtag/src \
	-y $(BBDEPTH)/hw/chip/bcp/rdp/src \
	-y $(BBDEPTH)/hw/chip/bcp/ri/src \
	-y $(BBDEPTH)/hw/chip/bcp/rsp/src \
	-y $(BBDEPTH)/hw/chip/bcp/ar/src \
	-y $(BBDEPTH)/hw/chip/bcp/mi/src \
	-y $(BBDEPTH)/hw/chip/bcp/vi/src \
	-y $(BBDEPTH)/hw/chip/bcp/ui/src \
	-y $(BBDEPTH)/hw/chip/bcp/ai/src \
	-y $(BBDEPTH)/hw/chip/bcp/pi/src \
	-y $(BBDEPTH)/hw/chip/bcp/si/src \
	-y $(BBDEPTH)/hw/chip/bcp/cs/src \
	-y $(BBDEPTH)/hw/chip/bcp/ew/src \
	-y $(BBDEPTH)/hw/chip/bcp/ep/src \
	-y $(BBDEPTH)/hw/chip/bcp/cv/src \
	-y $(BBDEPTH)/hw/chip/bcp/st/src \
	-y $(BBDEPTH)/hw/chip/bcp/tc/src \
	-y $(BBDEPTH)/hw/chip/bcp/tm/src \
	-y $(BBDEPTH)/hw/chip/bcp/tf/src \
	-y $(BBDEPTH)/hw/chip/bcp/cc/src \
	-y $(BBDEPTH)/hw/chip/bcp/bl/src \
	-y $(BBDEPTH)/hw/chip/bcp/at/src \
	-y $(BBDEPTH)/hw/chip/bcp/bl/src \
	-y $(BBDEPTH)/hw/chip/bcp/ms/src \
	-y $(BBDEPTH)/hw/chip/bcp/rsp/src \
	-y $(BBDEPTH)/hw/chip/bcp/su/src \
	-y $(BBDEPTH)/hw/chip/bcp/vu/src \
	-y $(BBDEPTH)/hw/chip/bcp/ls/src \
	-y $(BBDEPTH)/hw/chip/bcp/io/src \
	-y $(BBDEPTH)/hw/chip/bcp/sb/src \
	-v $(BBDEPTH)/hw/chip/$(VLIB)/ricoh_encoder/A5C382CORE.v \
	-v $(BBDEPTH)/hw/chip/$(VLIB)/virage/vtestena.v \
	-v $(BBDEPTH)/hw/chip/$(VLIB)/virage/v16x32wrap.v \
	-v $(BBDEPTH)/hw/chip/$(VLIB)/virage/v64x32wrap.v \
	-v $(BBDEPTH)/hw/chip/$(VLIB)/virage/NMS_16x32/nms_sc_16x32.v \
	-v $(BBDEPTH)/hw/chip/$(VLIB)/virage/NMS_16x32/nvco_nc15gfh_16x32.v \
	-v $(BBDEPTH)/hw/chip/$(VLIB)/virage/NMS_64x32/nms_sc_64x32.v \
	-v $(BBDEPTH)/hw/chip/$(VLIB)/virage/NMS_64x32/nvco_nc15gfh_64x32.v \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/jlib \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/usb_pad \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/nec.15/memories \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/nec.15/special \
	-y $(BBDEPTH)/hw/chip/lib/usb_arc/verilog \
	-y $(BBDEPTH)/hw/chip/lib/cast/aes_cbc_d/src \
	-y $(BBDEPTH)/hw/chip/src
endif

# vcs options for behavioral simulator;
# models only in below definition;

LVCSOPTS = $(BBV) \
	-y $(BBDEPTH)/hw/chip/vsim \
	-y $(BBDEPTH)/hw/chip/vsim/monitors \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/nec \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/nec.15/verilog_udp \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/nec.15/scan \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/nec.15/clockdriver \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/nec.15/gating \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/nec.15/iobuffer \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/nec.15/oscillator \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/nec.15/primitive \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/nec.15/nec_bscan \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/nec.15/testact \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/micron \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/cbus \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/dbus \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/ri \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/jchan \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/mjctrl \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/lctrl \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/flash \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/samsung/km29u64 \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/samsung/km29u128 \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/samsung/km29u256 \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/samsung/km29u512 \
	-y $(BBDEPTH)/hw/chip/$(VLIB)/toshiba/flash \
	-v $(BBDEPTH)/hw/chip/$(VLIB)/virage/nvcp_nc15gfh.v \
	-v $(BBDEPTH)/hw/chip/$(VLIB)/virage/NMS_16x32/nvrm_nc15gfh_16x32.v \
	-v $(BBDEPTH)/hw/chip/$(VLIB)/virage/NMS_64x32/nvrm_nc15gfh_64x32.v \
	-v $(BBDEPTH)/hw/chip/$(VLIB)/usb_pad/usb_arc_term.v \
	-v $(BBDEPTH)/hw/chip/$(VLIB)/usb_pad/usb_bb_term.v \
	-v $(BBDEPTH)/hw/chip/$(VLIB)/usb_pad/usb_hostio.v \
	-v $(BBDEPTH)/hw/chip/lib/usb_arc/verilog/vusb_host_ctl.v \
	-v $(BBDEPTH)/hw/chip/lib/usb_arc/verilog/vusb_otg_lpbck.v \
	+libext+.v+.vp+.VP+.vzd+.vmd \
	+incdir+$(BBDEPTH)/hw/chip/include \
	+incdir+$(BBDEPTH)/hw/chip/bcp/su/src \
	+incdir+$(BBDEPTH)/hw/chip/bcp/vu/src \
	+incdir+$(BBDEPTH)/hw/chip/bcp/ms/src \
	+incdir+$(BBDEPTH)/hw/chip/lib/usb_arc/verilog \
	+race=all \
	+vcs+lic+wait

# additional vcs options for ipc version;
# use pli interface;

IPCOPTS = +acc +librescan \
	+define+RSP_MON \
	+define+RSP_PRESENT \
	+define+MSPAN_MON

IPCCPUOPTS = +acc +librescan 

# additional vcs options for cpu version;

CPUOPTS =

# default target is to build the simulator for verilog tests;

TARGETS = sim.v 

default install: $(TARGETS)

# help

help: _always
	@echo "clean        - clean up all vcs temporaries"
	@echo "sim.v        - build verilog simulator"
	@echo "sim.v.vpd    - convert verilog.dump into vpd"
	@echo "sim.ipc      - build ipc simulator"
	@echo "sim.ipc.vpd  - convert verilog.dump into vpd"

# clean all vcs files;

clean-vcs: _always
	$(RM) -rf $(VCSDIRT)

# thorough clean;

clean: clean-vcs

# include BB common rules;

include $(BBDEPTH)/BBrules

# always dependency;

_always:

# compile the behavioral simulator;

sim.v: _always
	$(VCS) $(VCSOPTS) \
		-v $(BBDEPTH)/hw/chip/vsim/r4300uni.v \
		-Mdir=$(SIMDIR)/c.v \
		-P $(LIBBCPPLI)/bcppli.tab $(LIBBCPPLI)/libbcppli.a \
		-o $(SIMDIR)/$@  \
		vsim.v

sim.v.vpd: verilog.dump
	$(VCD2VPD) verilog.dump $@

# run various tests;

test_si: _always
	./sim.v +vcs+lic+wait \
		+seed=`date +%s` \
		+cpu_mon +cbus_mon +ri_mon +mem_mon +lctrl_mon +jctrl_mon \
		$(SIMDUMP) +dump_cpu +dump_si +dump_pi +dump_vsim \
		+test_si > si.log
	$(VCD2VPD) verilog.dump si.vpd

CLKOPTS=
ifdef TOSHIBA
    CLKOPTS = +sysclk=10400
endif

test_pi: _always
	./sim.v +vcs+lic+wait \
		+seed=`date +%s` \
		+cpu_mon +cbus_mon +ri_mon +mem_mon +fl_mon \
		$(SIMDUMP) $(CLKOPTS)\
		+test_pi > pi.log
	$(VCD2VPD) verilog.dump pi.vpd

test_mi: _always
	./sim.v +vcs+lic+wait \
		+seed=`date +%s` \
		+cpu_mon +cbus_mon +ri_mon +mem_mon \
		$(SIMDUMP) +dump_mi +dump_vsim \
		+test_mi > mi.log
	$(VCD2VPD) verilog.dump mi.vpd

test_mem_rand: _always
	./sim.v +vcs+lic+wait \
		+seed=`date +%s` \
		+cpu_mon +cbus_mon +ri_mon +mem_mon \
		$(SIMDUMP) +dump_cpu +dump_mi +dump_vsim +dump_ri \
		+test_mem_rand > mi.log
	$(VCD2VPD) verilog.dump mi.vpd

test_sp: _always
	./sim.v +vcs+lic+wait \
		+seed=`date +%s` \
		+cpu_mon +cbus_mon +ri_mon +mem_mon \
		$(SIMDUMP) +dump_cpu +dump_mi +dump_vsim +dump_rsp \
		+test_sp > sp.log
	$(VCD2VPD) verilog.dump sp.vpd

test_vi: _always
	./sim.v +vcs+lic+wait \
		+seed=`date +%s` \
		+cpu_mon +cbus_mon +ri_mon +mem_mon \
		$(SIMDUMP) +dump_cpu +dump_mi +dump_vsim +dump_vi \
		+test_vi > vi.log
	$(VCD2VPD) verilog.dump vi.vpd

# compile ipc simulator;

sim.ipc: _always
	$(VCS) $(VCSOPTS) $(IPCOPTS) \
		-v $(BBDEPTH)/hw/chip/vsim/r4300uni.v \
		-Mdir=$(SIMDIR)/c.ipc \
		+define+IPC \
		-P $(LIBBCPPLI)/bcppli.tab $(LIBBCPPLI)/libbcppli.a \
		-o $(SIMDIR)/$@ \
		vsim.v

sim.ipc.vpd: verilog.dump
	$(VCD2VPD) verilog.dump $@

# compile cpu simulator;

sim.cpu: _always
	$(VCS) $(VCSOPTS) $(CPUOPTS) \
		-y $(BBDEPTH)/hw/chip/$(VLIB)/r4300 \
		-Mdir=$(SIMDIR)/c.cpu \
		+define+SIMCPU \
		-P $(LIBBCPPLI)/bcppli.tab $(LIBBCPPLI)/libbcppli.a \
		-o $(SIMDIR)/$@ \
		vsim.v

sim.cpu.ipc: _always
	$(VCS) $(VCSOPTS) $(IPCCPUOPTS) \
		-y $(BBDEPTH)/hw/chip/$(VLIB)/r4300 \
		-Mdir=$(SIMDIR)/c.cpu \
		+define+SIMCPU \
		+define+IPC \
		-P $(LIBBCPPLI)/bcppli.tab $(LIBBCPPLI)/libbcppli.a \
		-o $(SIMDIR)/$@ \
		vsim.v

sim.cpu.vpd: verilog.dump
	$(VCD2VPD) verilog.dump $@

# run cpu test;

test_cpu: _always
	./sim.cpu +vcs+lic+wait \
		+seed=`date +%s` \
		+cpu_mon +cbus_mon +ri_mon +mem_mon \
		$(SIMDUMP) \
		> cpu.log

# grep out known race problems;

grep_race: _always
	grep -v '^0 ' race.out \
		| grep -v nec.15 \
		| grep -v lib.verilog.micron \
		| grep -v lib.verilog.virage.NMS_16x32 \
		| grep -v lib.verilog.virage.NMS_64x32 \
		| grep -v lib.verilog.virage.nvcp_nc15gfh.v \
		| grep -v nvco_nc15gfh_16x32.v \
		| grep -v nvco_nc15gfh_64x32.v \
		| grep -v lib.verilog.samsung \
		| grep -v lib.usb_arc.verilog \