// clkgen.v v1 Frank Berndt
// simulation clock generator;
// :set tabstop=4

`timescale 1ps/1ps

module clkgen ( period, clk, xclk );
	input [31:0] period;
	output clk;
	output xclk;

	// programmable clock generator;

	reg running;
	reg clk;
	reg xclk;

	initial
	begin
		running = 'bx;
		clk = 'bx;
		xclk = 'bx;
		#32000;
		running = 1;
		clk = 0;
		xclk = 0;
	end

	always
		#(period / 4) xclk = running & ~xclk;
	always @(posedge xclk)
		clk <= running & ~clk;

	always @(period)
		$display("%t: %M: period %0dps", $time, period);

endmodule