//**************************************************************************************
//
//	Model Name	: debug_prt.v
//	Revision	: $Revision: 1.8 $
//	Date		: $Date: 2003/04/23 20:55:07 $
//	Author		: Bill Saperstein
//	Description	: I/O bus to 1284 interface model
//
//**************************************************************************************


//**************************************************************************************
// Module Definition
//**************************************************************************************
module debug_prt
		(
	// Inputs
		cs_i ,		// interface chip select
		ale_i ,		// io bus ale strobe
		ior_i ,		// io bus read strobe
		iow_i ,		// io bus write strobe
		iorst_i ,	// io bus reset
	// Outputs
		ioirq_o ,	// interface interrupt
	// Bi-directionals
		ad_io		// io bus ad bus
		) ;

//**************************************************************************************
// Define Parameters (optional)
//**************************************************************************************

parameter	CMD_REG_ADDR		=	8'h00 ;
parameter	DATA_REG_LO_ADDR	=	8'h01 ;
parameter	DATA_REG_HI_ADDR	=	8'h02 ;
parameter	IRQ_REG_ADDR		=	8'h03 ;
parameter	sd			= 	0 ;


//**************************************************************************************
// Port Declarations
//**************************************************************************************
	input
		cs_i, ale_i, ior_i, iow_i, iorst_i ;
	output
		ioirq_o ;
	inout[15:0]
		ad_io ;
		
//**************************************************************************************
// Net Assignments and Declarations
//**************************************************************************************

	wire
	   data_tl_addr, data_th_addr, cmd_t_addr, irq_t_addr ,
	   cmd_t_en ;

//**************************************************************************************
// Pre-Defined Module Instantiations
//**************************************************************************************

// Not Applicable

//**************************************************************************************
// Gate and Structural Declarations
//**************************************************************************************

// *** Define the data_h register
//	32-bit register writable from the 1284 interface and readable from bb

	reg[31:0]	data_h_reg ;
	always @(negedge iorst_i)
	   data_h_reg <= 32'h00000000 ;

// *** Define the interface address register
//	16-bit register that is loadable via the ale strobe

	reg[15:0]	addr_reg ;
	always @(negedge (ale_i & ~cs_i))
	   begin
		addr_reg <= #sd ad_io ;
	   end

// *** Define the command_h register
//	8-bit register writable from the 1284 interface which controls setting
//	interrupt to the bb

	reg[7:0] 	cmd_h_reg ;
	always @(negedge iorst_i)
	   cmd_h_reg <= 8'h00 ;
	always @(posedge cmd_t_en)
	   if (ad_io[7])
	      cmd_h_reg[0] <= 1'b0 ;

// *** Define the data_t register
//	32-bit register writable from the bb and readable from the 1284 interface

	reg[31:0]	data_t_reg ;
	wire data_t_low_en, data_t_hi_en ;
	assign
		data_t_low_en = ~cs_i & ~iow_i & data_tl_addr ,
		data_t_hi_en = ~cs_i & ~iow_i & data_th_addr ;
	always @(negedge data_t_low_en)
	   begin
		data_t_reg[15:0] <= #sd ad_io ;
	   end
	always @(negedge data_t_hi_en)
	   begin
		data_t_reg[31:16] <= #sd ad_io ;
	   end

// *** Define the command_t register
//	8-bit register writable from the bb and readable from the bb that
//	controls the I/O interface of the debug port and sets interrupt to
//	1284 interface

	reg[7:0]	cmd_t_reg ;
	assign
		cmd_t_en = ~cs_i & ~iow_i & cmd_t_addr ;
	always @(negedge(cmd_t_en) or negedge(iorst_i))
	   begin
		if (!iorst_i) 
		   cmd_t_reg <= 8'h00 ;
	   	else
		   cmd_t_reg <= #sd {4'b0,ad_io[2:0]} ;
           end

	always @(posedge cmd_h_reg[7])
	   begin
		cmd_t_reg[0] <= 1'b0 ;
		cmd_h_reg[7] <= 1'b0 ;
	   end

// *** Define interrupt register that allows setting ioirq from bb interface
	reg[7:0]	irq_t_reg ;
	wire irq_t_en ;
	assign
		irq_t_en = ~cs_i & ~iow_i & irq_t_addr ;
	always @(negedge(irq_t_en) or negedge(iorst_i))
	   begin
		if (!iorst_i)
		   irq_t_reg <= 8'h00 ;
		else
		   irq_t_reg <= #sd ad_io[7:0] ;
	   end

// *** Define the address decode of the addr_reg
	assign 
	   cmd_t_addr = (addr_reg == CMD_REG_ADDR) ,
	   irq_t_addr = (addr_reg == IRQ_REG_ADDR) ,
	   data_tl_addr = (addr_reg == DATA_REG_LO_ADDR) ,
	   data_th_addr = (addr_reg == DATA_REG_HI_ADDR) ; 

// *** Define the bit decodes of the cmd_h_reg and cmd_t_reg

	assign
	   ioirq_o = (cmd_h_reg[2] ^ cmd_h_reg[0]) | (irq_t_reg[2] ^ irq_t_reg[0])  ;

// *** Define the tri-state driver and mux for the ad_io bus
	wire ad_en ;
	assign
	   ad_en = ~cs_i & ~ior_i , 
	   ad_io = ad_en ? ((addr_reg == CMD_REG_ADDR) ? {8'h00,cmd_h_reg} : 
			((addr_reg == DATA_REG_LO_ADDR) ? data_h_reg[15:0] : 
			((addr_reg == IRQ_REG_ADDR) ? irq_t_reg[7:0] : 
			data_h_reg[31:16]))) : 16'hz ;


//**************************************************************************************
// Procedural Assignments
//**************************************************************************************

// Not applicable

//**************************************************************************************
// Task and Function Definitions
//**************************************************************************************

// Not applicable

//**************************************************************************************
// End of Model
//**************************************************************************************
endmodule // debug_prt