// ipc.v v1 Frank Berndt
// frame for ipc test interface;
// :set tabstop=4

`timescale 1ns/1ps

module ipc(sysclk, coldrst_l, warmrst_l);
input sysclk;
input coldrst_l;
input warmrst_l;

`include "ipc.vh"
`include "tests/bb_usb_tests.v"

	// monitor ipc actions;

	reg ipc_mon, ipc_msg;
    integer live_socket;           // Keep alive socket. (BCP enhanced)
    integer i;
	reg ready;
	reg check_9th_bit;
	wire reset_l;

	assign reset_l = coldrst_l & warmrst_l;

	initial
	begin
		$display("%M: r4300 ipc simulator");
		ipc_mon = $test$plusargs("ipc_mon");
		live_socket = -1;          // default (not persist connection)  
        ipc_msg = 1;
		check_9th_bit = 0;
	end

	// Handle reset
	always @(posedge sysclk)
	begin
		if((reset_l === 0) | (reset_l === 1))
			ready = reset_l;
	end

	// ipc environment;

	reg [1:16*8] ipc_name;			// ipc name, not used;
	integer ipc_fd, new_fd;			// socket file descriptors;
	integer ret;					// pli return code;

	reg [31:0] req_code;			// request code;
	reg [31:0] req_size;			// request size;
	reg [31:0] req_address;			// request address;

    // For BCP, all request data and responds data can 
    // contain x/z values. 
    // As for PLI, 
    //   data_part    0    1   0   1
    //   xz_part      0    0   1   1
    //   data         0    1   z   x
 
	reg [31:0] req_data0, rsp_data0;         
	reg [31:0] req_data1, rsp_data1;
	reg [31:0] req_data2, rsp_data2;
	reg [31:0] req_data3, rsp_data3;
	reg [31:0] req_data4, rsp_data4;
	reg [31:0] req_data5, rsp_data5;
	reg [31:0] req_data6, rsp_data6;
	reg [31:0] req_data7, rsp_data7;   
	reg bit256;                      // rsp ctrace
	
    // BCP  extension 
    // BCP  request code extension
    // bit 31: zero time operation
    // bit 30: soft turn off ipc_mon
    // bit 29: need xz value combination (PLI only)
    // bit 28: need xz value split(pass to responds)
    // bit 27-24: # combined words
    // bit 23-20: # split words 
	// bit 15 :   nmi 
	// bit 14-10 : interrupt
	// bit 9 : debug interrupt

    reg [4:0] split_info;                // Ask for split or not
    reg [68*8:1] disp_msg;               // Add for msg 

	// ipc startup;

	initial
	begin
		ready = 0;
		ipc_name = "NULL";
		ret = $ipc_init(ipc_name);
		ipc_fd = $ipc_open(`IPC_SERVER);
		if(ipc_fd < 0) begin
			$display("ERROR: %t: %M: ipc_open", $time);
			$finish;
		end
	end

	// Add vi snoop tasks
	task disable_vi_snoop;
        begin
            vsim.vbus_mon.vi_snoop=0;
        end
    endtask

    task enable_vi_snoop;
        begin
            if($open_viout_file() == -1) begin
                $write("ERROR: %t: %M: cannot open vi output file", $time);
            end
            vsim.vbus_mon.vi_snoop = 1;
        end
    endtask
	
	// include various ip tasks;

`ifdef SIMCPU
`else
`ifdef	RSP_DUMMY
`else	// RSP_DUMMY
`ifdef SIMGATE
`else
`include "tasks/rspctrace_tasks.v"
`endif
`endif	// RSP_DUMMY
`endif

`include "tasks/si_bd.v"

	// send ipc reply;

	task ipc_reply;
		input [31:0] code;		// reply code;
        reg   [31:0] rsp_code;
		integer i;
		begin
			rsp_code = code;
            rsp_code[28] = split_info[4];
            rsp_code[23:20] = split_info[3:0];
			rsp_code[15] = ~vsim.bb.nmi_l;
`ifdef SIMGATE
			rsp_code[14:10] = ~vsim.bb_int_l;
`else
			rsp_code[14:10] = ~vsim.bb.int_l;
`endif
			rsp_code[9] = vsim.dbug.cmd_h_reg[0] ;

			if(ipc_mon & ipc_msg) begin
				$display("%t: %M: code=%0d, size=%0d, addr=%h",
						$time, req_code, req_size, req_address);
`ifdef SIMCPU
                 $display("%t: %M: ipc reply code=%b, rsp_data0=%b",
                          $time, rsp_code, rsp_data0);
`else
                 $display("%t: %M: ipc reply code=%b, data[0]=%b",
                          $time, rsp_code, vsim.bb.cpu.data[0]);
`endif
			end
             
			ret = $ipc_send(new_fd,
				rsp_code, req_size, req_address,
				rsp_data0, rsp_data1, rsp_data2, rsp_data3,
				rsp_data4, rsp_data5, rsp_data6, rsp_data7);

			if(ret < 0)
				$display("ERROR: %t: %M: ipc send", $time);
		end
	endtask

	// ipc execution;
	// bind the bus model through socket to cosim;
	// XXX keep socket open for performance;

	always @(posedge sysclk)
	begin : ipc_top
		reg ztime;
		reg [63:0] bcp_time;

		// stall until cpu is ready;
`ifdef SIMCPU
`else
		wait(ready);
`endif
		ztime = 1;
        ipc_msg = 1;
 
		while(ztime) begin

			// block on accept;
			// read and execute request;
        	if (live_socket < 0) begin
				if (ipc_mon & ipc_msg) $display("%t: %M: open new socket", $time);
 				new_fd = $ipc_accept(ipc_fd);
        	end else begin 
				if (ipc_mon & ipc_msg) $display("%t: %M: use old socket %d", $time, live_socket);
            	new_fd = live_socket;
        	end

			if(new_fd < 0)
				$display("ERROR: %t: %M: ipc_accept", $time);
			else begin
				ret = $ipc_receive(new_fd,
					req_code, req_size, req_address,
					req_data0, req_data1, req_data2, req_data3,
					req_data4, req_data5, req_data6, req_data7, disp_msg);

				if(ret < 0)
					$display("ERROR: %t: %M: ipc_receive", $time);
				else begin : ipc_exe
					
					if(ipc_mon & ipc_msg) begin
						$display("%t: %M: ipc: code=%0d, size=%0d, addr=%h recv data[0]=%b",
							$time, req_code, req_size, req_address, req_data0);
					end

					ztime = req_code[31];           // Bits 31 zero time io
                    ipc_msg = ~req_code[30];        // Turn off ipc message
					split_info[4] = req_code[28];
					split_info[3:0] = req_code[23:20];
		
					case(req_code & 0'h800FFFFF)
`ifdef SIMCPU
`else
						`BCP_9TH_BITS: begin
								$display("%t: %M: Before: 9th bit check is %s", 
										 $time, check_9th_bit?"on":"off");
								check_9th_bit = req_data0[0];
								$display("%t: %M: After: 9th bit check is %s", 
										 $time, check_9th_bit?"on":"off");
								ipc_reply(`RSP_OK);
							end
						`REQ_SINGLE_READ: begin
								if (check_9th_bit) mem_check9(req_address, 1);
								vsim.bb.cpu.sread(req_address, req_size, vsim.bb.cpu.data[0]);
								rsp_data0 = vsim.bb.cpu.data[0];
								ipc_reply(`RSP_DATA);
							end
						`REQ_BLOCK_READ: begin
								if (check_9th_bit)
									 mem_check9(req_address, 1<<(req_size+1));
								vsim.bb.cpu.bread(req_address, req_size);
                                rsp_data0 = vsim.bb.cpu.data[0];
                                rsp_data1 = vsim.bb.cpu.data[1];
                                rsp_data2 = vsim.bb.cpu.data[2];
                                rsp_data3 = vsim.bb.cpu.data[3];
                                rsp_data4 = vsim.bb.cpu.data[4];
                                rsp_data5 = vsim.bb.cpu.data[5];
                                rsp_data6 = vsim.bb.cpu.data[6];
                                rsp_data7 = vsim.bb.cpu.data[7];
								ipc_reply(`RSP_DATA);
							end
						`REQ_SINGLE_WRITE: begin
								vsim.bb.cpu.swrite(req_address, req_size, req_data0);
								ipc_reply(`RSP_OK);
							end
						`REQ_BLOCK_WRITE: begin
								vsim.bb.cpu.data[0] = req_data0;
								vsim.bb.cpu.data[1] = req_data1;
								vsim.bb.cpu.data[2] = req_data2;
								vsim.bb.cpu.data[3] = req_data3;
								vsim.bb.cpu.data[4] = req_data4;
								vsim.bb.cpu.data[5] = req_data5;
								vsim.bb.cpu.data[6] = req_data6;
								vsim.bb.cpu.data[7] = req_data7;
								vsim.bb.cpu.bwrite(req_address, req_size);
								ipc_reply(`RSP_OK);
							end
`endif
						`REQ_STALL: begin
								repeat(req_data0) @(posedge sysclk);
								ipc_reply(`RSP_OK);
							end
						`BCP_SIM_TIME : begin 
								bcp_time = $time;
								rsp_data0 = bcp_time[63:32];
								rsp_data1 = bcp_time[31:0];
								ipc_reply(`RSP_OK);
							end
						`BCP_SYSCLK_PERIOD : begin 
								rsp_data0 = vsim.sysclk_period;
								ipc_reply(`RSP_DATA);
							end
						`BCP_VCLK_PERIOD : begin 
								rsp_data0 = vsim.vclk_period;
								ipc_reply(`RSP_DATA);
							end
						`BCP_SIM_MEM_INFO: begin
								rsp_data0[7:0] = vsim.MEM_NADDR;
`ifdef DDR32M16		
								rsp_data0[15:8] = 16;
`else
								rsp_data0[15:8] = 32;
`endif
								ipc_reply(`RSP_DATA);
							end
						`REQ_LOG: begin
								ipc_reply(`RSP_OK);
							end
						`REQ_QUIT: begin
								ipc_reply(`RSP_OK);
`ifdef	MSPAN_MON
								// XXX vsim.mspan_mon_0.ms_state_results;
`endif	// MSPAN_MON
								$finish;
							end

						//Add DDR backdoor support
						`BD_REQ_SINGLE_READ: begin
								if (check_9th_bit) mem_check9(req_address, 1);
								mem_sread(req_address, req_size, rsp_data0);
								ipc_reply(`RSP_DATA);
							end 

						`BD_REQ_BLOCK_READ: begin
								if (check_9th_bit) 
									mem_check9(req_address, 1<<(1+req_size));
								mem_bread(req_address, req_size, rsp_data0,
										rsp_data1, rsp_data2, rsp_data3,
										rsp_data4, rsp_data5, rsp_data6, rsp_data7);
								ipc_reply(`RSP_DATA);
							end

						`BD_REQ_SINGLE_WRITE: begin
								mem_swrite(req_address, req_size, req_data0);
								ipc_reply(`RSP_OK);
							end

						`BD_REQ_BLOCK_WRITE: begin
                                mem_bwrite(req_address, req_size, req_data0,
									req_data1, req_data2, req_data3,
									req_data4, req_data5, req_data6, req_data7);
                                ipc_reply(`RSP_OK);
                            end 

						`BD_REQ_DISPLAY_MSG: begin
								$display("%t ## %s", $time, disp_msg);
								ipc_reply(`RSP_OK);
							end

						`BD_REQ_SINGLE_SEARCH: begin
								//mem_search(req_data0);
								ipc_reply(`RSP_OK);
							end

						`OPEN_ALIVE_SOCKET: begin
								live_socket = new_fd;
								ipc_reply(`RSP_OK);
							end

						`CLOSE_ALIVE_SOCKET: begin
								live_socket = -1; 
								ipc_reply(`RSP_OK);
							end

						`VI_SNOOP_ON: begin
								enable_vi_snoop;
								ipc_reply(`RSP_OK);
							end

						`VI_SNOOP_OFF: begin
								disable_vi_snoop;
								ipc_reply(`RSP_OK);
							end

						`GET_VI_TAB_FILE: begin
								ret = $ipc_viget(rsp_data0);
								ipc_reply(`RSP_DATA);
							end

						`READ_VI_TAB_FILE: begin
								ret = $ipc_viread(req_data0, req_data1,
											rsp_data0, rsp_data1, rsp_data2, rsp_data3,
											rsp_data4, rsp_data5, rsp_data6, rsp_data7);
								ipc_reply(`RSP_DATA);
							end
`ifdef SIMCPU
`else
`ifdef	RSP_DUMMY
`else	// RSP_DUMMY
`ifdef SIMGATE
`else
						`RSP_CTRACE_TEST_ON : begin
								rsp_ctrace_on(req_data0[0], req_data0[2:1]);
								ipc_reply(`RSP_OK);
							end      
						`RSP_CTRACE_TEST_NEXT : begin
								rsp_ctrace_next;
								ipc_reply(`RSP_OK);
							end
						`RSP_CTRACE_TEST_OFF  : begin
								rsp_ctrace_off;
								ipc_reply(`RSP_OK);
							end
						`RSP_CTRACE_STATUS    : begin
								rsp_ctrace_status(rsp_data0);
								ipc_reply(`RSP_DATA);
							end
						`RSP_CTRACE_DATA	  : begin
								rsp_ctrace_data(req_address, req_size,
										rsp_data0, rsp_data1, rsp_data2, rsp_data3,
										rsp_data4, rsp_data5, rsp_data6, rsp_data7);
								ipc_reply(`RSP_DATA);
							end
						`RSP_IMEM_LOAD 	:	begin
								rsp_imem_load(req_address, req_data0, req_data1);
								ipc_reply(`RSP_OK);
							end					

						`RSP_DMEM_LOAD 	:	begin
								rsp_dmem_load(req_address,   
											  req_data0[15:8], req_data0[7:0]);
								ipc_reply(`RSP_OK);
							end					
`endif
`endif	// RSP_DUMMY
`endif // SIMCPU

						`BD_REQ_DUMP :	begin
								if (req_data0[0]) vsim.dump.dump = 1;
								else vsim.dump.dump = 0;
								ipc_reply(`RSP_OK);
							end
						`BD_REQ_SI_CTRL: begin 
								si_backdoor_setup(req_address, req_size,
									req_data0, req_data1, req_data2, req_data3,
									req_data4, req_data5, req_data6, req_data7);
								ipc_reply(`RSP_OK); 								
							end
						`BD_RD_SI_CTRL : begin
								si_backdoor_read( req_size,rsp_data0,
								 rsp_data1, rsp_data2, rsp_data3) ;
								ipc_reply(`RSP_DATA) ;
							end
						`BD_RD_SI_CTRL_PKD : begin
								si_backdoor_rd_pkd(req_address, req_size,
										rsp_data0, rsp_data1, rsp_data2, rsp_data3,
										rsp_data4, rsp_data5, rsp_data6, rsp_data7);
								ipc_reply(`RSP_DATA) ;
							end
						`BCP_USB_TEST_ON: begin
								// XXXXX will add to turn on 
								// which device(data0) later
								bb_usb_test_on(req_data0, req_data1);
								ipc_reply(`RSP_OK);	
							end
						`BCP_LINESTATE: begin
								if (req_data0)
							    	rsp_data0 = vsim.usb_tests.ext_host_ctl1.u_host_ctl.bcp_linestate;
								else
							    	rsp_data0 = vsim.usb_tests.ext_host_ctl0.u_host_ctl.bcp_linestate;
								ipc_reply(`RSP_DATA);	
							end
						`BCP_USB_OTG_DONE: begin
								if (req_data0) 
							    	vsim.usb_tests.ext_host_ctl1.u_host_ctl.otg_test_done=1;
								else
							    	vsim.usb_tests.ext_host_ctl0.u_host_ctl.otg_test_done=1;
								ipc_reply(`RSP_OK);	
							end 

						`BCP_USB_READ_STAT: begin
								bb_usb_stat(req_data0, rsp_data0);
								ipc_reply(`RSP_DATA);	
							end
						
						`BCP_USB_READ_DATA: begin /* max 4 bytes */
								bb_usb_read_packet(req_address, req_size,
										req_data0, rsp_data0);
								ipc_reply(`RSP_DATA);
							end

						`BCP_USB_WRITE_DATA: begin /* max 4 bytes */
								bb_usb_write_packet(req_address, req_size,
                                        req_data0, req_data1);
								ipc_reply(`RSP_OK);	
							end

						`BCP_USB_TERM_CTL: begin
								bb_usb_term_ctl(req_address, req_size, req_data0) ;
								ipc_reply(`RSP_OK) ;
							end
						`BCP_USB_BIAS_CTL: begin
								bb_usb_bias_ctl(req_address, req_size, req_data0) ;
								ipc_reply(`RSP_OK) ;
							end

						`BCP_USB_HOST_CTL: begin
								bb_usb_host_ctl(req_address, req_size, req_data0) ;
								ipc_reply(`RSP_OK) ;
							end
								
						`BD_MM_PRESENT: begin
								if (req_data0) 
									vsim.mm.fl_md = 1'bz;
								else 
									vsim.mm.fl_md = 0;
								ipc_reply(`RSP_OK);
								end
						`BD_JTAG_WRITE: begin
								vsim.jtag_tests.jtag_driver[3:0] = req_data0[3:0];
								ipc_reply(`RSP_OK);
								end
						`BD_JTAG_READ: begin
								rsp_data0 = vsim.jtag_tests.jtag_driver;
								ipc_reply(`RSP_OK);
								end
						`BD_JTAG_ENABLE: begin
								vsim.jtag_en = req_data0[0];
								ipc_reply(`RSP_OK);
								end
						`BD_DBUG_DWRITE: begin
								vsim.dbug.data_h_reg = req_data0 ;
								ipc_reply(`RSP_OK) ;
								end 
						`BD_DBUG_DREAD:	begin
								rsp_data0 = vsim.dbug.data_t_reg ;
								ipc_reply(`RSP_DATA) ;
								end
						`BD_DBUG_CWRITE: begin
								vsim.dbug.cmd_h_reg = req_data0[7:0] ;
								ipc_reply(`RSP_OK) ;
								end
						`BD_DBUG_CREAD : begin
								rsp_data0 = vsim.dbug.cmd_t_reg ;
								ipc_reply(`RSP_DATA) ;
								end
						`BD_PIN_RESET : begin
								vsim.rst_l = 0;
								repeat(16) @(posedge sysclk);
								vsim.rst_l = 1;
								ipc_reply(`RSP_OK);
								end
						`BD_CLOCK_MON_ENABLE : begin
								vsim.clk_mon.clock_mon = req_data0 ;
								ipc_reply(`RSP_OK);
								end

`ifdef SIMCPU
`else
						`BCP_SET_RSP_TIMEOUT: begin
								vsim.bb.cpu.rsp_timeout = req_data0;
								ipc_reply(`RSP_OK) ;
								end	
						`BCP_GET_RSP_TIMEOUT: begin
								rsp_data0 = vsim.bb.cpu.rsp_timeout;
								ipc_reply(`RSP_DATA) ;
								end	
`endif
						`BD_ZERO_STAT: begin
								if (req_data0 > 20) vsim.cbus_mon.zero_idle;
								else vsim.cbus_mon.zero_stat(req_data0[3:0]);
								ipc_reply(`RSP_OK) ;
								end	
						`BD_DISP_STAT: begin
								vsim.cbus_mon.dump_stat;
								ipc_reply(`RSP_OK) ;
								end	
						default: begin
								ipc_reply(`RSP_ERROR);
								$display("ERROR: %t: %M: ipc req %0d", $time, req_code);
							end
					endcase
				end
				if (live_socket < 0) begin
					if (ipc_mon &ipc_msg) $display("%t: %M: socket %d closed", $time, new_fd);
					ret = $ipc_close(new_fd);
				end
			end
		end
	end

endmodule