// vsim.v v1 Frank Berndt
// top level bcp verilog simulation;
// :set tabstop=4

`timescale 1ps/1ps

module vsim;

`include "define.vh"
`include "rcp.vh"

`ifdef	NANDRING
	initial
		$display("%M: enable nand ring testing");
`endif	// NANDRING

`ifdef	SIMGATE
	initial
		$display("%M: gate level simulator");
`endif	// SIMGATE

	// board clocks;

	wire sysclk;			// system clock, from oscillator;
	wire sysclkx2;			// 2x system clock used when bypassing pll
	wire usbclk;			// usb clock, from crystal;
	wire vclk;				// video clock, from crystal;
	integer board_del;

	// main memory interface;

	wire [1:0] #(board_del) mclk;	// memory clocks and board delay;
	wire          mcke;		// clock enables;
	wire [12:0] maddr;		// row/col address;
	wire [1:0] mbank;		// bank address;
	wire [31:0] mdata;		// data;
	wire mras, mcas, mwe;	// command;
	wire [3:0] mdqm;		// byte enables;
	wire [3:0] #(board_del) mdqs;	// strobe and board delay;

	wire [3:0] brd_mdqs;

	// video/audio DAC interface;

	wire vclock;			// video clock;
	wire [6:0] vdata;		// video data;
	wire vsync;				// video sync;
	wire aclock;			// audio clock;
	wire adata;				// audio data;
	wire aword;				// audio word clock;

	// controller interfaces;

	wire [3:1] jchan;		// joy channel ports;
	wire [1:0] lx;			// stick x port;
	wire [1:0] ly;			// stick x port;
	wire [1:0] bb_lx;
	wire [1:0] bb_ly;
	wire [1:0] nr_lx;
	wire [1:0] nr_ly;

	// generic io interface;

	wire io_rst;			// io bus reset;
	wire [15:0] io_ad;		// muxed io address/data bus;
	wire io_ale;			// io address latch enable;
	wire [3:0] io_cs;		// io pio chip selects;
	wire io_ior;			// io read pulse;
	wire io_iow;			// io write pulse;
	wire io_dmarq;			// io dma request;
	wire io_dmack;			// io dma acknowledge;
	wire io_intr;			// io device interrupt;
	wire bb_io_intr;	
	wire nr_io_intr;

	// NAND flash interface;

	wire [3:0] fl_ce;		// chip enables;
	wire fl_ale;			// address latch enable;
	wire fl_cle;			// command latch enable;
	wire fl_re;				// read eanble;
	wire fl_we;				// write eanble;
	wire fl_wp;				// write protect;
	wand fl_ryby;			// ready/busy;
	wire fl_md;				// module detect;
	wire bb_fl_md;
	wire nr_fl_md;

	// gpio signals;
	// gpio[0] power control, 0=off, 1=on;
	// gpio[1] error led, 0=on, 1=off;
	// gpio[3:2] are inputs;

	wire [3:0] gpio;		// gpio signals;

	// instantiate clock generators;
	// sysclk is oscillator;
	// usbclk and vclk are crystals;
	// default video clock is for NTSC;
	// clock periods are in ps;

	integer boardid_arg;
	integer period;
	reg [31:0] sysclk_period;
	reg [31:0] usbclk_period;
	reg [31:0] vclk_period;
	reg [15:6] board_id;

	initial
	begin
		sysclk_period = 16000;
		usbclk_period = 20000;
		vclk_period = 69841;
		board_id = { 4'b0000, 1'b0, 2'b00, 3'b000 };
		if($getnum$plusarg("boardid=", boardid_arg) == 1) begin
                        board_id = boardid_arg;

			// sysclk_period must be divisible for all div modes
			// and result in an even number.

			case(board_id[10:9])
				2'b00: sysclk_period = 16008;
				2'b01: sysclk_period = 12504;
				2'b10: sysclk_period = 10788;
				2'b11: sysclk_period = 10008;
			endcase

			case(board_id[13:12])
				2'b00: vclk_period = 69842;
				2'b01: vclk_period = 56388;
				2'b10: vclk_period = 69918;
				2'b11: vclk_period = 69842;
			endcase
			vclk_period[0] = 0;
		end

		// sysclk and vclk can be explictly set differnt than
		// spcecified by board_id value.

		if($getnum$plusarg("sysclk=", period) == 1)
			sysclk_period = period;
		if($getnum$plusarg("vclk=", period) == 1)
			vclk_period = period;
		if($getnum$plusarg("usbclk=", period) == 1)
			usbclk_period = period;

		// set memclk and strobe delay 
`ifdef TEST_VECTORS 
		board_del = ((sysclk_period / 8000) + 1)*1000;
`else
		board_del = ((sysclk_period / 80) + 1)*10;

`ifdef	SIMSDF
		board_del = board_del - 1300;
`endif	// SIMSDF
`endif	// TEST_VECTORS 
	end

	clkgen sysclk_gen ( .period	(sysclk_period), 
			    .clk	(sysclk), 
			    .xclk	(sysclkx2) );
	clkgen usbclk_gen ( .period(usbclk_period), .clk(usbclk) );
	clkgen vclk_gen   ( .period(vclk_period),   .clk(vclk) );

	// chip reset;
	// simulates power-on reset circuit;

	reg rst_l;				// chip reset;

	initial
	begin
		$timeformat(-9, 2, "ns", 13);
		vsim.bb.rst_l_reg <= 0;
		rst_l <= 0;
	`ifdef	NANDRING
		repeat(200) @(posedge sysclk);
	`endif	// NANDRING
		repeat(2000) @(posedge sysclk);
		rst_l <= 1;
	end

	// pwr_gd button (active 1);
	// simulates power-on/user button;
	// default to 1 to simulate push for power-on;

	
	
	wire tdo;
	reg	nring_enl ;
	reg	ring_xor ;
	reg	ring_fail ;
	reg	[132:0]	ring_select;
	integer	ring_count;
	reg	button ;
	initial
	   begin
		nring_enl <= 1'b1 ;
	`ifdef	NANDRING
		button    <= 1'b1 ;
		ring_select = {133{1'b0}};
		repeat(20)  @(posedge sysclk);
		nring_enl <= 1'b0 ;	// start nand ring test
		button    <= 1'b0 ;
		for (ring_count=132;ring_count>=0;ring_count=ring_count-1)
			begin   
			ring_select[ring_count] = 1'b1;
			@(posedge sysclk);
			ring_xor = (^ ring_select[132:1]) ^ (ring_count==1);
			ring_fail = (ring_xor==tdo);
			if (~(ring_fail===0)) 
				$display("%M: ERROR: nand ring testing failed");
			button    <= ~button;
			@(negedge sysclk);
		end
		nring_enl <= 1'b1 ;	// nand ring enable (1=normal op)
	`ifdef TEST_VECTORS
		$finish;
	`endif
	`endif	// NANDRING
		button <= 1'b1 ;
		repeat(20) @(posedge sysclk) ;
		button <= 1'b0 ;
	   end

	// usb signals;

	wire [1:0]  usb_dminus;
	wire [1:0]  usb_dplus;
	wire [1:0]  usb_dp_high;
	wire [1:0]  usb_d_low_n;
	wire [1:0]  usb_vbus_vld;
	wire [1:0]  usb_id;
	wire [1:0]  bb_usb_id;
	wire [1:0]  nr_usb_id;
	wire [1:0]  usb_vbus_on;

//	assign usb_vbus_vld = 2'b11 ;

	// JTAG signals
	wire trst;
	wire tdi;
	wire tms;
	wire tck;
	wire bb_trst;
	wire bb_tdi;
	wire bb_tms;
	wire bb_tck;
	wire nr_trst;
	wire nr_tdi;
	wire nr_tms;
	wire nr_tck;

	reg jtag_en;
	// Enable jtag
	initial
`ifdef TEST_VECTORS     // Nec asked to turned of jtag-en
		jtag_en = 0;
`else
		jtag_en = 1;
`endif

	// NEC TMC signal

	wire tmc = 1'b0;
	wire bb_tmc;
	wire nr_tmc;

	wire nectrst = 1'b0;
	wire bb_nectrst;
	wire nr_nectrst;

	// pll powers;

	wire pllx2_avdd = 1'b1;		// ddr pll power;
	wire pllx2_agnd = 1'b0;		// ddr pll ground;
	wire pllc_avdd = 1'b1;		// cpu pll power;
	wire pllc_agnd = 1'b0;		// cpu pll ground;
	wire pllv_avdd = 1'b1;		// video pll power;
	wire pllv_agnd = 1'b0;		// video pll ground;

	// drive gpio[3] with sysclkx2 if pll_bypass=1;
	// however, the gpio bit must be configured as input;

	assign gpio[3] = bb.pll_bypass? ~sysclkx2 : 1'bz;

	// instantiate bb chip;

	bb bb (
		.PAD_RST_L					(rst_l),
		.PAD_SYSCLK					(sysclk),
		.PAD_USBCLKI				(usbclk),
		.PAD_USBCLKO				(),
		.PAD_VCLKI					(vclk),
		.PAD_VCLKO					(),
		.PAD_BUTTON					(button),
		.PAD_VCLOCK					(vclock),
		.PAD_VDATA0					(vdata[0]),
		.PAD_VDATA1					(vdata[1]),
		.PAD_VDATA2					(vdata[2]),
		.PAD_VDATA3					(vdata[3]),
		.PAD_VDATA4					(vdata[4]),
		.PAD_VDATA5					(vdata[5]),
		.PAD_VDATA6					(vdata[6]),
		.PAD_VSYNC					(vsync),
		.PAD_VOA					(),
		.PAD_VOB					(),
		.PAD_VOC					(),
		.PAD_ACLOCK					(aclock),
		.PAD_ADATA					(adata),
		.PAD_AWORD					(aword),
		.PAD_JCHAN1					(jchan[1]),
		.PAD_JCHAN2					(jchan[2]),
		.PAD_JCHAN3					(jchan[3]),
		.PAD_LX0					(bb_lx[0]),
		.PAD_LX1					(bb_lx[1]),
		.PAD_LY0					(bb_ly[0]),
		.PAD_LY1					(bb_ly[1]),
		.PAD_IO_RST					(io_rst),
		.PAD_IO_AD0					(io_ad[0]),
		.PAD_IO_AD1					(io_ad[1]),
		.PAD_IO_AD2					(io_ad[2]),
		.PAD_IO_AD3					(io_ad[3]),
		.PAD_IO_AD4					(io_ad[4]),
		.PAD_IO_AD5					(io_ad[5]),
		.PAD_IO_AD6					(io_ad[6]),
		.PAD_IO_AD7					(io_ad[7]),
		.PAD_IO_AD8					(io_ad[8]),
		.PAD_IO_AD9					(io_ad[9]),
		.PAD_IO_AD10				(io_ad[10]),
		.PAD_IO_AD11				(io_ad[11]),
		.PAD_IO_AD12				(io_ad[12]),
		.PAD_IO_AD13				(io_ad[13]),
		.PAD_IO_AD14				(io_ad[14]),
		.PAD_IO_AD15				(io_ad[15]),
		.PAD_IO_ALE					(io_ale),
		.PAD_IO_CS0					(io_cs[0]),
		.PAD_IO_CS1					(io_cs[1]),
		.PAD_IO_CS2					(io_cs[2]),
		.PAD_IO_CS3					(io_cs[3]),
		.PAD_IO_IOR					(io_ior),
		.PAD_IO_IOW					(io_iow),
		.PAD_IO_DMARQ				(io_dmarq),
		.PAD_IO_DMACK				(io_dmack),
		.PAD_IO_INTR				(bb_io_intr),
		.PAD_NRING_ENL				(nring_enl),
		.PAD_FL_CE0					(fl_ce[0]),
		.PAD_FL_CE1					(fl_ce[1]),
		.PAD_FL_CE2					(fl_ce[2]),
		.PAD_FL_CE3					(fl_ce[3]),
		.PAD_FL_ALE					(fl_ale),
		.PAD_FL_CLE					(fl_cle),
		.PAD_FL_RE					(fl_re),
		.PAD_FL_WE					(fl_we),
		.PAD_FL_WP					(fl_wp),
		.PAD_FL_RYBY				(fl_ryby),
		.PAD_FL_MD					(bb_fl_md),
		.PAD_GPIO0					(gpio[0]),
		.PAD_GPIO1					(gpio[1]),
		.PAD_GPIO2					(gpio[2]),
		.PAD_GPIO3					(gpio[3]),
		.PAD_MCLK0					(mclk[0]),
		.PAD_MCLK1					(mclk[1]),
		.PAD_MCKE					(mcke),
		.PAD_MADDR0					(maddr[0]),
		.PAD_MADDR1					(maddr[1]),
		.PAD_MADDR2					(maddr[2]),
		.PAD_MADDR3					(maddr[3]),
		.PAD_MADDR4					(maddr[4]),
		.PAD_MADDR5					(maddr[5]),
		.PAD_MADDR6					(maddr[6]),
		.PAD_MADDR7					(maddr[7]),
		.PAD_MADDR8					(maddr[8]),
		.PAD_MADDR9					(maddr[9]),
		.PAD_MADDR10				(maddr[10]),
		.PAD_MADDR11				(maddr[11]),
		.PAD_MADDR12				(maddr[12]),
		.PAD_MBANK0					(mbank[0]),
		.PAD_MBANK1					(mbank[1]),
		.PAD_MDATA0					(mdata[0]),
		.PAD_MDATA1					(mdata[1]),
		.PAD_MDATA2					(mdata[2]),
		.PAD_MDATA3					(mdata[3]),
		.PAD_MDATA4					(mdata[4]),
		.PAD_MDATA5					(mdata[5]),
		.PAD_MDATA6					(mdata[6]),
		.PAD_MDATA7					(mdata[7]),
		.PAD_MDATA8					(mdata[8]),
		.PAD_MDATA9					(mdata[9]),
		.PAD_MDATA10				(mdata[10]),
		.PAD_MDATA11				(mdata[11]),
		.PAD_MDATA12				(mdata[12]),
		.PAD_MDATA13				(mdata[13]),
		.PAD_MDATA14				(mdata[14]),
		.PAD_MDATA15				(mdata[15]),
		.PAD_MDATA16				(mdata[16]),
		.PAD_MDATA17				(mdata[17]),
		.PAD_MDATA18				(mdata[18]),
		.PAD_MDATA19				(mdata[19]),
		.PAD_MDATA20				(mdata[20]),
		.PAD_MDATA21				(mdata[21]),
		.PAD_MDATA22				(mdata[22]),
		.PAD_MDATA23				(mdata[23]),
		.PAD_MDATA24				(mdata[24]),
		.PAD_MDATA25				(mdata[25]),
		.PAD_MDATA26				(mdata[26]),
		.PAD_MDATA27				(mdata[27]),
		.PAD_MDATA28				(mdata[28]),
		.PAD_MDATA29				(mdata[29]),
		.PAD_MDATA30				(mdata[30]),
		.PAD_MDATA31				(mdata[31]),
		.PAD_MRAS					(mras),
		.PAD_MCAS					(mcas),
		.PAD_MWE					(mwe),
		.PAD_MDQM0					(mdqm[0]),
		.PAD_MDQM1					(mdqm[1]),
		.PAD_MDQM2					(mdqm[2]),
		.PAD_MDQM3					(mdqm[3]),
		.PAD_MDQS0					(mdqs[0]),
		.PAD_MDQS1					(mdqs[1]),
		.PAD_MDQS2					(mdqs[2]),
		.PAD_MDQS3					(mdqs[3]),
		.PAD_USB_DPLUS0				(usb_dplus[0]),
		.PAD_USB_DPLUS1				(usb_dplus[1]),
		.PAD_USB_DMINUS0			(usb_dminus[0]),
		.PAD_USB_DMINUS1			(usb_dminus[1]),
		.PAD_USB_DP_HIGH0			(usb_dp_high[0]),
		.PAD_USB_DP_HIGH1			(usb_dp_high[1]),
		.PAD_USB_D_LOW_N0			(usb_d_low_n[0]),
		.PAD_USB_D_LOW_N1			(usb_d_low_n[1]),
		.PAD_USB_VBUS_VLD0			(usb_vbus_vld[0]),
		.PAD_USB_VBUS_VLD1			(usb_vbus_vld[1]),
		.PAD_USB_ID0				(bb_usb_id[0]),
		.PAD_USB_ID1				(bb_usb_id[1]),
		.PAD_USB_VBUS_ON0			(usb_vbus_on[0]),
		.PAD_USB_VBUS_ON1			(usb_vbus_on[1]),
		.PAD_TRST					(bb_trst), 
		.PAD_TDI					(bb_tdi), 
		.PAD_TMS					(bb_tms), 
		.PAD_TCK					(bb_tck), 
		.PAD_TDO					(tdo),
		.PAD_PLLX2_AVDD				(pllx2_avdd),
		.PAD_PLLX2_AGND				(pllx2_agnd),
		.PAD_PLLC_AVDD				(pllc_avdd),
		.PAD_PLLC_AGND				(pllc_agnd),
		.PAD_PLLV_AVDD				(pllv_avdd),
		.PAD_PLLV_AGND				(pllv_agnd),
		.PAD_JTAG_EN				(jtag_en),
		.PAD_TMC					(bb_tmc),
		.PAD_NECTRST				(bb_nectrst)
	);

`ifdef	SIMSDF
	initial
	begin
		$display("%M: sdf simulation");
`ifdef BBFIX
		$sdf_annotate("../fixes/bb.sdf", bb,, "sdf.log");
`else
		$sdf_annotate("../syn/bb.sdf", bb,, "sdf.log");
`endif
	end
`endif	// SIMSDF

	// instantiate main memory and dv backdoor;
	// only for real ri rtl, not for ri model;

	// monitor ddr model;

	reg ddr_mon;
	reg ddr_x16;

	initial
		ddr_mon = $test$plusargs("ddr_mon");

	wire	mcs = 1'b0;

`ifdef  DDR32M16
 
	parameter MEM_NADDR = 27;               // # of address bit in x64 space;
	parameter MEM_SIZE = (1 << MEM_NADDR);  // size of x64 space;
                                    
	initial
	begin
		$display("%M: memory 32m16, 16MB");
		ddr_x16 = 1;
	end

`include "mem.v"
`include "mem_ri32m16.v"

	assign vsim.ddr0.Debug = ddr_mon;
	assign vsim.ddr1.Debug = ddr_mon;

	mt46v32m16 ddr0  (
		.Dq	(mdata[31:16]),
		.Dqs	(mdqs[3:2]),
		.Addr	(maddr[12:0]),
		.Ba	(mbank),
		.Clk	(mclk[0]),
		.Clk_n	(mclk[1]),
		.Cke	(mcke),
		.Cs_n	(mcs),
		.Ras_n	(mras),
		.Cas_n	(mcas),
		.We_n	(mwe),
		.Dm	(mdqm[3:2])
	);
	mt46v32m16 ddr1 (
		.Dq	(mdata[15:0]),
		.Dqs	(mdqs[1:0]),
		.Addr	(maddr[12:0]),
		.Ba	(mbank),
		.Clk	(mclk[0]),
		.Clk_n	(mclk[1]),
		.Cke	(mcke),
		.Cs_n	(mcs),
		.Ras_n	(mras),
		.Cas_n	(mcas),
		.We_n	(mwe),
		.Dm	(mdqm[1:0])
	);

`else	// DDR32M16

	parameter MEM_NADDR = 24;				// # of address bit in x64 space;
	parameter MEM_SIZE = (1 << MEM_NADDR);	// size of x64 space;

	initial
	begin
		$display("%M: memory 8m32, 16MB");
		ddr_x16 = 0;
	end

`include "mem.v"
`include "mem_ri.v"

	assign vsim.ddr.Debug = ddr_mon;

	mt46v4m32_tsop ddr (
		.Dq	(mdata),
		.Dqs	(mdqs),
		.Addr	(maddr[11:0]),
		.Ba	(mbank),
		.Clk	(mclk[0]),
		.Clk_n	(mclk[1]),
		.Cke	(mcke),
		.Cs_n	(mcs),
		.Ras_n	(mras),
		.Cas_n	(mcas),
		.We_n	(mwe),
		.Dm	(mdqm)
	);
`endif

	// instantiate joychannel controllers;

	jctrl jctrl1 ( .jbus(jchan[1]) );
	jctrl jctrl2 ( .jbus(jchan[2]) );
	jctrl jctrl3 ( .jbus(jchan[3]) );

	// instantiate local controller;

	lctrl lctrl (
		.lx(lx),
		.ly(ly),
		.lout(io_ad),
`ifdef  LCTRL_BUTTON_ON
		.lena((io_cs[2] | ~nring_enl))
`else
		.lena((io_ior | io_cs[2] | ~nring_enl))
`endif
	);

	// instantiate master controller

	contlr_mstr mjctrl (.jchan(jchan[1])) ;

	// instantiate flash memory module;
	// pull chip side signals;

	flashmm mm (
		.fl_md(fl_md),
		.fl_db(io_ad[15:8]),
		.fl_cle(fl_cle),
		.fl_ale(fl_ale),
		.fl_ce((fl_ce | {4{~nring_enl}})),
		.fl_re(fl_re),
		.fl_we(fl_we),
		.fl_ryby(fl_ryby),
		.fl_wp(fl_wp)
	);

	pullup ( fl_md );
	pullup ( fl_ryby );
	pulldown ( fl_wp );

	// drive board id during pin reset;
	// id is initially set to 0xf05a;

	bufif0 (highz1,pull0)
	   g15	(io_ad[15],1'b0,board_id[15]),
	   g14  (io_ad[14],1'b0,board_id[14]),
	   g13	(io_ad[13],1'b0,board_id[13]),
	   g12	(io_ad[12],1'b0,board_id[12]),
	   g11	(io_ad[11],1'b0,board_id[11]),
	   g10	(io_ad[10],1'b0,board_id[10]),
	   g9	(io_ad[9],1'b0,board_id[9]),
	   g8	(io_ad[8],1'b0,board_id[8]),
	   g7	(io_ad[7],1'b0,board_id[7]),
	   g6	(io_ad[6],1'b0,board_id[6]);

	bufif1 (pull1,highz0)
	   h15	(io_ad[15],1'b1,board_id[15]),
	   h14  (io_ad[14],1'b1,board_id[14]),
	   h13	(io_ad[13],1'b1,board_id[13]),
	   h12	(io_ad[12],1'b1,board_id[12]),
	   h11	(io_ad[11],1'b1,board_id[11]),
	   h10	(io_ad[10],1'b1,board_id[10]),
	   h9	(io_ad[9],1'b1,board_id[9]),
	   h8	(io_ad[8],1'b1,board_id[8]),
	   h7	(io_ad[7],1'b1,board_id[7]),
	   h6	(io_ad[6],1'b1,board_id[6]);

	// assign io_ad[15:6] = rst_l? 10'bz : board_id;

	// instantiate ide device model;
	// XXX

	assign io_dmarq = 0; //XXX

	// instantiate debug port

	pulldown(io_intr) ;

	debug_prt	dbug
		(.cs_i((io_cs[0] | ~nring_enl)) ,
		 .ale_i(io_ale) ,
		 .ior_i(io_ior) ,
		 .iow_i(io_iow) ,
		 .iorst_i(io_rst) ,
		 .ioirq_o(io_intr) ,
		 .ad_io(io_ad) ) ;

	// instantiate dump control module;

	dump dump ();

	// initialize virage novea arrays from files;
	// done on after 10 clocks to avoid the earom blasting 
	// that happens in the beginning

	reg [1:256*8] v0file;
	reg [1:256*8] v1file;
	reg [1:256*8] v2file;

	initial
	begin
		repeat (10) @(posedge sysclk);
		if($getstr$plusarg("v0=", v0file) != 1)
			v0file = "tests/v0.dat";
		$display("%t: %M: v0 recall: %0s", $time, v0file);
		$readmemh(v0file, bb.v0.vsc.I_NOVeA.I_NOVeA_Expand.uut.earom);

		if($getstr$plusarg("v1=", v1file) != 1)
			v1file = "tests/v1.dat";
		$display("%t: %M: v1 recall: %0s", $time, v1file);
		$readmemh(v1file, bb.v1.vsc.I_NOVeA.I_NOVeA_Expand.uut.earom);

		if($getstr$plusarg("v2=", v2file) != 1)
			v2file = "tests/v2.dat";
		$display("%t: %M: v2 recall: %0s", $time, v2file);
		$readmemh(v2file, bb.v2.vsc.I_NOVeA.I_NOVeA_Expand.uut.earom);
	end

	// This is used through IDE to force re-load of the earom
	// from the file
	reg [2:0] virage_restore;

	always @(virage_restore)
	begin
		if (virage_restore[0]) 
		begin
			if($getstr$plusarg("v0=", v0file) != 1)
				v0file = "tests/v0.dat";
			$display("%t: %M: v0 recall: %0s", $time, v0file);
			$readmemh(v0file, bb.v0.vsc.I_NOVeA.I_NOVeA_Expand.uut.earom);

		end
		if (virage_restore[1]) 
		begin
			if($getstr$plusarg("v1=", v1file) != 1)
				v1file = "tests/v1.dat";
			$display("%t: %M: v1 recall: %0s", $time, v1file);
			$readmemh(v1file, bb.v1.vsc.I_NOVeA.I_NOVeA_Expand.uut.earom);
		end
		if (virage_restore[2]) 
		begin
			if($getstr$plusarg("v2=", v2file) != 1)
				v2file = "tests/v2.dat";
			$display("%t: %M: v2 recall: %0s", $time, v2file);
			$readmemh(v2file, bb.v2.vsc.I_NOVeA.I_NOVeA_Expand.uut.earom);
		end

	end

	// short-cut cpu pll stand-by time;

`ifdef	SIMCPU
`ifdef	RESET_FAST
	always @(bb.cpu.NB4300.pll.ABPLSSCH_IF.PLL._STBY)
	begin
		if(bb.cpu.NB4300.pll.ABPLSSCH_IF.PLL._STBY == 1)
			force bb.cpu.NB4300.pll.ABPLSSCH_IF.PLL._PBSTBY = 1'b1;
		if(bb.cpu.NB4300.pll.ABPLSSCH_IF.PLL._STBY == 0)
			force bb.cpu.NB4300.pll.ABPLSSCH_IF.PLL._PBSTBY = 1'b0;
	end
`endif	// RESET_FAST
`endif	// SIMCPU

	// monitor chip reset signal;

	always @(rst_l)
	begin
		if(!rst_l)
			$display("%t: %M: chip reset asserted", $time);
		else
			$display("%t: %M: chip reset deasserted", $time);
	end
	
	wire	memclk_mon = bb.pll_bypass ? 1'b0 : bb.memclk;

	// instantiate clock monitor;

	clk_mon clk_mon (
		.sysclk(bb.sysclk),
		.memclk(memclk_mon),
		.reset_l(bb.reset_l)
	);

	// instantiate cpu monitor;
	
	wire [4:0] bb_int_l;
	wire [31:0] bb_sysad_out;
	wire [4:0] bb_syscmd_out;
	wire bb_bcp_mi_sec_mode_0;
	wire [2:0] bb_divmode;
	wire [31:0] bb_sysad_in;
	wire [4:0] bb_syscmd_in;
	wire [1:0] bb_pll_lock;

`ifdef  SIMGATE
	assign bb_int_l = { bb.int_l_4_, bb.int_l_3_, bb.int_l_2_, 
						bb.int_l_1_, bb.int_l_0_};
	assign bb_sysad_out = { bb.sysad_out_31_, bb.sysad_out_30_, 
							bb.sysad_out_29_, bb.sysad_out_28_,
							bb.sysad_out_27_, bb.sysad_out_26_,
							bb.sysad_out_25_, bb.sysad_out_24_,
							bb.sysad_out_23_, bb.sysad_out_22_,
							bb.sysad_out_21_, bb.sysad_out_20_,
							bb.sysad_out_19_, bb.sysad_out_18_,
							bb.sysad_out_17_, bb.sysad_out_16_,
							bb.sysad_out_15_, bb.sysad_out_14_,
							bb.sysad_out_13_, bb.sysad_out_12_,
							bb.sysad_out_11_, bb.sysad_out_10_,
							bb.sysad_out_9_, bb.sysad_out_8_,
							bb.sysad_out_7_, bb.sysad_out_6_,
							bb.sysad_out_5_, bb.sysad_out_4_,
							bb.sysad_out_3_, bb.sysad_out_2_,
							bb.sysad_out_1_, bb.sysad_out_0_};
	assign bb_syscmd_out = { bb.syscmd_out_4_, bb.syscmd_out_3_,
							 bb.syscmd_out_2_, bb.syscmd_out_1_,
							 bb.syscmd_out_0_};
	assign bb_bcp_mi_sec_mode_0 = bb.bcp.mi.sec_mode_0_;  //XXXXX mi
	assign bb_divmode = { bb.divmode_2_, bb.divmode_1_, bb.divmode_0_};
	assign bb_sysad_in = { bb.sysad_in_31_, bb.sysad_in_30_, 
							bb.sysad_in_29_, bb.sysad_in_28_,
							bb.sysad_in_27_, bb.sysad_in_26_,
							bb.sysad_in_25_, bb.sysad_in_24_,
							bb.sysad_in_23_, bb.sysad_in_22_,
							bb.sysad_in_21_, bb.sysad_in_20_,
							bb.sysad_in_19_, bb.sysad_in_18_,
							bb.sysad_in_17_, bb.sysad_in_16_,
							bb.sysad_in_15_, bb.sysad_in_14_,
							bb.sysad_in_13_, bb.sysad_in_12_,
							bb.sysad_in_11_, bb.sysad_in_10_,
							bb.sysad_in_9_, bb.sysad_in_8_,
							bb.sysad_in_7_, bb.sysad_in_6_,
							bb.sysad_in_5_, bb.sysad_in_4_,
							bb.sysad_in_3_, bb.sysad_in_2_,
							bb.sysad_in_1_, bb.sysad_in_0_};
	assign bb_syscmd_in = { 1'b1, bb.syscmd_in_3_,
							 bb.syscmd_in_2_, bb.syscmd_in_1_,
							 1'b0};
	assign bb_pll_lock = { bb.pllx2_lock, bb.pll_lock_0_};
							
`else
	assign bb_int_l = bb.int_l; 
	assign bb_sysad_out = bb.sysad_out;
	assign bb_syscmd_out = bb.syscmd_out;
	assign bb_bcp_mi_sec_mode_0 = bb.bcp.mi.sec_mode[0];
	assign bb_divmode = bb.divmode;
	assign bb_syscmd_in = bb.syscmd_in;
	assign bb_sysad_in = bb.sysad_in;
	assign bb_sysad_in = bb.sysad_in;
	assign bb_pll_lock = bb.pll_lock;
`endif

	cpu_mon cpu_mon (
		.sysclk(bb.sysclk),
		.divmode(bb_divmode),
		.coldrst_l(bb.coldrst_l),
		.warmrst_l(bb.warmrst_l),
		.pll_lock(bb_pll_lock),
		.eok_l(bb.eok_l),
		.sysad_out(bb_sysad_out),
		.syscmd_out(bb_syscmd_out),
		.pvalid_l(bb.pvalid_l),
		.sysad_in(bb_sysad_in),
		.syscmd_in(bb_syscmd_in),
		.evalid_l(bb.evalid_l),
		.int_l(bb_int_l),
		.nmi_l(bb.nmi_l),
		.secure(bb_bcp_mi_sec_mode_0),
		.stim_load(bb.bcp.mi.stim_load),
		.stim_set(bb.bcp.mi.stim_set)
	);
	

	// cbus monitor;

	wire cbus_val;
	wire [3:0] cbus_dev;
	wire ri_dbus_write_enable;

	assign ri_dbus_write_enable = bb.bcp.ri.DBusOE;

	wire [31:0] bb_bcp_cbus_din;
	wire [2:0] bb_bcp_cbus_command;
	wire [1:0] bb_bcp_cbus_select;

`ifdef SIMGATE
	assign bb_bcp_cbus_din = { 
				bb.bcp.cbus_din_31_, bb.bcp.cbus_din_30_,
				bb.bcp.cbus_din_29_, bb.bcp.cbus_din_28_,
				bb.bcp.cbus_din_27_, bb.bcp.cbus_din_26_,
				bb.bcp.cbus_din_25_, bb.bcp.cbus_din_24_,
				bb.bcp.cbus_din_23_, bb.bcp.cbus_din_22_,
				bb.bcp.cbus_din_21_, bb.bcp.cbus_din_20_,
				bb.bcp.cbus_din_19_, bb.bcp.cbus_din_18_,
				bb.bcp.cbus_din_17_, bb.bcp.cbus_din_16_,
				bb.bcp.cbus_din_15_, bb.bcp.cbus_din_14_,
				bb.bcp.cbus_din_13_, bb.bcp.cbus_din_12_,
				bb.bcp.cbus_din_11_, bb.bcp.cbus_din_10_,
				bb.bcp.cbus_din_9_, bb.bcp.cbus_din_8_,
				bb.bcp.cbus_din_7_, bb.bcp.cbus_din_6_,
				bb.bcp.cbus_din_5_, bb.bcp.cbus_din_4_,
				bb.bcp.cbus_din_3_, bb.bcp.cbus_din_2_,
				bb.bcp.cbus_din_1_, bb.bcp.cbus_din_0_};
	assign bb_bcp_cbus_command = { bb.bcp.cbus_command_2_,  
				bb.bcp.cbus_command_1_, bb.bcp.cbus_command_0_};
	assign bb_bcp_cbus_select = { bb.bcp.cbus_select_1_, bb.bcp.cbus_select_0_};
`else
	assign bb_bcp_cbus_din = bb.bcp.cbus_din;
	assign bb_bcp_cbus_command = bb.bcp.cbus_command;
	assign bb_bcp_cbus_select = bb.bcp.cbus_select;
`endif

	cbus_mon cbus_mon (
		.sysclk(bb.sysclk),
		.reset_l(bb.reset_l),
		.cbus_command(bb_bcp_cbus_command),
		.cbus_select(bb_bcp_cbus_select),
		.cbus_data(bb_bcp_cbus_din),
		.cbus_val(cbus_val),
		.cbus_dev(cbus_dev),
		.mi_cbus_write_request(bb.bcp.mi_cbus_write_request),
		.mi_cbus_read_request(bb.bcp.mi_cbus_read_request),
		.sp_dma_request(bb.bcp.sp_dma_request),
		.mi_dma_request(bb.bcp.mi_dma_request),
		.ai_dma_request(bb.bcp.ai_dma_request),
		.pi_dma_request(bb.bcp.pi_dma_request),
		.vi_dma_request(bb.bcp.vi_dma_request),
		.ui_dma_request(bb.bcp.ui_dma_request),
		.si_dma_request(bb.bcp.si_dma_request),
		.cmd_dma_request(bb.bcp.cmd_dma_request),
		.span_dma_request(bb.bcp.span_dma_request),
		.mi_cbus_write_enable(bb.bcp.mi_cbus_write_enable),
		.sp_cbus_write_enable(bb.bcp.sp_cbus_write_enable),
		.span_cbus_write_enable(bb.bcp.span_cbus_write_enable),
		.cmd_cbus_write_enable(bb.bcp.cmd_cbus_write_enable),
		.pi_cbus_write_enable(bb.bcp.pi_cbus_write_enable),
		.ri_cbus_write_enable(bb.bcp.ri_cbus_write_enable),
		.si_cbus_write_enable(bb.bcp.si_cbus_write_enable),
		.ai_cbus_write_enable(bb.bcp.ai_cbus_write_enable),
		.vi_cbus_write_enable(bb.bcp.vi_cbus_write_enable),
		.mem_cbus_write_enable(bb.bcp.mem_cbus_write_enable),
		.ui_cbus_write_enable(bb.bcp.ui_cbus_write_enable)
	);
	

	wire [63:0] bb_bcp_dbus_din;
    wire [7:0]  bb_bcp_ebus_din;

`ifdef	SIMGATE
	assign bb_bcp_dbus_din = {
				bb.bcp.dbus_din_63_, bb.bcp.dbus_din_62_,	
				bb.bcp.dbus_din_61_, bb.bcp.dbus_din_60_,	
				bb.bcp.dbus_din_59_, bb.bcp.dbus_din_58_,	
				bb.bcp.dbus_din_57_, bb.bcp.dbus_din_56_,	
				bb.bcp.dbus_din_55_, bb.bcp.dbus_din_54_,	
				bb.bcp.dbus_din_53_, bb.bcp.dbus_din_52_,	
				bb.bcp.dbus_din_51_, bb.bcp.dbus_din_50_,	
				bb.bcp.dbus_din_49_, bb.bcp.dbus_din_48_,	
				bb.bcp.dbus_din_47_, bb.bcp.dbus_din_46_,	
				bb.bcp.dbus_din_45_, bb.bcp.dbus_din_44_,	
				bb.bcp.dbus_din_43_, bb.bcp.dbus_din_42_,	
				bb.bcp.dbus_din_41_, bb.bcp.dbus_din_40_,	
				bb.bcp.dbus_din_39_, bb.bcp.dbus_din_38_,	
				bb.bcp.dbus_din_37_, bb.bcp.dbus_din_36_,	
				bb.bcp.dbus_din_35_, bb.bcp.dbus_din_34_,	
				bb.bcp.dbus_din_33_, bb.bcp.dbus_din_32_,	
				bb.bcp.dbus_din_31_, bb.bcp.dbus_din_30_,	
				bb.bcp.dbus_din_29_, bb.bcp.dbus_din_28_,	
				bb.bcp.dbus_din_27_, bb.bcp.dbus_din_26_,	
				bb.bcp.dbus_din_25_, bb.bcp.dbus_din_24_,	
				bb.bcp.dbus_din_23_, bb.bcp.dbus_din_22_,	
				bb.bcp.dbus_din_21_, bb.bcp.dbus_din_20_,	
				bb.bcp.dbus_din_19_, bb.bcp.dbus_din_18_,	
				bb.bcp.dbus_din_17_, bb.bcp.dbus_din_16_,	
				bb.bcp.dbus_din_15_, bb.bcp.dbus_din_14_,	
				bb.bcp.dbus_din_13_, bb.bcp.dbus_din_12_,	
				bb.bcp.dbus_din_11_, bb.bcp.dbus_din_10_,	
				bb.bcp.dbus_din_9_, bb.bcp.dbus_din_8_,	
				bb.bcp.dbus_din_7_, bb.bcp.dbus_din_6_,	
				bb.bcp.dbus_din_5_, bb.bcp.dbus_din_4_,	
				bb.bcp.dbus_din_3_, bb.bcp.dbus_din_2_,	
				bb.bcp.dbus_din_1_, bb.bcp.dbus_din_0_};

	assign bb_bcp_ebus_din = {
				bb.bcp.ebus_din_7_, bb.bcp.ebus_din_6_,
				bb.bcp.ebus_din_5_, bb.bcp.ebus_din_4_,
				bb.bcp.ebus_din_3_, bb.bcp.ebus_din_2_,
				bb.bcp.ebus_din_1_, bb.bcp.ebus_din_0_};

`else	//SIMGATE
	assign bb_bcp_dbus_din = bb.bcp.dbus_din;
	assign bb_bcp_ebus_din = bb.bcp.ebus_din;
`endif

	dbus_mon dbus_mon (
		.sysclk(bb.sysclk),
		.reset_l(bb.reset_l),
		.cbus_val(cbus_val),
		.cbus_dev(cbus_dev),
		.dbus_data(bb_bcp_dbus_din),
		.ebus_data(bb_bcp_ebus_din),
		.mi_dma_start(bb.bcp.mi_dma_start),
		.mi_dma_last(bb.bcp.mi_dma_last),
		.mi_dbus_write_enable(bb.bcp.mi_dbus_write_enable),
		.sp_dma_start(bb.bcp.sp_dma_start),
		.sp_dma_last(bb.bcp.sp_dma_last),
		.sp_dbus_write_enable(bb.bcp.sp_dbus_write_enable),
		.span_dma_start(bb.bcp.span_dma_start),
		.span_dma_last(bb.bcp.span_dma_last),
		.span_dbus_write_enable(bb.bcp.span_dbus_write_enable),
		.pi_dma_start(bb.bcp.pi_dma_start),
		.pi_dma_last(bb.bcp.pi_dma_last),
		.pi_dbus_write_enable(bb.bcp.pi_dbus_write_enable),
		.si_dma_start(bb.bcp.si_dma_start),
		.si_dma_last(bb.bcp.si_dma_last),
		.si_dbus_write_enable(bb.bcp.si_dbus_write_enable),
		.vi_dma_start(bb.bcp.vi_dma_start),
		.vi_dma_last(bb.bcp.vi_dma_last),
		.vi_dbus_write_enable(1'b0),
		.ai_dma_start(bb.bcp.ai_dma_start),
		//.ai_dma_last(bb.bcp.ai_dma_last),   // XXXXX Not exist in GL
		.ai_dbus_write_enable(1'b0),
		.ui_dma_start(bb.bcp.ui_dma_start),
		.ui_dbus_write_enable(bb.bcp.ui_dbus_write_enable),
		.ri_dbus_write_enable(ri_dbus_write_enable)
	);

	// do not compile in rsp c-tracer for dummy rsp;

`ifdef SIMGATE
`else
`ifdef	RSP_DUMMY
`else	// RSP_DUMMY
	rsp_ctrace rsp_ctrace ();
`endif	// RSP_DUMMY
`endif	

	vbus_mon vbus_mon();

	// Audio test DAC
	test_adac test_adac_0( bb.reset_l, 32'b0, adata, aclock, aword);


// test and monitor modules
`ifdef GATE_LEVEL
`else
xbus_mon xbus_mon_0(bb.sysclk, bb.reset_l);
`endif

	// instantiate io bus monitor;

	io_mon io_mon (
		.reset_l(bb.reset_l),
		.io_rst(io_rst),
		.io_ad(io_ad),
		.io_ale(io_ale),
		.io_cs(io_cs),
		.io_ior(io_ior),
		.io_iow(io_iow),
		.io_dmarq(io_dmarq),
		.io_dmack(io_dmack),
		.io_intr(io_intr),
		.fl_ce(fl_ce),
		.fl_ale(fl_ale),
		.fl_cle(fl_cle),
		.fl_re(fl_re),
		.fl_we(fl_we),
		.fl_wp(fl_wp),
		.fl_ryby(fl_ryby),
		.fl_md(fl_md)
	);

	// instantiate ide debug space devices;
	// aids and backdoors for dv;
	// hangs on io_cs[3], see include/addr.vh;

	ide_dev ide_dev (
		.sysclk(bb.sysclk),
		.reset_l(bb.reset_l),
		.io_rst(io_rst),
		.io_ad(io_ad),
		.io_ale(io_ale),
		.io_cs(io_cs),
		.io_ior(io_ior),
		.io_iow(io_iow),
		.io_intr(io_intr),
		.gpio(gpio)
	);

	// USB test modules
	usb_tests  usb_tests(
		.usb_dminus(usb_dminus),
		.usb_dplus(usb_dplus),
		.usb_dp_high(usb_dp_high),
		.usb_d_low_n(usb_d_low_n),
		.usb_vbus_vld(usb_vbus_vld),
		.usb_id(usb_id),
		.usb_vbus_on(usb_vbus_on)	
	);

	// JTAG testing
	jtag_tests jtag_tests(
		.trst(trst),
		.tdi(tdi),
		.tms(tms),
		.tck(tck),
		.tdo(tdo)
	);

	// gpio monitor;

	always @(gpio)
	begin
		//$display("%t: %M: gpio %b", $time, gpio);
	end


`ifdef IPC
	ipc ipc(.sysclk(bb.sysclk),
		.coldrst_l(bb.coldrst_l),
		.warmrst_l(bb.warmrst_l)
	);
`endif

	assign	bb_lx = nring_enl ? lx : nr_lx;
	assign	bb_ly = nring_enl ? ly : nr_ly;
	assign	bb_io_intr = nring_enl ? io_intr : nr_io_intr;
	assign	bb_fl_md = nring_enl ? fl_md : nr_fl_md;
	assign	bb_usb_id = nring_enl ? usb_id : nr_usb_id;
	assign	bb_trst = nring_enl ? trst : nr_trst;
	assign	bb_tdi = nring_enl ? tdi : nr_tdi;
	assign	bb_tms = nring_enl ? tms : nr_tms;
	assign	bb_tck = nring_enl ? tck : nr_tck;
	assign	bb_tmc = nring_enl ? tmc : nr_tmc;
	assign  bb_nectrst = nectrst;

	assign	{	mclk,
	 			mdqs,
				mdata,
				mras,
				mcas,
				mwe,
				mbank,
				mcke,
				maddr,
				mdqm,
				vdata,
				vclock,
				vsync,
				aclock,
				adata,
				aword,
				jchan,
				nr_lx,
				nr_ly,
				nr_io_intr,
				io_ad,
				io_rst,
				io_cs,
				io_ale,
				io_ior,
				io_iow,
				fl_ryby,
				nr_fl_md,
				fl_ale,
				fl_cle,
				fl_re,
				fl_we,
				fl_wp,
				fl_ce[2:0],
				gpio,
				nr_usb_id,
				usb_vbus_on,
				usb_dp_high,
				usb_d_low_n,
				nr_trst,
				nr_tdi,
				nr_tms,
				nr_tck,
				nr_tmc } = nring_enl ? {132{1'bz}} : ring_select[132:1];

endmodule