AND16.v
820 Bytes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
// $Header: /root/leakn64/depot/rf/hw/debug/xilinx/AND16.v,v 1.1 2003/04/01 21:47:33 berndt Exp $
/*
FUNCTION : 16-INPUT AND GATE
*/
`timescale 100 ps / 10 ps
module AND16 (O, I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15);
output O;
input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;
and O1 (O, I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15);
specify
(I0 *> O) = (1, 1);
(I1 *> O) = (1, 1);
(I2 *> O) = (1, 1);
(I3 *> O) = (1, 1);
(I4 *> O) = (1, 1);
(I5 *> O) = (1, 1);
(I6 *> O) = (1, 1);
(I7 *> O) = (1, 1);
(I8 *> O) = (1, 1);
(I9 *> O) = (1, 1);
(I10 *> O) = (1, 1);
(I11 *> O) = (1, 1);
(I12 *> O) = (1, 1);
(I13 *> O) = (1, 1);
(I14 *> O) = (1, 1);
(I15 *> O) = (1, 1);
endspecify
endmodule