access_util.c
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#include "ultra64.h"
#include "os_bb.h"
#include "bcp.h"
#include "access.h"
#include "access_util.h"
#include "nu64sys.h"
#include "graph.h"
void exitSecureMode(){
u32 error;
/* grant no access to buffer dma, aes, atb, flash, buf*/
IO_WRITE(PI_ACCESS_REG, 0x00000000);
/*
* Exit secure mode: no ISRAM access
*/
error = IO_READ(MI_SEC_MODE_REG);
error = error & 0x42;
IO_WRITE(MI_SEC_MODE_REG, error);
}
/* input data, write in and read out, compare */
int sram_write_test(u32 *data, u32 array_addr, int size){
int i;
u32 x;
for (i=0; i<size; i++) {
IO_WRITE(array_addr+(i<<2), data[i]);
x = IO_READ(array_addr+(i<<2));
if (x != data[i]) {
return FAIL;
}
}
return PASS;
}
/* read and compare with data */
int sram_read_test(u32 *data, u32 array_addr, int size){
int i;
u32 x;
for(i =0; i < size; i++){
x = IO_READ(array_addr + (i <<2));
if(x != data[i]){
return FAIL;
}
}
return PASS;
}
int accChk (u32 addr, u32 rwbits, int expect_fail)
{
int ret;
u32 org, now, mod;
org = IO_READ(addr);
mod = org ^ rwbits;
IO_WRITE(addr,mod);
now = IO_READ(addr);
if( (mod & rwbits) != (now & rwbits) )
ret = expect_fail ? PASS : FAIL;
else
ret = expect_fail ? FAIL : PASS;
return ret;
}
int checkAes(){
if(accChk(PI_AES_EKEY_REG, myrand(), TRUE) == FAIL){
return FAIL;
}
if(accChk(PI_AES_INIT_REG, myrand(), TRUE) == FAIL){
return FAIL;
}
if(accChk(PI_AES_CTRL_REG, PI_AES_CTRL_HC, TRUE) == FAIL){
return FAIL;
}
if(accChk(PI_AES_CTRL_REG, PI_AES_CTRL_START, TRUE) == FAIL){
return FAIL;
}
return PASS;
}
int checkFlash(){
if(accChk(PI_FLASH_CTRL_REG, PI_FLASH_CTRL_START, TRUE) == FAIL){
return FAIL;
}
if(accChk(PI_FLASH_ADDR_REG, myrand() & 0x3FFFFFFF, TRUE) == FAIL){
return FAIL;
}
if(accChk(PI_FLASH_CONFIG_REG, PI_FLASH_CONFIG_WR_PROTECT, TRUE) == FAIL){
return FAIL;
}
return PASS;
}
void atbWrite(u32 wordLow,u32 bits9,u32 addrOffset)
{
IO_WRITE(PI_ATBU_REG,bits9);
IO_WRITE(PI_ATB_BUFFER_LO_REG+addrOffset,wordLow);
}
void atbRead(u32 *wordLow,u32 *bits9,u32 addrOffset)
{
u32 addrAligned;
*wordLow = IO_READ(PI_ATB_BUFFER_LO_REG+addrOffset);
/* access to the upper bit of two consecutive entries
* is done with a single read. So, the reads to the
* PI_BUF_ATBU_READ space must be 8-byte aligned.
*/
*bits9 = IO_READ(PI_ATB_BUFFER_HI_REG+PI_ATB_BUFFER_OFFSET+(addrOffset&~7));
if(!(addrOffset&4)){
*bits9 = (*bits9)>>16;
}
*bits9 &= 0x1ff;
}
int checkAtb(int expect_fail){
u32 addrOffset, wordLow_w, bits9_w, wordLow_r, bits9_r;
wordLow_w = myrand();
bits9_w = myrand() & 0x1FF;
addrOffset = (myrand() % PI_ATB_NUM_ENTRIES) * 4;
atbWrite(wordLow_w,bits9_w,addrOffset);
atbRead(&wordLow_r,&bits9_r,addrOffset);
if (wordLow_r != wordLow_w || bits9_r != bits9_w) {
return expect_fail? PASS: FAIL; /* expect FAIL */
}
else{
return expect_fail? FAIL: PASS;
}
}
int checkBufDma(){
if(accChk(PI_DMA_BUFFER_RD_REG, myrand() & 0x3FFFFFFF, TRUE) == FAIL){
return FAIL;
}
if(accChk(PI_DMA_BUFFER_WR_REG, myrand() & 0x3FFFFFFF, TRUE) == FAIL){
return FAIL;
}
return PASS;
}
int checkIDEacc(){
if(accChk(PI_IDE_CONFIG_REG, 0x80000000, TRUE) == FAIL){
return FAIL;
}
return PASS;
}