reset.c
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#include "cpusim.h"
void
passed(void) {
message("test reset passed\n");
DBG_JTAG_PASS("test reset passed\n");
test_postamble();
}
void
failed(const char* code) {
message("test reset failed (");
message(code);
message(")\n");
DBG_JTAG_FAIL(code);
test_postamble();
}
int
main() {
int ri, cfg;
cfg = getcp0reg(C0_CONFIG);
IO_WRITE(PI_IDE0_BASE_REG, getcp0reg(C0_CONFIG));
test_preamble();
cfg &= CONFIG_EC;
cfg >>= 28;
if (!cfg) {
IO_WRITE(INTERNAL_RAM_START, 0x700);
}
ri = IO_READ(INTERNAL_RAM_START);
if (ri == 0x700) { /* default value */
if (cfg != 0) failed("1");
IO_WRITE(INTERNAL_RAM_START, 0x600);
IO_WRITE(MI_CTRL_REG, MI_CTRL_HARD_RESET|MI_CTRL_DIV_MODE_1_5);
} else if (ri == 0x600) {
if (cfg != 1) failed("2");
IO_WRITE(INTERNAL_RAM_START, 0x500);
IO_WRITE(MI_CTRL_REG, MI_CTRL_HARD_RESET|MI_CTRL_DIV_MODE_2);
} else if (ri == 0x500) {
if (cfg != 2) failed("3");
IO_WRITE(INTERNAL_RAM_START, 0x400);
IO_WRITE(MI_CTRL_REG, MI_CTRL_HARD_RESET|MI_CTRL_DIV_MODE_3);
} else if (ri == 0x400) {
if (cfg != 3) failed("4");
IO_WRITE(INTERNAL_RAM_START, 0x300);
IO_WRITE(MI_CTRL_REG, MI_CTRL_HARD_RESET|MI_CTRL_DIV_MODE_1_5);
} else if (ri == 0x300) {
if (cfg != 1) failed("5");
IO_WRITE(INTERNAL_RAM_START, 0x200);
IO_WRITE(MI_CTRL_REG, MI_CTRL_SOFT_RESET|MI_CTRL_DIV_MODE_2);
} else if (ri == 0x200) {
if (cfg != 1) failed("6");
passed();
}
failed("0");
return 0;
}