toplevel.v
1.35 KB
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//
// This module simulates a top-level module to verify tab2vmem
//
`timescale 100 ps / 100 ps
module toplevel;
//
//
//
reg gclk;
reg [11:0] sig_e;
reg sig_b;
wire [7:0] sig_c;
wire sig_d;
wire [3:0] sig_a;
//
// Inputs/Outputs
//
parameter cycle = 160;
//
// Instance modules
//
driver driver(sig_a, sig_b, sig_e, sig_c, sig_d, gclk);
//
// Generate Clock
//
initial
begin
gclk = 1;
end
always
begin
#(cycle/2) gclk = ~gclk;
end
//
// Print input values
//
initial
begin
$monitor("%10d\t", $time,
"sig_a[3:0] = %x\t", sig_a[3:0],
"sig_c[7:0] = %x\t", sig_c[7:0]);
end
//
// Generate some test patterns
//
initial
begin
sig_e[11:0] = 'h555;
sig_b = 'b0;
#cycle
sig_e[11:0] = 'haaa;
sig_b = 'b1;
#cycle
sig_e[11:0] = 'h555;
sig_b = 'b0;
#cycle
sig_e[11:0] = 'haaa;
sig_b = 'b1;
#cycle
sig_e[11:0] = 'h555;
sig_b = 'b1;
#cycle
sig_e[11:0] = 'haaa;
sig_b = 'b1;
#cycle
sig_e[11:0] = 'h555;
sig_b = 'b0;
#cycle
sig_e[11:0] = 'haaa;
sig_b = 'b0;
end
//
// Kill simulation when tabular file read
//
always @(driver.EndVectors)
#cycle $finish;
endmodule