/*************************************************************************
 *                                                                       *
 *               Copyright (C) 1994, Silicon Graphics, Inc.              *
 *                                                                       *
 *  These coded instructions, statements, and computer programs  contain *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and *
 *  are protected by Federal copyright  law.  They  may not be disclosed *
 *  to  third  parties  or copied or duplicated in any form, in whole or *
 *  in part, without the prior written consent of Silicon Graphics, Inc. *
 *                                                                       *
 ************************************************************************/
	
/* aresample.s */
 
#define rs_vstorem(x) vmadm x, vONE, vSHIFT[0]
#define rs_vstoren(x) vmadn x, vONE, vSHIFT[0]

#define	SBASE	2
#define	CBASE	3
#define	PINC	4
#define	PHCNT	5

#define	SBASEb	4
#define	CBASEb	6
#define	PINCb	8
#define	PHCNTb	10

 ########################################################################
 #
 # resample data in dmemin to dmemout using

.name	OutPtr,		$23
.name	loopctl,	$22
.name	count,		$3
.name	state_addr,	$2
.name	dm_state_addr,	$1

.name	vONE,		$v31
.name	vSHIFT,		$v30
.name	vZEROFOUR,	$v29
.name	vONEFIVE,	$v28
.name	vTWOSIX,	$v27
.name	vTHREESEVEN,	$v26
.name	vMULINC,	$v25
.name	vfco,		$v24
.name	vico,		$v23
.name	vica,		$v22

.name	vchparmz,	$v21
.name	vphaddr,	$v20
.name	vdata0,		$v19
.name	vcoef0,		$v18
.name	vdata1,		$v17
.name	vcoef1,		$v16
.name	vdata2,		$v15
.name	vcoef2,		$v14
.name	vdata3,		$v13
.name	vcoef3,		$v12
.name	vout0,		$v11
.name	vout1,		$v10
.name	vout2,		$v9
.name	vout3,		$v8
.name	vout,		$v7

.name flags,		$21
.name inbuffbase,	$20
.name temp,		$4

case_A_RESAMPLE:
	sll	state_addr, aud0, 8
				vxor	vico, vico, vico
	srl	state_addr, state_addr, 8
	addi	state_addr, state_addr, 0
	addi	count, zero, RES_STATE_SIZE8

	srl	flags, aud1, 30
	bgtz	flags, res_dont_init_from_state
	addi	dm_state_addr, scrbase, RES_STATE_BASE

	mfc0	temp, SP_RESERVED
resampleDMAreadwait:
	bne	temp, $0, resampleDMAreadwait
	mfc0	temp, SP_RESERVED

	mfc0	temp, DMA_FULL
resampleDRFull1:
	bne	temp, $0, resampleDRFull1
	mfc0	temp, DMA_FULL

	mtc0	dm_state_addr, DMA_CACHE
	mtc0	state_addr, DMA_DRAM
	mtc0	count, DMA_READ_LENGTH
	
	srl	inbuffbase, aud1, 2
	andi	inbuffbase, inbuffbase, 0x0fff
	addi	inbuffbase, inbuffbase, AL_RESAMPLER_BUFFER_OFFSET
	lqv	vONE[0], AL_CONST_C_ONE(zero)
	lqv	vMULINC[0], AL_CONST_C_MULINC(zero)

	mfc0	$5, DMA_BUSY
RESAMPLEwait1:	
	bne	$5, zero, RESAMPLEwait1
	mfc0	$5, DMA_BUSY

	mtc0	$0, SP_RESERVED

	ldv	vdata0[0], ZMEM_OFFSET(scrbase)

	j	res_after_load
	lsv	vfco[14], FCA_OFFSET(scrbase)	

res_dont_init_from_state:
	srl	inbuffbase, aud1, 2
	andi	inbuffbase, inbuffbase, 0x0fff
	addi	inbuffbase, inbuffbase, AL_RESAMPLER_BUFFER_OFFSET
	lqv	vONE[0], AL_CONST_C_ONE(zero)
				vxor	vdata0, vdata0, vdata0
	lqv	vMULINC[0], AL_CONST_C_MULINC(zero)
				vxor	vfco, vfco, vfco

res_after_load:
	mtc2	inbuffbase, vchparmz[SBASEb]
	addi	temp, zero, RES_TABLE_OFFSET
	mtc2	temp, vchparmz[CBASEb]
				vsub	vMULINC, vMULINC, vONE
	srl	temp, aud1, 14
	mtc2	temp, vchparmz[PINCb]
	addi	temp, zero, RES_PHASE_COUNT
	mtc2	temp, vchparmz[PHCNTb]
				vsub	vMULINC, vMULINC, vONE
	lqv	vSHIFT[0], AL_CONST_C_SHIFT(zero)
	lqv	vZEROFOUR[0], AL_CONST_C_ZEROFOUR(zero)
	lqv	vONEFIVE[0], AL_CONST_C_ONEFIVE(zero)
				vmudm	vfco, vONE, vfco[7]
	lqv	vTWOSIX[0], AL_CONST_C_TWOSIX(zero)
				vmadm	vico, vMULINC, vchparmz[PINC]
	lqv	vTHREESEVEN[0], AL_CONST_C_THREESEVEN(zero)
				rs_vstoren(vfco)
	sdv	vdata0[0], 0(inbuffbase)
	lqv	vMULINC[0], AL_CONST_C_MULINC(zero)
				vmudn	vica, vONE, vchparmz[SBASE]
	addi	loopctl, zero, AL_ALL_COUNTER
				vmadn	vica, vico, vSHIFT[2]
	andi	temp, aud1, 0x0003
				vmudl	vphaddr, vfco, vchparmz[PHCNT]
	beq	temp, zero, resample_swap
	addi	OutPtr, zero, AL_RESAMPLE_IN_0

	addi	OutPtr, zero, AL_RESAMPLE_IN_1

resample_swap:
	ssv	vfco[7], FCA_OFFSET(scrbase)
				vmudn	vphaddr, vphaddr, vSHIFT[4]
	sqv	vica[0], iCAptr0(zero)
				vmadn	vphaddr, vONE, vchparmz[CBASE]
	sqv	vphaddr[0], CPHptr0(zero)

.unname	flags
.unname inbuffbase
.unname	temp


.name	CAptr0,		$21
.name	CAptr2,		$20
.name	CAptr4,		$19
.name	CAptr6,		$18
.name	CAptr8,		$17
.name	CAptr10,	$16
.name	CAptr12,	$15
.name	CAptr14,	$14
.name	PHptr0,		$13
.name	PHptr2,		$12
.name	PHptr4,		$11
.name	PHptr6,		$10
.name	PHptr8,		$9
.name	PHptr10,	$8
.name	PHptr12,	$7
.name	PHptr14,	$6

	lh	CAptr0, iCAptr0(zero)
	lh	PHptr0, CPHptr0(zero)
	lh	CAptr8, iCAptr8(zero)
	lh	PHptr8, CPHptr8(zero)
	lh	CAptr2, iCAptr2(zero)
	lh	PHptr2, CPHptr2(zero)
	lh	CAptr10, iCAptr10(zero)
	lh	PHptr10, CPHptr10(zero)
	lh	CAptr4, iCAptr4(zero)
	lh	PHptr4, CPHptr4(zero)
	lh	CAptr12, iCAptr12(zero)
	lh	PHptr12, CPHptr12(zero)
	lh	CAptr6, iCAptr6(zero)
	lh	PHptr6, CPHptr6(zero)
	lh	CAptr14, iCAptr14(zero)
	lh	PHptr14, CPHptr14(zero)
	
loop:	ldv	vdata0[0], 0(CAptr0)
				vmudm	vfco, vONE, vfco[7]
	ldv	vcoef0[0], 0(PHptr0)
				vmadh	vfco, vONE, vico[7]
	ldv	vdata0[8], 0(CAptr8)
				vmadm	vico, vMULINC, vchparmz[PINC]
	ldv	vcoef0[8], 0(PHptr8)
				rs_vstoren(vfco)
	ldv	vdata1[0], 0(CAptr2)
				vmudn	vica, vONE, vchparmz[SBASE]
	ldv	vcoef1[0], 0(PHptr2)
	ldv	vdata1[8], 0(CAptr10)
				vmadn	vica, vico, vSHIFT[2]	
	ldv	vcoef1[8], 0(PHptr10)
				vmudl	vphaddr, vfco, vchparmz[PHCNT]
	ldv	vdata2[0], 0(CAptr4)
	ldv	vcoef2[0], 0(PHptr4)
	ldv	vdata2[8], 0(CAptr12)
	ldv	vcoef2[8], 0(PHptr12)
				vmudn	vphaddr, vphaddr, vSHIFT[4]
	ldv	vdata3[0], 0(CAptr6)
				vmadn	vphaddr, vONE, vchparmz[CBASE]
	ldv	vcoef3[0], 0(PHptr6)
	ldv	vdata3[8], 0(CAptr14)
				vmulf	vout0, vdata0, vcoef0
	ldv	vcoef3[8], 0(PHptr14)
				vmulf	vout1, vdata1, vcoef1
	sqv	vica[0], iCAptr0(zero)
				vmulf	vout2, vdata2, vcoef2
	sqv	vphaddr[0], CPHptr0(zero)
	lh	CAptr0, iCAptr0(zero)
	lh	PHptr0, CPHptr0(zero)
				vmulf	vout3, vdata3, vcoef3
	lh	CAptr8, iCAptr8(zero)
				vadd	vout0, vout0, vout0[1q]
	lh	PHptr8, CPHptr8(zero)
				vadd	vout1, vout1, vout1[1q]
	lh	CAptr2, iCAptr2(zero)
				vadd	vout2, vout2, vout2[1q]
	lh	PHptr2, CPHptr2(zero)
				vadd	vout3, vout3, vout3[1q]
	lh	CAptr10, iCAptr10(zero)
				vadd	vout0, vout0, vout0[2h]
	lh	PHptr10, CPHptr10(zero)
				vadd	vout1, vout1, vout1[2h]
	lh	CAptr4, iCAptr4(zero)
				vadd	vout2, vout2, vout2[2h]
	lh	PHptr4, CPHptr4(zero)
				vadd	vout3, vout3, vout3[2h]
	lh	CAptr12, iCAptr12(zero)
				vmudn	vout, vZEROFOUR, vout0[0h]
	lh	PHptr12, CPHptr12(zero)
				vmadn	vout, vONEFIVE, vout1[0h]
	lh	CAptr6, iCAptr6(zero)
				vmadn	vout, vTWOSIX, vout2[0h]
	lh	PHptr6, CPHptr6(zero)
				vmadn	vout, vTHREESEVEN, vout3[0h]
	lh	CAptr14, iCAptr14(zero)
	lh	PHptr14, CPHptr14(zero)
	addi	loopctl, loopctl, -16
	blez	loopctl, fini
	sqv	vout[0], 0(OutPtr)
	j	loop
	addi	OutPtr, OutPtr, 0x10

fini:	ldv	vdata0[0], 0(CAptr0)
	ssv	vfco[0], FCA_OFFSET(scrbase)
	jal	DMAwrite
	sdv	vdata0[0], ZMEM_OFFSET(scrbase)

	addi	dlcount, dlcount, -8

	mfc0	$5, DMA_BUSY
RESAMPLEwait2:	
	bne	$5, zero, RESAMPLEwait2
	mfc0	$5, DMA_BUSY

	j	AudDone
	mtc0	$0, SP_RESERVED

.unname	OutPtr
.unname	loopctl
.unname	CAptr0
.unname	CAptr2
.unname	CAptr4
.unname	CAptr6
.unname	CAptr8
.unname	CAptr10
.unname	CAptr12
.unname	CAptr14
.unname	PHptr0
.unname	PHptr2
.unname	PHptr4
.unname	PHptr6
.unname	PHptr8
.unname	PHptr10
.unname	PHptr12
.unname	PHptr14
.unname	count
.unname	state_addr
.unname	dm_state_addr

.unname	vONE
.unname	vSHIFT
.unname	vZEROFOUR
.unname	vONEFIVE
.unname	vTWOSIX
.unname	vTHREESEVEN
.unname	vMULINC
.unname	vfco
.unname	vico
.unname	vica
.unname	vchparmz
.unname	vphaddr
.unname	vdata0
.unname	vcoef0
.unname	vdata1
.unname	vcoef1
.unname	vdata2
.unname	vcoef2
.unname	vdata3
.unname	vcoef3
.unname	vout0
.unname	vout1
.unname	vout2
.unname	vout3
.unname	vout