/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/

/*
 * File:	su.c
 * Creator:	hsa@sgi.com
 * Create Date:	Tue Feb  8 11:51:11 PST 1994
 *
 * This file is the scalar unit simulator for the RSP simulator.
 *
 */

#include <stdio.h>
#include <math.h>	/* for rand() */
#include "rsp.h"
#include "rspctl.h"
#include "opcode.h"
#include "su.h"
#include "vu.h"
#include "memory.h"
#include "trace_print.h"


/* pipeline stall machinery */
boolean	rsp_SUStalled;

/*
 * RSP Scalar Unit registers. (these can be thought of as the
 * "general-purpose" registers in the R4K architecture, the
 * VU is implemented as COP2 and has it's own registers.
 *
 * The RSP registers are 32-bits. (should they be signed?)
 *
 */

/*
 * holds integer multiply/divide results:
 */
i32	rsp_LO, rsp_HI;

/*
 * General-purpose registers.
 * r0  always holds 0, acts like /dev/null
 * r31 is the default link register for Jump and Link instructions.
 */
i32	rsp_GPR[35];	/* extra for control registers */

void
rsp_SuInit(int init_regs)
{
    int i;

    rsp_SUStalled = FALSE;

    /*
     * If we're not asked to initialize the registers to
     * zero, we randomize them.  Else, we leave them alone
     */
    rsp_GPR[0] = 0;
    if (init_regs) {
	for (i=1; i<35; i++)
	    rsp_GPR[i] = 0;
    } else {
	for (i=1; i<32; i++)
	    rsp_GPR[i] = (u32) rand() << 16 | rand();
	for (i=32; i<35; i++)
	    rsp_GPR[i] = rand() & 0xFFFF;
    }
}

/*
 * answers query
 */
boolean
rsp_SUIsStalled(void)
{
    return(rsp_SUStalled);
}

/*
 * The following routines implement the SU instructions. They
 * are grouped according to instruction "type".
 */

/*
 * J, JAL, BEQ, BNE, BLEZ, BGTZ
 */
void
rsp_SuRegularJump(u32 inst)
{
    boolean	tbool;
    int		opKey, rs, rt;
    u32		target, new_pc;
    i16		offset;
    i32		ti32;

    opKey = ExtractOpcode(inst);

    offset = ExtractBits(inst, 15, 0);
    ti32 = offset;
    ti32 <<= 2;
    new_pc = (u32) (((i32) (rsp_programCounter+4)) + ti32);
    new_pc &= 0xffc;

    switch (opKey) {
      case rsp_JAL:
	rsp_GPR[31] = (rsp_programCounter+8) & 0xffc;
        traceSU(31, rsp_GPR[31], rsp_programCounter);
	/* fall through, do the same work as rsp_J */

      case rsp_J:
	target = ExtractBits(inst, 25, 0);
	target <<= 2;
	target &= 0xffc;
	new_pc = ((rsp_programCounter+4) & 0xf0000000) | target;
	rsp_PCSet(new_pc, 1);
	break;

      case rsp_BEQ:
	rs = ExtractBits(inst, 25, 21);
	rt = ExtractBits(inst, 20, 16);
	if (rsp_GPR[rs] == rsp_GPR[rt]) {
	    rsp_PCSet(new_pc, 1);
	}
	break;

      case rsp_BNE:
	rs = ExtractBits(inst, 25, 21);
	rt = ExtractBits(inst, 20, 16);
	if (rsp_GPR[rs] != rsp_GPR[rt]) {
	    rsp_PCSet(new_pc, 1);
	}
	break;

      case rsp_BLEZ:
	rs = ExtractBits(inst, 25, 21);
	if (rsp_GPR[rs] <= 0) {
	    rsp_PCSet(new_pc, 1);
	}
	break;

      case rsp_BGTZ:
	rs = ExtractBits(inst, 25, 21);
	if (rsp_GPR[rs] > 0) {
	    rsp_PCSet(new_pc, 1);
	}
	break;
    }
}

/*
 * ADDI, ADDIU, SLTI, SLTIU, ANDI, ORI, XORI, LUI
 */
void
rsp_SuRegularArith(u32 inst)
{
    int	opKey, rs, rt;
    i32	immed;
    u32	immedu;
    u32	tmp;

    opKey = ExtractOpcode(inst);

    rs = ExtractBits(inst, 25, 21);
    rt = ExtractBits(inst, 20, 16);
    immed  = (i32) ((i16) ExtractBits(inst, 15, 0));
    immedu = (u32) ((u16) ExtractBits(inst, 15, 0));

    /*
     * what about exceptions?
     */

    switch (opKey) {
      case rsp_ADDI:
      case rsp_ADDIU:
	rsp_GPR[rt] = rsp_GPR[rs] + immed;
	break;

      case rsp_SLTI:
	if (rsp_GPR[rs] < immed) {
	    rsp_GPR[rt] = 1;
	} else {
	    rsp_GPR[rt] = 0;
	}
	break;

      case rsp_SLTIU:
	if ((u32) rsp_GPR[rs] < (u32) immed) {
	    rsp_GPR[rt] = 1;
	} else {
	    rsp_GPR[rt] = 0;
	}
	break;

      case rsp_ANDI:
	tmp = immedu;	/* zero-extend */
	rsp_GPR[rt] = rsp_GPR[rs] & tmp;
	break;

      case rsp_ORI:
	tmp = immedu;	/* zero-extend */
	rsp_GPR[rt] = rsp_GPR[rs] | tmp;
	break;

      case rsp_XORI:
	tmp = immedu;	/* zero-extend */
	rsp_GPR[rt] = rsp_GPR[rs] ^ tmp;
	break;

      case rsp_LUI:	/* zero-filled */
	rsp_GPR[rt] = immedu << 16;
	break;

    }
    traceSU(rt, rsp_GPR[rt], rsp_programCounter);
}

/*
 * LB, LBU, LH, LHU, LW
 */
void
rsp_SuRegularLoad(u32 inst)
{
    int	opKey, base, rt;
    u32 addr;
    i32	ti32;
    i16	ti16, offset;
    u16	tu16;
    i8	ti8;
    u8	tu8;
    
    opKey = ExtractOpcode(inst);
    base = ExtractBits(inst, 25, 21);
    rt = ExtractBits(inst, 20, 16);
    offset = ExtractBits(inst, 15, 0);
    addr = (u32) (rsp_GPR[base] + offset);

    /*
     * these should be proper DMA fetches...
     */

    switch (opKey) {
      case rsp_LB:
	ti8 = (i8) rsp_MemReadByte(addr,rsp_DCACHE_ACCESS);
	rsp_GPR[rt] = ti8;
	break;

      case rsp_LBU:
	tu8 = (u8) rsp_MemReadByte(addr,rsp_DCACHE_ACCESS);
	rsp_GPR[rt] = tu8;
	break;

      case rsp_LH:
	ti16 = (i16) rsp_MemReadHalf(addr,rsp_DCACHE_ACCESS);
	rsp_GPR[rt] = ti16;
	break;

      case rsp_LHU:
	tu16 = (u16) rsp_MemReadHalf(addr,rsp_DCACHE_ACCESS);
	rsp_GPR[rt] = tu16;
	break;

      case rsp_LW:
	ti32 = (i32) rsp_MemReadWord(addr,rsp_DCACHE_ACCESS);
	rsp_GPR[rt] = ti32;
	break;

      default:
	rsp_eprintf(stderr,"unknown opKey\n");
	break;
    }
    traceSU(rt, rsp_GPR[rt], rsp_programCounter);
}

/*
 * SB, SH, SW
 */
void
rsp_SuRegularStore(u32 inst)
{
    int	opKey, base, rt;
    u32 addr;
    u32	tu32;
    i16	offset;
    u16	tu16;
    u8	tu8;
    i128 trData;
    i128 trMask;
    int i;

    for (i=0; i<16; i++) 
	trData.b[i] = trMask.b[i] = 0;
    
    opKey = ExtractOpcode(inst);
    base = ExtractBits(inst, 25, 21);
    rt = ExtractBits(inst, 20, 16);
    offset = ExtractBits(inst, 15, 0);
    addr = (u32) (rsp_GPR[base] + offset);

    /*
     * these should be proper DMA fetches...
     */

    switch (opKey) {
      case rsp_SB:
	tu8 = (rsp_GPR[rt] & 0x000000ff);
	rsp_MemWriteByte(addr, tu8,rsp_DCACHE_ACCESS);

	trData.b[addr&0xf] = tu8;
	trMask.b[addr&0xf] = 1;
        traceDM(addr,&(trData), &(trMask),rsp_programCounter,1);  
	break;

      case rsp_SH:
	tu16 = (rsp_GPR[rt] & 0x0000ffff);
	rsp_MemWriteHalf(addr, tu16,rsp_DCACHE_ACCESS);

        for (i=0; i<2; i++) {
	 trData.b[(addr+i)&0xf] = (tu16>>((1-i)*8)) & 0xff;
	 trMask.b[(addr+i)&0xf] = 1;
	}
        traceDM(addr,&(trData), &(trMask),rsp_programCounter,2);  
	break;

      case rsp_SW:
	tu32 = rsp_GPR[rt];
	rsp_MemWriteWord(addr, tu32,rsp_DCACHE_ACCESS);

        for (i=0; i<4; i++) {
	 trData.b[(addr+i)&0xf] = (tu32>>((3-i)*8)) & 0xff;
	 trMask.b[(addr+i)&0xf] = 1;
	}
        traceDM(addr,&(trData), &(trMask),rsp_programCounter,4);  
	break;
    }

}

/*
 * LWC2, SWC2
 */
void
rsp_SuRegularCOP2(u32 inst, u32 pc)
{
    int	opKey, base, rt, opcode, elem;
    u32 addr;
    u32	tu32;
    u16	tu16;
    u8	tu8;
    
    opKey = ExtractOpcode(inst);
    base = ExtractBits(inst, 25, 21);
    addr = (u32) rsp_GPR[base];
    rt = ExtractBits(inst, 20, 16);
    opcode = ExtractBits(inst, 15, 11);
    elem = ExtractBits(inst, 10, 7);

    /*
     * these should be proper DMA fetches...
     */
    switch (opKey) {

      case rsp_LWC2:
	rsp_VULoadInstall(inst, pc);
	break;

      case rsp_SWC2:
	rsp_VUStoreInstall(inst, pc);
	break;

    }
}

/*
 * ADD, ADDU, SUB, SUBU, SLT, SLTU, AND, OR, XOR, NOR
 */
void
rsp_SuSpecialArithR(u32 inst)
{
    int	opKey, rs, rt, rd;

    opKey = ExtractBits(inst, 5, 0);
    rs = ExtractBits(inst, 25, 21);
    rt = ExtractBits(inst, 20, 16);
    rd = ExtractBits(inst, 15, 11);

    switch (opKey) {

      case rsp_ADD:
	rsp_GPR[rd] = rsp_GPR[rs] + rsp_GPR[rt];
	break;

      case rsp_ADDU:
	rsp_GPR[rd] = rsp_GPR[rs] + rsp_GPR[rt];
	break;

      case rsp_SUB:
	rsp_GPR[rd] = rsp_GPR[rs] - rsp_GPR[rt];
	break;

      case rsp_SUBU:
	rsp_GPR[rd] = rsp_GPR[rs] - rsp_GPR[rt];
	break;

      case rsp_SLT:
	if (rsp_GPR[rs] < rsp_GPR[rt]) {
	    rsp_GPR[rd] = 1;
	} else {
	    rsp_GPR[rd] = 0;
	}
	break;

      case rsp_SLTU:
	if ((u32) rsp_GPR[rs] < (u32) rsp_GPR[rt]) {
	    rsp_GPR[rd] = 1;
	} else {
	    rsp_GPR[rd] = 0;
	}
	break;

      case rsp_AND:
	rsp_GPR[rd] = rsp_GPR[rs] & rsp_GPR[rt];
	break;

      case rsp_OR:
	rsp_GPR[rd] = rsp_GPR[rs] | rsp_GPR[rt];
	break;

      case rsp_XOR:
	rsp_GPR[rd] = rsp_GPR[rs] ^ rsp_GPR[rt];
	break;

      case rsp_NOR:
	rsp_GPR[rd] = ~(rsp_GPR[rs] | rsp_GPR[rt]);
	break;

    }
    traceSU(rd, rsp_GPR[rd], rsp_programCounter);
}

/*
 * MULT, MULTU, DIV, DIVU, MFHI, MTHI, MFLO, MTLO
 */
void
rsp_SuSpecialArith(u32 inst)
{
    int			opKey, rs, rt, rd;
    long long int	bigtmp;

    opKey = ExtractBits(inst, 5, 0);
    rs = ExtractBits(inst, 25, 21);
    rt = ExtractBits(inst, 20, 16);
    rd = ExtractBits(inst, 15, 11);	/* not used for some */

    switch (opKey) {

      case rsp_MULT:
	bigtmp = rsp_GPR[rs] * rsp_GPR[rt];
	rsp_HI = ((bigtmp & 0xffffffff00000000) >> 32);
	rsp_LO = (bigtmp & 0x00000000ffffffff);
	break;

      case rsp_MULTU:
	bigtmp = (u32) rsp_GPR[rs] * (u32) rsp_GPR[rt];
	rsp_HI = ((bigtmp & 0xffffffff00000000) >> 32);
	rsp_LO = (bigtmp & 0x00000000ffffffff);
	break;

      case rsp_DIV:
	rsp_LO = rsp_GPR[rs] / rsp_GPR[rt];
	rsp_HI = rsp_GPR[rs] % rsp_GPR[rt];
	break;

      case rsp_DIVU:
	rsp_LO = (u32) rsp_GPR[rs] / (u32) rsp_GPR[rt];
	rsp_HI = (u32) rsp_GPR[rs] % (u32) rsp_GPR[rt];
	break;

      case rsp_MFHI:
	rsp_GPR[rd] = rsp_HI;
        traceSU(rd, rsp_GPR[rd], rsp_programCounter);
	break;

      case rsp_MTHI:
	rsp_HI = rsp_GPR[rs];
	break;

      case rsp_MFLO:
	rsp_GPR[rd] = rsp_LO;
        traceSU(rd, rsp_GPR[rd], rsp_programCounter);
	break;

      case rsp_MTLO:
	rsp_LO = rsp_GPR[rs];
	break;

    }
}

/*
 * JR, JALR
 */
void
rsp_SuSpecialJump(u32 inst)
{
    int	opKey, rs, rd;

    opKey = ExtractBits(inst, 5, 0);
    rs = ExtractBits(inst, 25, 21);
    rd = ExtractBits(inst, 15, 11);

    switch (opKey) {

      case rsp_JR:
	rsp_PCSet(rsp_GPR[rs], 1);
	break;

      case rsp_JALR:	/* default rd == 31 */
	rsp_PCSet(rsp_GPR[rs], 1);
	rsp_GPR[rd] = (rsp_programCounter + 8) & 0xffc;
        traceSU(rd, rsp_GPR[rd], rsp_programCounter);
	break;

    }
}

/*
 * BREAK
 */
void
rsp_SuSpecialBreak(u32 inst)
{
    rsp_controlReg = Flag(rsp_controlReg, rsp_CtlHaltMask);
}

/*
 * SLL, SRL, SRA, SLLV, SRLV, SRAV
 */
void
rsp_SuSpecialShift(u32 inst)
{
    int	opKey, rs, rt, rd, sa;

    opKey = ExtractBits(inst, 5, 0);
    rs = ExtractBits(inst, 25, 21);
    rt = ExtractBits(inst, 20, 16);
    rd = ExtractBits(inst, 15, 11);
    sa = ExtractBits(inst, 10, 6);

    switch (opKey) {

      case rsp_SLL:
	rsp_GPR[rd] = rsp_GPR[rt] << sa;
	break;

      case rsp_SRL:
	rsp_GPR[rd] = ((u32) rsp_GPR[rt]) >> sa;
	break;

      case rsp_SRA:
	rsp_GPR[rd] = rsp_GPR[rt] >> sa;
	break;

      case rsp_SLLV:
	rsp_GPR[rd] = rsp_GPR[rt] << (rsp_GPR[rs] & 0x1f);
	break;

      case rsp_SRLV:
	rsp_GPR[rd] = ((u32) rsp_GPR[rt]) >> (rsp_GPR[rs] & 0x1f);
	break;

      case rsp_SRAV:
	rsp_GPR[rd] = rsp_GPR[rt] >> (rsp_GPR[rs] & 0x1f);
	break;

    }
    traceSU(rd, rsp_GPR[rd], rsp_programCounter);
}

/*
 * BLTZ, BGEZ, BLTZAL, BGEZAL
 */
void
rsp_SuRegimmJump(u32 inst)
{
    int	opKey, rs;
    i16	offset;
    i32 newpc;

    opKey = ExtractBits(inst, 20, 16);
    rs = ExtractBits(inst, 25, 21);
    offset = ExtractBits(inst, 15, 0);
    newpc = offset;
    newpc = (rsp_programCounter + 4) + (newpc << 2);

    switch (opKey) {

      case rsp_BLTZ:
	if (rsp_GPR[rs] < 0) {
	    rsp_PCSet(newpc, 1);
	}
	break;

      case rsp_BGEZ:
	if (rsp_GPR[rs] >= 0) {
	    rsp_PCSet(newpc, 1);
	}
	break;

      case rsp_BLTZAL:
	if (rsp_GPR[rs] < 0) {
	    rsp_PCSet(newpc, 1);
	}
	rsp_GPR[31] = (rsp_programCounter + 8) & 0xffc;
        traceSU(31, rsp_GPR[31], rsp_programCounter);
	break;

      case rsp_BGEZAL:
	if (rsp_GPR[rs] >= 0) {
	    rsp_PCSet(newpc, 1);
	}
	rsp_GPR[31] = (rsp_programCounter + 8) & 0xffc;
        traceSU(31, rsp_GPR[31], rsp_programCounter);
	break;

    }
}

/*
 * CP0 Coprocessor instructions are actually SU instructions...
 *
 * Coprocessor 0 in the RSP is used for DMA transfers (what else?).
 * So these registers, etc. are connected to the DMA module.
 * If we ever assign anymore behavior to CP0, we will want to
 * split this out and add another layer...
 */
void
rsp_SuCOP0(u32 inst)
{
    int	opKey, rt, rd;
    i16	offset;
    i32	ti32;
    u32	tu32, new_pc;
    u16	tu16;
    u8	tu8;
    
    opKey = ExtractBits(inst, 25, 21);	/* what kind of op */

    switch (opKey) {

      case 0x00:	/* MFC0 */
	rt = ExtractBits(inst, 20, 16);
	rd = ExtractBits(inst, 15, 11);
	rsp_GPR[rt] = cop0_RegGet(rd);
        traceSU(rt, rsp_GPR[rt], rsp_programCounter);
	break;

      case 0x04:	/* MTC0 */
	rt = ExtractBits(inst, 20, 16);
	rd = ExtractBits(inst, 15, 11);
	cop0_RegSet(rd, rsp_GPR[rt]);
	break;

      case 0x08:	/* BC0T, BC0F */
	opKey = ExtractBits(inst, 20, 16);	/* what kind of branch */
	offset = ExtractBits(inst, 15, 0);
	ti32 = offset;
	ti32 <<= 2;
	new_pc = (u32) (((i32) (rsp_programCounter+4)) + ti32);
	if (opKey) {
	    if (cop0_DmaBusy())	/* CP0 condition line is TRUE */
		rsp_PCSet(new_pc, 1);
	} else {
	    if (!cop0_DmaBusy())/* CP0 condition line is FALSE */
		rsp_PCSet(new_pc, 1);
	}
	break;

    }
}

/*
 * Coprocessor moves are actually SU instructions, but they need to
 * stall and behave like VU ops, so we simulate them that way.
 */
void
rsp_SuCOP2Move(u32 inst, u32 pc)
{
    int	opKey;
    
    opKey = ExtractBits(inst, 25, 21);	/* what kind of move */
    switch (opKey) {
      case 0x00:	/* MF */
      case 0x02:	/* CF */
	rsp_VUMoveFromInstall(inst, pc);
	break;

      case 0x04:	/* MT */
      case 0x06:	/* CT */
	rsp_VUMoveToInstall(inst, pc);
	break;
    }
}

/*
 * actually execute an SU instruction:
 */
void
rsp_SUExec(u32 inst, u32 pc)
{
    int		opKey;

    opKey = ExtractOpcode(inst);
    switch (opKey) {
      case rsp_SPECIAL:
	opKey = ExtractBits(inst, 5, 0);
	if (opKey >= rsp_ADD && opKey <= rsp_SLTU)
	    rsp_SuSpecialArithR(inst);
	else if (opKey >= rsp_MULT && opKey <= rsp_DIVU)
	    rsp_SuSpecialArith(inst);
	else if (opKey >= rsp_JR && opKey <= rsp_JALR)
	    rsp_SuSpecialJump(inst);
	else if (opKey == rsp_BREAK)
	    rsp_SuSpecialBreak(inst);
	else if (opKey >= rsp_SLL && opKey <= rsp_SRAV)
	    rsp_SuSpecialShift(inst);
	break;

      case rsp_REGIMM:
	opKey = ExtractBits(inst, 20, 16);
	if (opKey >= rsp_BLTZ && opKey <= rsp_BGEZAL)
	    rsp_SuRegimmJump(inst);
	break;
	
      case rsp_COP0:	/* MFC0/MTC0 BC0T/BC0F */
	rsp_SuCOP0(inst);
	break;

      case rsp_COP2:	/* MFC2/MTC2 CFC2/CTC2 */
	rsp_SuCOP2Move(inst, pc);
	break;

      default:
	if (opKey >= rsp_J && opKey <= rsp_BGTZ)
	    rsp_SuRegularJump(inst);
	else if (opKey >= rsp_ADDI && opKey <= rsp_LUI)
	    rsp_SuRegularArith(inst);
	else if (opKey >= rsp_LB && opKey <= rsp_LHU)
	    rsp_SuRegularLoad(inst);
	else if (opKey >= rsp_SB && opKey <= rsp_SW)
	    rsp_SuRegularStore(inst);
	else if (opKey >= rsp_LWC2 && opKey <= rsp_SWC2)
	    rsp_SuRegularCOP2(inst, pc);
	break;
    }

    rsp_GPR[0] = 0;   /* simulate $0 which cannot be written to */
}

/***************************************************************************/

/*
 * Debugging operations.
 */

i32
rsp_SuGPRGet(i16 reg)
{
    if (reg == 32) {
	return(rsp_programCounter);
    } else if (reg == 33) {
	return(rsp_controlReg);
    } else if (reg == 34) {
	return(rsp_clock);
    }

    if (reg > 35) {
	rsp_eprintf(stderr,"ERROR : invalid register %d.\n",reg);
	return(0);
    }

    return(rsp_GPR[reg]);
}

i32
rsp_SuGPRSet(i16 reg, i32 value)
{
    if (reg == 32) {
	rsp_programCounter = 0x04001000 + (value & 0xffc);
    } else if (reg == 33) {
	rsp_controlReg = value;
    } else if (reg == 34) {
	rsp_clock = value;
    }

    if (reg > 35) {
	rsp_eprintf(stderr,"ERROR : invalid register %d.\n",reg);
	return(0);
    }

    if (reg == 0) {
	value = 0;
    }

    rsp_GPR[reg] = value;

    return(value);
}