#!/usr/sbin/perl

if ($ENV{"ROOT"}) {
   $ROOT = $ENV{"ROOT"};
  }
else {
  die "ROOT env not set. Plaase set ROOT environment first \n";
  }

$VUREGRES =  $ROOT."/PR/rspsim/vuregre";

$hw2 = 1;
$REGRESSION_DIR = $VUREGRES."/regression2";

if ($ENV{"USE_HW_ROOT"}) {
   $hw2 = 0;
   $REGRESSION_DIR = $VUREGRES."/regression";
  }
#elsif ($ENV{"USE_NEWVU"}) {
#   $REGRESSION_DIR = $VUREGRES."/regression_newvu";
#  }


$SUREGRES =  $ROOT."/PR/rspsim/suregre";
$VUSRC =  $VUREGRES."/src";
$SUSRC =  $SUREGRES."/ready";
$TOOL =   $VUREGRES."/bin";
$RSPASM = $ROOT."/PR/rspasm1201";
$RSPSIM = $ROOT."/PR/rspsim";
$VCSDIR = "/ecad/vcs/vcs_2.2/sgi";


$WORKDIR = `pwd`;
chop($WORKDIR);
$TESTDIR = $WORKDIR."/tests";
$TESTDIR_VU = $WORKDIR."/tests/VU";
$TESTDIR_SU = $WORKDIR."/tests/SU";
$TESTDIR_VUCT = $WORKDIR."/tests/VU/ctrace";
$TESTDIR_SUCT = $WORKDIR."/tests/SU/ctrace";
$DESIGNC = $WORKDIR."/designc"; 


$OPTION_ASM = 1;
$OPTION_ASM_ONLY = 0;
$OPTION_VCSCOMPILE = 1;
$OPTION_VCSRUN = 1;
$OPTION_VU = 0;
$OPTION_GROUP = 0;
$OPTION_SU = 0;
$OPTION_ALL = 1;
$OPTION_GATE = 0;
@PlusArgs = ("+vcs+lic+wait");
$ALL_DIAGS = 1;


while ($#ARGV >= 0) {

    if ($ARGV[0] eq '-noasm') {
      shift (@ARGV);
      $OPTION_ASM = 0;
     }
    elsif ($ARGV[0] eq '-nocompile') {
      shift (@ARGV);
      $OPTION_VCSCOMPILE = 0;
      $OPTION_ASM = 0;
    }
    elsif ($ARGV[0] eq '-gate') {
      shift (@ARGV);
      $OPTION_GATE = 1;
    }
    elsif ($ARGV[0] eq '-SU') {
      shift (@ARGV);
      $OPTION_SU = 1;
      $OPTION_ALL = 0;
    }
    elsif ($ARGV[0] eq '-VU') {
      shift (@ARGV);
      $OPTION_VU = 1;
      $OPTION_ALL = 0;
    }
    elsif ($ARGV[0] eq '-asmonly') {
      shift (@ARGV);
      $OPTION_ASM_ONLY = 1;
    }
    elsif ($ARGV[0] eq '-norun') {
      shift (@ARGV);
      $OPTION_VCSRUN = 0;
    }
    elsif ($ARGV[0] =~ /^\+seed=/) {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
    }
    elsif ($ARGV[0] eq '+random_halt') {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
    }
    elsif ($ARGV[0] eq '+random_idma') {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
    }
    elsif ($ARGV[0] eq '+random_ddma') {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
    }
    elsif ($ARGV[0] eq '+dumpvars') {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
    }
    elsif ($ARGV[0] eq '+single_step') {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
    }
    elsif ($ARGV[0] eq '+ctrace') {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
    }
    elsif ($ARGV[0] =~ /^\+diag=/) {
      ($TEMP,$DIAG) = split(/=/,shift(@ARGV));
      $PlusArgs = push(@PlusArgs,"+diag_".$DIAG);
      $ALL_DIAGS = 0;
    }
    elsif ($ARGV[0] eq '-h') {
      shift (@ARGV);
      print "\n";
      print "\n";
      print "Usage: rsp_regression [options]\n";
      print "\n";
      print "\n";
      print "  options:\n";
      print "  -h           //Help \n";
      print "\n";
      print "  -noasm       //This skips assembler on .s files \n";
      print "\n";
      print "  -nocompile   //This skips VCS compile of your design. Useful if you want to only \n";
      print "                 re-run the previously compiled design \n";
      print "\n";
      print "  -gate        //selects GATE_LEVEL design <default rtl>\n";
      print "\n";
      print "  -VU          //Selects only VU diags <default both SU, VU>\n";
      print "\n";
      print "  -SU          //Selects only SU diags <default both SU, VU>\n";
      print "\n";
      print "  -norun       //This does not execute simulation. Only compiles. \n";
      print "\n";
      print "  +dumpvars    //This causes the \$dumpvars to take effect. default is no dump. \n";
      print "\n";
      print "  +ctrace      //This enables the regi/mem traces to compare with verilog\n";
      print "\n";
      print "  +diag=<diag_name>  //This passes the diag_name as +arg to simulation and \n";
      print "                       simulate only with given diag. You can provide more then \n";
      print "                       one diag name as shown below. \n";
      print "                        +diag=<diag_1> +diag=<diag_2> .... +diag=<diag_3> \n";
      print "\n";
      print "                       If this option is not given, then default is all the \n";
      print "                       diags specified in testssuite. \n";
      print "\n";
      print "                       With this feature, you can compile once with all the \n";
      print "                       diags in testsuite and choose to only run the ones you want. \n";
      print "\n";
      print "  +single_step // Runs diags in single step mode\n";
      print "\n";
      print "  +random_halt //Forces random HALT event during simulation\n";
      print "\n";
      print "  +random_idma //Forces random IMEM DMA event during simulation\n";
      print "\n";
      print "  +random_ddma //Forces random DMEM DMA event during simulation\n";
      print "\n";
      print "  +seed=<seed_number> //Initialize the seed number for random events\n";
      print "\n";
      exit; 
    }
    else {
    die "Illigal option provided \n";
    }

} #while ($#ARGV >= 0)

if ($ALL_DIAGS==1) {
    $PlusArgs = push(@PlusArgs,"+AllDiags");
    }
if ($OPTION_GROUP) {
    $OPTION_VU = 0;
    $OPTION_SU = 0;
    $OPTION_ALL = 0;
    }


if (!(-e $TESTDIR && -d $TESTDIR)) {
  print "Creating the $TESTDIR directory\n";
  mkdir ($TESTDIR,0777)    || die "Cant make $TESTDIR \n";
  }
if (!(-e $TESTDIR_VU && -d $TESTDIR_VU)) {
  print "Creating the $TESTDIR_VU directory\n";
  mkdir ($TESTDIR_VU,0777)    || die "Cant make $TESTDIR_VU \n";
  }
if (!(-e $TESTDIR_SU && -d $TESTDIR_SU)) {
  print "Creating the $TESTDIR_SU directory\n";
  mkdir ($TESTDIR_SU,0777)    || die "Cant make $TESTDIR_SU \n";
  }
if (!(-e $TESTDIR_VUCT && -d $TESTDIR_VUCT)) {
  print "Creating the $TESTDIR_VUCT directory\n";
  mkdir ($TESTDIR_VUCT,0777)    || die "Cant make $TESTDIR_VUCT \n";
  }
if (!(-e $TESTDIR_SUCT && -d $TESTDIR_SUCT)) {
  print "Creating the $TESTDIR_SUCT directory\n";
  mkdir ($TESTDIR_SUCT,0777)    || die "Cant make $TESTDIR_SUCT \n";
  }

if (!(-e $DESIGNC && -d $DESIGNC)) {
  print "Creating the $DESIGNC directory\n";
  mkdir ($DESIGNC,0777) || die "Cant make $DESIGNC \n";
  } 

if (!(-r $REGRESSION_DIR."/rsp_regr_include.v")){
  die "rsp_regr_include.v not found. Please p_tupdate $VUREGRES \n";
  }

if (-r $REGRESSION_DIR."/rsp_regression.makefile") {
    system("cp $REGRESSION_DIR/rsp_regression.makefile Makefile")==0 
       || die " System Call interrupt";
    chmod(0666,Makefile);
  }
else {
  die "can not get rsp_regression.makefile. Please p_tupdate $VUREGRES \n";
  }

if ($OPTION_ASM) {

   if (!(-r "testsuite")){
      print "Getting file $REGRESSION_DIR/testsuite \n";
      system("cp $REGRESSION_DIR/testsuite $WORKDIR")==0
       || die " System Call interrupt";
      chmod(0666,$WORKDIR."/testsuite");
    }

  open(TESTSUITE,"testsuite") || die "Cant open testsuite \n";
  open(TESTSKIPPED,">tests.skipped") || die "Cant open tests.skipped \n";

  $test_num=0;

  while ($_= <TESTSUITE>) {

     split;

     $INTYPE = 0; $STYPE = 0;
     $VUTEST = 0; $SUTEST = 0;

     $TEST_TYPE = $_[0]; #VU,SU
     $TEST =      $_[1]; #test
     $GROUP =     $_[2];


     $GROUP_MATCH = 0;
     if ($GROUP eq $GROUP_STDIN && $OPTION_GROUP) {
	$GROUP_MATCH = 1;
        if  ($TEST_TYPE eq "XX") {
	  $TEST_TYPE="SU";
	  }
	}
      
     if (($TEST_TYPE eq "VU" && ($OPTION_ALL | $OPTION_VU || $GROUP_MATCH)) || 
         ($TEST_TYPE eq "SU" && ($OPTION_ALL | $OPTION_SU || $GROUP_MATCH))
        ) {
	
        if ($TEST_TYPE eq "VU") {
	   $VUTEST = 1;
   	   $TESTNAME_FULL = $ROOT."/PR/".$TEST;
	   $TESTDIR = $TESTDIR_VU;
           open(MAKEFILE,">$TESTDIR/Makefile") || die "Cant open $TESTDIR/Makefile \n";
         }
	else { 
	   $SUTEST = 1; 
	   $TESTNAME_FULL = $ROOT."/PR/".$TEST;
	   $TESTDIR = $TESTDIR_SU;
           open(MAKEFILE,">$TESTDIR/Makefile") || die "Cant open $TESTDIR/Makefile \n";
           chmod(0666,$TESTDIR."/suregre.h");
	  }

	$TEST = `basename $TESTNAME_FULL`;
	chop($TEST);

	print "test is $TEST \n";
	
	($TEST,$FILE_TYPE) = split(/\./,$TEST);

        if ($FILE_TYPE eq "in") { 
	   $INTYPE = 1; 
          }
	else { 
	   $STYPE = 1; 
	  }

	if (-r $TESTNAME_FULL) {

	    chdir ($TESTDIR) || die "Cant go to $TESTDIR \n";
            
	    print MAKEFILE "\n";
	    print MAKEFILE "TARGET1 = $TEST.$FILE_TYPE\n";
	    print MAKEFILE "TARGET2 = $TEST.IMEM\n";
	    print MAKEFILE "TOOL = $TOOL/lst2IMEM $TOOL/dat2DMEM $RSPASM/rspasm $TOOL/d2asm".
		           " $TOOL/trace2ver $TOOL/make_rtsk $RSPSIM/rsp\n";
	    print MAKEFILE "INCLUDE = VU_AVP.h suregre.h\n";
	    print MAKEFILE "\n";
	    print MAKEFILE "\$(TARGET2): $TEST.$FILE_TYPE \$(TOOL) \$(INCLUDE)\n";
	    print MAKEFILE "\ttouch a.out\n";
	    print MAKEFILE "\trm a.out*\n";
	    if ($FILE_TYPE eq "in") {
	           print MAKEFILE "\t$TOOL/d2asm $TEST.in $TEST.s $TEST.inlst\n";
		  }
	    print MAKEFILE "\t$RSPASM/rspasm -b 0 $TEST.s\n";
	    print MAKEFILE "\tmv a.out $TEST.out\n";
	    print MAKEFILE "\tmv a.out.lst $TEST.lst\n";
	    print MAKEFILE "\tmv a.out.dat $TEST.dat\n";
	    if ($TEST_TYPE eq "SU") {
	          print MAKEFILE "\t$TOOL/make_rtsk $TEST 1 0\n";
		  }
            else {
	          print MAKEFILE "\t$TOOL/make_rtsk $TEST 31 0\n";
		  }
	    print MAKEFILE "\t$RSPSIM/rsp -rntz $TEST.rtsk</dev/null> $TEST.simlog \n";
	    print MAKEFILE "\tmv trace_out ctrace/$TEST.ctrace\n";
	    print MAKEFILE "\t$TOOL/cvtdmem $TEST.dat | $TOOL/dat2DMEM > $TEST.DMEM\n";
	    print MAKEFILE "\t(cd ctrace; $TOOL/trace2ver $TEST)\n";
	    print MAKEFILE "\t$TOOL/lst2IMEM $TEST.lst > $TEST.IMEM\n";
	    print MAKEFILE "\n";
	    print MAKEFILE "\$(TARGET1): $TESTNAME_FULL\n";
	    print MAKEFILE "\tcp $TESTNAME_FULL $TEST.$FILE_TYPE\n";
	    print MAKEFILE "\tchmod +w $TEST.$FILE_TYPE\n";
	    print MAKEFILE "\n";
	    print MAKEFILE "\suregre.h: $SUREGRES/csrc/suregre.h \n";
	    print MAKEFILE "\tcp $SUREGRES/csrc/suregre.h suregre.h\n";
	    print MAKEFILE "\tchmod +w suregre.h\n";
	    print MAKEFILE "\n";
	    print MAKEFILE "\VU_AVP.h: $VUREGRES/src/include/VU_AVP.h \n";
	    print MAKEFILE "\tcp $VUREGRES/src/include/VU_AVP.h VU_AVP.h\n";
	    print MAKEFILE "\tchmod +w VU_AVP.h\n";
	    close(MAKEFILE);
		
            if (system("make")==0) {
	       $ARRY0[$test_num] = $TEST_TYPE;
	       $ARRY1[$test_num] = $FILE_TYPE;
	       $ARRY2[$test_num] = $TEST;
	       $test_num++;
	       }
	    else {
	       print "\n\n****ERROR:asm steps: test skipped\n\n";
	       print TESTSKIPPED "$_ skipped due to Error\n";
               system("touch $TESTDIR/$TEST.IMEM")==0 || die "System Interrupt";
               system("rm $TESTDIR/$TEST.IMEM")==0 || die "System Interrupt";
	       }
	 } #if (-r $TESTNAME_FULL)

	chdir ($WORKDIR) || die "Cant go to parent \n";


      }
  } #while

close(TESTSKIPPED);
if (-z $WORKDIR."/tests.skipped") {
   system("rm $WORKDIR/tests.skipped")==0 || die "System Interrupt";
   }    

  if ($test_num==0) {
   die "NO TESTS found in testsuite \n";
   }

  if ($OPTION_ASM_ONLY==1) {
   print "DONE compiling tests \n";
   exit;
   }
  open(OUT,">rsp_tests.v") || die "Cant open rsp_tests.v";
  open(TLIST,">rsp_tests.list") || die "Cant open rsp_tests.list";
  
  $TEMP = $REGRESSION_DIR."/rsp_regr_include.v";
  
  print OUT "\n";
  print OUT "`timescale 1ns / 10ps \n";
  print OUT "\n";
  print OUT "module rsp_tests;\n";
  print OUT "\n";
  print OUT "\n";
  print OUT "`include  \"$TEMP\""; 
  print OUT "\n";
  print OUT "\n";

  for ($i=0; $i<$test_num; $i++) {
     $TEST      = $ARRY2[$i];
     print OUT "reg diag_$TEST;\n";

     print TLIST "$TEST\n";
    }
  print OUT "initial\n";
  print OUT "    begin\n";
  for ($i=0; $i<$test_num; $i++) {
     $TEST      = $ARRY2[$i];
     print OUT "       diag_$TEST=0;\n";
     print OUT "       if (\$test\$plusargs(\"diag_$TEST\"))\n";
     print OUT "           diag_$TEST=1;\n";
     print OUT "\n";
   }
  print OUT "    end\n";
  print OUT "\n";

  print OUT "initial \n";
  print OUT "begin \n";
  print OUT "@(posedge `CLK)";
  print OUT "\n";
  print OUT "\n";
  print OUT "\$fwrite(fp,\"\\n\\n\");\n";
  print OUT "\n";
  print OUT "wait (`Reset_l==1);\n";
  print OUT "@(posedge `CLK);\n";
  print OUT "\n";
  print OUT "\n";
  
  for ($i=0; $i<$test_num; $i++) {
     $TEST_TYPE = $ARRY0[$i];
     $FILE_TYPE = $ARRY1[$i];
     $TEST      = $ARRY2[$i];
     if ($TEST_TYPE eq "VU") {
       $TESTDIR = "tests/VU";
       $test_code = "2'b00";
       }
     else {
       $TESTDIR = "tests/SU";
       $test_code = "2'b01";
       }
     $j = $i+1;
     print OUT "\n";
     print OUT "/*********************************************\n";
     print OUT " * (Test# $j)  Test Name: $TEST \n";
     print OUT " *********************************************/\n";
     print OUT "\n";
     print OUT "if (diag_$TEST || AllDiags) \n";
     print OUT "begin \n";
     print OUT "   \$display(\$time,\" TEST $TEST starts\"); \n";
     print OUT "   \$readmemh(\"$TESTDIR/$TEST.IMEM\",`IMEM); \n";
     print OUT "   \$readmemh(\"$TESTDIR/$TEST.DMEM\",mem); \n";
     print OUT "   if (ctrace) \n";
     print OUT "   begin \n";
     print OUT "     \$readmemh(\"$TESTDIR/ctrace/$TEST.trSU\",`tr.su_mem); \n";
     print OUT "     \$readmemh(\"$TESTDIR/ctrace/$TEST.trVU\",`tr.vu_mem); \n";
     print OUT "     \$readmemh(\"$TESTDIR/ctrace/$TEST.trDM\",`tr.dm_mem); \n";
     print OUT "   end \n";
     print OUT "   rundiag($test_code,\"$TEST.$FILE_TYPE\", 'hfff, 'hfff, 'b10);\n";
     print OUT "   \$display(\$time,\"TEST $TEST ends\"); \n";
     print OUT "end\n";
  }
  print OUT "\n";
  print OUT "\n";
  print OUT "test_report; \n";
  print OUT "\$finish; \n";
  print OUT "\n";
  print OUT "end \n";
  print OUT "\n";
  print OUT "endmodule \n";
  
  close(TESTSUITE);
  close(OUT);

} #if ($OPTION_ASM)  

$SIMV = "simv"; 
$GATE_LEVEL = "";

if ($OPTION_GATE==1) {
  $SIMV = "simv_gate"; 
  $GATE_LEVEL = "GATE_LEVEL";
  }

$HW_TYPE = "on HW2";
if ($hw2==0) {
  $HW_TYPE = "on HW";
  }

if ($OPTION_VCSCOMPILE) {
  print "\n\nVCS Compile in progress\n\n";
  chdir ("$WORKDIR");
  if (-r "designc/$SIMV"){
      system("rm designc/$SIMV")==0 || die "System Interrupt";
    }
 system("make $SIMV")==0 || die "VCS compile system call interupt";
}

if ($OPTION_VCSRUN) {
  chdir ("$WORKDIR");
  print "\n\n Running (RSP_MODULE_LEVEL,$GATE_LEVEL,$HW_TYPE) Simulation\n\n";

  print "plusargs passed to vcs are: @PlusArgs \n";

  system("/bin/csh -c 'setenv LD_LIBRARY_PATH $VCSDIR/lib; ".
   "time designc/$SIMV -q @PlusArgs ' > out")==0
               || die("Interrupt occured, cannot run regression");

  print "SImulation Complete\n";
}