testit
4.06 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
#!/bin/sh
DUMPDIR=${SIMVDIR:-"./"}
TIMELIMIT=1800
MSMON="+mspan_mon +gclock_mon=150"
#TIMELIMIT=1200
#MSMON="+mspan_mon"
#
# Run the C simulation (rdp_c)
#
csim()
{
set -x
echo C sim Test ${1} start `date`
zcat InData/test${1}.${2}.rdram.Z > InData/c_${1}.mem
rdram2rdp InData/c_${1}.mem > InData/c_${1}.rdp
rdp_c -i c_${1} -m c_${1}.mem -e -z
rm InData/c_${1}.mem
echo C sim Test ${1} end `date`
set +x
}
#
# Run the Verilog simulation (iosim & simv.ipc)
#
vsim()
{
set -x
echo V sim Test ${1} start `date`
zcat InData/test${1}.${2}.rdram.Z > InData/v_${1}.rdram
rdramgclr InData/v_${1}
# Using env
SIMV="${SIMVDIR}/simv.ipc -vcd $DUMPDIR/verilog.dump +mmap_rdram=InData/v_${1} +timelimit=${TIMELIMIT} ${MSMON} ${VCS_VERBOSE}"
export SIMV
$WORKAREA/PR/iosim/src/iosim -d 0x41 -f $WORKAREA/PR/iosim/test/rdp.tst -l OutData/test${1}.log
# Old
# $WORKAREA/PR/iosim/src/iosim -d 0x41 -f $WORKAREA/PR/iosim/test/rdp.tst -l OutData/test${1}.log -s ${SIMVDIR}/simv.ipc \"-vcd $DUMPDIR/verilog.dump +mmap_rdram=InData/v_${1} +timelimit=${TIMELIMIT} +mspan_mon ${VCS_VERBOSE}\"
# $WORKAREA/PR/iosim/src/iosim -d 0x41 -f $WORKAREA/PR/iosim/test/rdp.tst -l OutData/test${1}.log -s \"${SIMVDIR}/simv.ipc -vcd $DUMPDIR/verilog.dump +mmap_rdram=InData/v_${1} +timelimit=${TIMELIMIT} +mspan_mon ${VCS_VERBOSE}\"
rdram2image InData/v_${1}
echo V sim Test ${1} end `date`
set +x
}
#
# Compare the image files from C & Verilog runs
#
check_results()
{
iclr OutData/c_${1}_0.rgb
iclr OutData/c_${1}_0.z
iclr OutData/v_${1}_0.rgb
iclr OutData/v_${1}_0.z
cmp -s OutData/c_${1}_0.rgb OutData/v_${1}_0.rgb
if test $? -ne 0 ; then
echo "TEST $1 FAILED, images didn't compare"
IMAGEOK=0
else
IMAGEOK=1
fi
cmp -s OutData/c_${1}_0.z OutData/v_${1}_0.z
if test $? -ne 0 ; then
echo "TEST $1 FAILED, Z images didn't compare"
ZOK=0
else
ZOK=1
fi
cmp -s OutData/c_${1}_0.cvg OutData/v_${1}_0.cvg
if test $? -ne 0 ; then
echo "TEST $1 FAILED, CVG files didn't compare"
else
if [ $IMAGEOK -eq 1 -a $ZOK -eq 1 ] ; then
echo "TEST $1 PASSED, images, Z, & CVG compare"
fi
fi
}
clean_up()
{
rm InData/v_${1}.rdram
}
RUN_ALL=1
RUN_MEM=0
RUN_C=0
RUN_V=0
RUN_I=0
REDUCE=
QUIET=0
while getopts mcvirq a
do
case $a in
m) RUN_MEM=1;RUN_ALL=0;;
c) RUN_C=1;RUN_ALL=0;;
v) RUN_V=1;RUN_ALL=0;;
i) RUN_I=1;RUN_ALL=0;;
r) REDUCE="-r";;
q) QUIET=1;;
\?) echo "Usage: testit <-m> <-c> <-v> <-i> <test list>"
echo " -m Run emulator to generate .rdram file"
echo " -c Run C sim"
echo " -v Run V sim"
echo " -i Run image compare"
echo " -r Reduce viewport"
echo " -q Quiet mode, no mbus mon or verilog.dump"
echo " test list defaults to 001 002 ..."
echo " Running an individual test (w/o -q) will turn on and save verilog.dump"
echo " To run a test in 32 bit mode, add 100 to test # (eg 103)"
exit 2;;
esac
done
shift `expr $OPTIND - 1`
TESTLIST=${@:-"001 002 003 004 005 006 007 101 102 103 104 105 106 010 011 013 014 015 016 017 114 115"}
#TESTLIST=${@:-"001 002 003 004 005 006 007 010 011 013 014 015 016 017"}
if [ $# -ne 0 -a $QUIET -eq 0 ] ; then
VCS_VERBOSE="+mbus_mon +ms_dump"
fi
for TTT in $TESTLIST
do
if [ ${TTT} -ge 100 ] ; then
T=`expr ${TTT} - 100`
TRUECOLOR="-t"
else
T=`expr ${TTT} + 0`
TRUECOLOR=""
fi
if [ ! -x rdpverif ] ; then
make rdpverif
fi
if [ $RUN_ALL -eq 1 -o $RUN_MEM -eq 1 ] ; then
set -x
emulate -n -s -a "${REDUCE} ${TRUECOLOR} -d -a -o ${T} -f ${T} -m -n InData/test${TTT}" rdpverif rom
set +x
fi
if [ $RUN_ALL -eq 1 -o $RUN_C -eq 1 ] ; then
csim $TTT $T
fi
if [ $RUN_ALL -eq 1 -o $RUN_V -eq 1 ] ; then
vsim $TTT $T
if [ $# -ne 0 -a $QUIET -eq 0 ] ; then
echo "Did not clean up v_${TTT}.rdram files"
echo "moved verilog.dump to $DUMPDIR/verilog.dump${TTT}"
mv $DUMPDIR/verilog.dump $DUMPDIR/verilog.dump${TTT}
else
clean_up $TTT
fi
fi
if [ $RUN_ALL -eq 1 -o $RUN_I -eq 1 ] ; then
check_results $TTT
fi
done