if_logic.ss 4.71 KB
/*****************************************************************************/
/* custom variables                                                          */
/*****************************************************************************/
module = "if_logic"
wire_load = 256000
standard_load = 0.01
clock = "clock"
clocks = "clock"
default_input_delay = 1.5
default_output_delay = 13.0
default_pin_delay = 12.0
default_input_load = 40
default_output_load = 40
default_pin_load = 200
default_drive_cell = "dfntnh"
default_drive_pin = "q"
default_period = 16.0
default_max_transition = 1.5
default_uncertainty = 0.5

compile_default_critical_range = 1.0


/*****************************************************************************/
/* set the path and read                                                     */
/*****************************************************************************/
search_path = search_path + "../syn"

read -f edif module + ".edf"
include module + ".cap" > module + ".cap_errors"

current_design = module


/*****************************************************************************/
/* default environment                                                       */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top


/*****************************************************************************/
/* clock constraints                                                         */
/*****************************************************************************/
create_clock clocks -period default_period -waveform { 0.0 default_period / 2 }
set_clock_skew -propagated -uncertainty default_uncertainty clocks
dont_touch_network clocks


/*****************************************************************************/
/* default constraints                                                       */
/*****************************************************************************/
set_dont_touch { ne35hd130d/nt01d* }

set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null

set_drive 0 clocks
set_input_delay 0 clocks

set_max_transition default_max_transition current_design


/*****************************************************************************/
/* custom constraints                                                        */
/*****************************************************************************/
set_driving_cell -cell ni01d5 { *_dbus_read_enable *_dbus_write_enable }
set_load 200 * standard_load { *_cbus_read_enable *_cbus_write_enable }
set_output_delay 10.0 -clock clock { *_cbus_read_enable *_cbus_write_enable }

set_driving_cell -cell nt01d5 { cbus_data dbus_data ebus_data }
set_load 100 * standard_load { cbus_data dbus_data ebus_data }
set_input_delay 10.0 -clock clock { cbus_data dbus_data ebus_data }
set_output_delay 10.0 -clock clock { cbus_data dbus_data ebus_data }

set_load 100 * standard_load { cbus_select cbus_command }
set_output_delay 13.0 -clock clock { cbus_select cbus_command }
set_max_transition 1.0 { cbus_command cbus_select }

set_load 100 * standard_load { dma_start dma_last }

set_load default_pin_load * standard_load \
   { sys_ad_out sys_cmd_out e_valid_l e_ok_l int_l sys_ad_enable_l \
     abus_clock abus_data abus_word pif_clock pif_cmd }
set_output_delay default_pin_delay -clock clock \
   { sys_ad_out sys_cmd_out e_valid_l e_ok_l int_l sys_ad_enable_l \
     abus_clock abus_data abus_word pif_clock pif_cmd }

set_input_delay 4.0 -clock clock { reset_l_0 }


/*****************************************************************************/
/* check                                                                     */
/*****************************************************************************/
link
check_design > module + ".lint"


/*****************************************************************************/
/* compile                                                                   */
/*****************************************************************************/
/* set_fix_hold all_clocks() */
compile -in_place


/*****************************************************************************/
/* write                                                                     */
/*****************************************************************************/
include "report.dc"

write -format edif -hierarchy -o module + ".edf_ipo" module
write -format db -hierarchy -o module + ".db" module

quit