TITLE "$Id: dbg_cnt.tdf,v 1.1.1.1 2002/05/17 06:07:56 blythe Exp $ Copyright (C) 1994, 1995 Silicon Graphics, Inc.";
%*************************************************************************%
%*                                                                       *%
%*          Copyright (C) 1994, 1995 Silicon Graphics, Inc.              *%
%*                                                                       *%
%*  These coded instructions, statements, and computer programs  contain *%
%*  unpublished  proprietary  information of Silicon Graphics, Inc., and *%
%*  are protected by Federal copyright  law.  They  may not be disclosed *%
%*  to  third  parties  or copied or duplicated in any form, in whole or *%
%*  in part, without the prior written consent of Silicon Graphics, Inc. *%
%*                                                                       *%
%*************************************************************************%


subdesign dbg_cnt
(
	sys_clk,			% SysAD clock			%
	sys_reset_l,			% SysAD reset			%
	p_valid_l,			% SysAD processor valid		%
	e_valid_l,			% SysAD rcp valid		%
	e_ok_l,				% SysAD rcp ok			%
	sys_ad_2,			% SysAD address/data bit 2	%
	sys_ad_3,			% SysAD address/data bit 3	%
	sys_ad_31,			% SysAD address/data bit 31	%
	sys_cmd_oe_l			% SysAD command output enable	%
	: INPUT;

	sys_cmd_0,			% SysAD command bit 0		%
	sys_cmd_1,			% SysAD command bit 1		%
	sys_cmd_2,			% SysAD command bit 2		%
	sys_cmd_3,			% SysAD command bit 3		%
	sys_cmd_4 			% SysAD command bit 4		%
	: BIDIR;

	gio_clk,			% GIO clock			%
	gio_reset_l,			% GIO reset			%
	gio_select,			% GIO device selected		%
	gio_read,			% GIO read			%
	gio_ad_2,			% GIO address/data bit 2	%
	gio_ad_3,			% GIO address/data bit 3	%
	gio_masdly 			% GIO master delay		%
	: INPUT;

	gio_slvdly,			% GIO slave delay		%
	gio_slvdly_en_l,		% GIO slave delay driver enable	%

	sys_write_int_l,		% SysAD write interrupt		%
	sys_read_int_l,			% SysAD read interrupt		%
	gio_write_int,			% GIO write interrupt status	%
	gio_read_int,			% GIO read interrupt status	%
	gio_int,			% GIO interrupt			%

	sys_load_l,			% load SysAD data		%
	sys_enable_l,			% enable SysAD data		%
	gio_load_l,			% load GIO data			%
	gio_enable_l			% enable GIO data		%
	: OUTPUT;
)

variable
	% SYS controller %
	target_select,
	target_write,
	target_read,
	target_data_select,
	host_write_interrupt_select,
	host_read_interrupt_select,
	target_write_data,
	% target_read_data, %
	target_enable,
	host_write_interrupt_write,
	host_read_interrupt_write,
	target_write_interrupt,
	target_read_interrupt,

	% GIO controller %
	host_write,
	host_read,
	host_data_select,
	target_write_interrupt_select,
	target_read_interrupt_select,
	host_data_write,
	host_data_read,
	host_enable,
	host_load,
	target_write_interrupt_write,
	target_read_interrupt_write,
	target_interrupt,
	host_write_interrupt,
	host_read_interrupt,
	slave_ready,
	slave_ready_enable,

	clock,
	interrupt_reset_l
	: NODE;

	% SYS controller %
	e_ok_l_reg,
	target_enable_reg,
	target_load_reg,
	target_read_reg,
	target_write_interrupt_reg,
	target_read_interrupt_reg,
	target_interrupt_reg,
	clear_host_write_interrupt_reg,
	clear_host_read_interrupt_reg,

	% GIO controller %
	gio_masdly_reg,
	gio_read_reg,
	gio_ad_2_reg,
	gio_ad_3_reg,
	host_data_read_reg,
	host_enable_reg,
	host_load_reg,
	host_write_interrupt_reg,
	host_read_interrupt_reg,
	slave_ready_reg,
	slave_ready_enable_reg,
	clear_target_write_interrupt_reg,
	clear_target_read_interrupt_reg
	: DFF;

	sys_cmd_0,
	sys_cmd_1,
	sys_cmd_2,
	sys_cmd_3,
	sys_cmd_4 
	: TRI;

begin
	clock = global(sys_clk);
	interrupt_reset_l		= sys_reset_l & gio_reset_l;

	% Target SysAD interface                                        %
	% respond to address 'b1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx  %
	target_select			= !p_valid_l & !e_ok_l & !e_ok_l_reg
					  & !sys_cmd_4 & sys_ad_31;

	target_write			= target_select &  sys_cmd_3;
	target_read			= target_select & !sys_cmd_3;

	target_data_select		= !sys_ad_3 & !sys_ad_2;
	host_write_interrupt_select	=  sys_ad_3 & !sys_ad_2;
	host_read_interrupt_select	=  sys_ad_3 &  sys_ad_2;

	target_write_data		= target_write & target_data_select;
	% target_read_data		= target_read  & target_data_select; %
	host_write_interrupt_write	= target_write
					  & host_write_interrupt_select;
	host_read_interrupt_write	= target_write
					  & host_read_interrupt_select;

	target_enable			= target_read_reg
					  # (target_enable_reg & e_valid_l);

	target_write_interrupt		= target_load_reg
					  # target_write_interrupt_reg;
	target_read_interrupt		= (target_enable_reg & !e_valid_l)
					  # target_read_interrupt_reg;
	target_interrupt		= target_read_interrupt
					  # target_write_interrupt;

	sys_cmd_0			= gnd;
	sys_cmd_1			= gnd;
	sys_cmd_2			= gnd;
	sys_cmd_3			= gnd;
	sys_cmd_4			= vcc;

	sys_cmd_0.oe			= !sys_cmd_oe_l;
	sys_cmd_1.oe			= !sys_cmd_oe_l;
	sys_cmd_2.oe			= !sys_cmd_oe_l;
	sys_cmd_3.oe			= !sys_cmd_oe_l;
	sys_cmd_4.oe			= !sys_cmd_oe_l;

	% Interrupts %
	gio_write_int			= target_write_interrupt_reg;
	gio_read_int			= target_read_interrupt_reg;
	gio_int 			= target_interrupt_reg;

	% Data pipeline control %
	sys_enable_l			= !target_enable_reg;
	sys_load_l			= !target_load_reg;

	% SysAD bus control FFs %
	e_ok_l_reg.clk			= clock;
	e_ok_l_reg.clrn			= sys_reset_l;
	e_ok_l_reg			= e_ok_l;

	target_enable_reg.clk		= clock;
	target_enable_reg.clrn		= sys_reset_l;
	target_enable_reg		= target_enable;

	target_load_reg.clk		= clock;
	target_load_reg.clrn		= sys_reset_l;
	target_load_reg			= target_write_data;

	target_read_reg.clk		= clock;
	target_read_reg.clrn		= sys_reset_l;
	target_read_reg			= target_read;

	% Interrupt control FFs %
	clear_host_write_interrupt_reg.clk	= clock;
	clear_host_write_interrupt_reg.clrn	= interrupt_reset_l;
	clear_host_write_interrupt_reg		= !host_write_interrupt_write;

	clear_host_read_interrupt_reg.clk	= clock;
	clear_host_read_interrupt_reg.clrn	= interrupt_reset_l;
	clear_host_read_interrupt_reg		= !host_read_interrupt_write;

	target_write_interrupt_reg.clk	= clock;
	target_write_interrupt_reg.clrn	= clear_target_write_interrupt_reg;
	target_write_interrupt_reg	= target_write_interrupt;

	target_read_interrupt_reg.clk	= clock;
	target_read_interrupt_reg.clrn	= clear_target_read_interrupt_reg;
	target_read_interrupt_reg	= target_read_interrupt;

	target_interrupt_reg.clk	= clock;
	target_interrupt_reg.clrn	= interrupt_reset_l;
	target_interrupt_reg		= target_interrupt;


	% Target GIO interface                                          %
	% respond to address 'b1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx  %
	host_write			= gio_select & !gio_read_reg;
	host_read			= gio_select &  gio_read_reg;

	host_data_select		= !gio_ad_3_reg & !gio_ad_2_reg;
	target_write_interrupt_select	=  gio_ad_3_reg & !gio_ad_2_reg;
	target_read_interrupt_select	=  gio_ad_3_reg &  gio_ad_2_reg;

	host_data_write			= host_write & host_data_select;
	host_data_read			= host_read  & host_data_select;
	target_write_interrupt_write	= host_write
					  & target_write_interrupt_select;
	target_read_interrupt_write	= host_write
					  & target_read_interrupt_select;

	host_enable			= host_data_read_reg
					  # (host_enable_reg & gio_masdly);
	host_load			= host_data_write
					  # (host_load_reg & gio_masdly);

	host_write_interrupt		= (host_load_reg & !gio_masdly)
					  # host_write_interrupt_reg;
	host_read_interrupt		= (host_enable_reg & !gio_masdly)
					  # host_read_interrupt_reg;

	slave_ready			= gio_masdly;
	slave_ready_enable		= gio_select # (slave_ready_enable_reg
						        & gio_masdly_reg);
	gio_slvdly			= !slave_ready_reg;
	gio_slvdly_en_l			= !slave_ready_enable_reg;

	% Interrupts %
	sys_write_int_l			= !host_write_interrupt_reg;
	sys_read_int_l			= !host_read_interrupt_reg;

	% Data pipeline control %
	gio_enable_l			= !host_enable_reg;
	gio_load_l			= !host_load_reg;

	% GIO bus control FFs %
	gio_read_reg.clk = gio_clk;
	gio_read_reg.clrn = gio_reset_l;
	gio_read_reg = gio_read;

	gio_ad_2_reg.clk = gio_clk;
	gio_ad_2_reg.clrn = gio_reset_l;
	gio_ad_2_reg = gio_ad_2;

	gio_ad_3_reg.clk = gio_clk;
	gio_ad_3_reg.clrn = gio_reset_l;
	gio_ad_3_reg = gio_ad_3;

	gio_masdly_reg.clk = gio_clk;
	gio_masdly_reg.clrn = gio_reset_l;
	gio_masdly_reg = gio_masdly;

	host_data_read_reg.clk = gio_clk;
	host_data_read_reg.clrn = gio_reset_l;
	host_data_read_reg = host_data_read;

	host_enable_reg.clk = gio_clk;
	host_enable_reg.clrn = gio_reset_l;
	host_enable_reg = host_enable;

	host_load_reg.clk = gio_clk;
	host_load_reg.clrn = gio_reset_l;
	host_load_reg = host_load;

	slave_ready_reg.clk = gio_clk;
	slave_ready_reg.prn = gio_reset_l;
	slave_ready_reg = slave_ready;

	slave_ready_enable_reg.clk = gio_clk;
	slave_ready_enable_reg.prn = gio_reset_l;
	slave_ready_enable_reg = slave_ready_enable;

	% Interrupt control FFs %
	clear_target_write_interrupt_reg.clk = gio_clk;
	clear_target_write_interrupt_reg.clrn = interrupt_reset_l;
	clear_target_write_interrupt_reg = !target_write_interrupt_write;

	clear_target_read_interrupt_reg.clk = gio_clk;
	clear_target_read_interrupt_reg.clrn = interrupt_reset_l;
	clear_target_read_interrupt_reg = !target_read_interrupt_write;

	host_write_interrupt_reg.clk = gio_clk;
	host_write_interrupt_reg.clrn = clear_host_write_interrupt_reg;
	host_write_interrupt_reg = host_write_interrupt;

	host_read_interrupt_reg.clk = gio_clk;
	host_read_interrupt_reg.clrn = clear_host_read_interrupt_reg;
	host_read_interrupt_reg = host_read_interrupt;

end;