dramcntl.tdf
18.8 KB
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TITLE "$Id: dramcntl.tdf,v 1.1.1.1 2002/05/17 06:07:56 blythe Exp $ Copyright (C) 1994, 1995 Silicon Graphics, Inc.";
%*************************************************************************%
%* *%
%* Copyright (C) 1994, 1995 Silicon Graphics, Inc. *%
%* *%
%* These coded instructions, statements, and computer programs contain *%
%* unpublished proprietary information of Silicon Graphics, Inc., and *%
%* are protected by Federal copyright law. They may not be disclosed *%
%* to third parties or copied or duplicated in any form, in whole or *%
%* in part, without the prior written consent of Silicon Graphics, Inc. *%
%* *%
%*************************************************************************%
INCLUDE "rcpproto.inc";
function dr_state
(
clock, rstB, rst_d, gio_ras_state, gio_start, gio_rd, gio_halfcnt, refresh_inc,
block_access, cart_enable, cart_wr, cart_rd, cart_rd_d, cart_banksel
)
returns
(
rasB, casB, weB, oeB, dr_cntl[2..0], gio_start_ack, gio_latch, gio_output
);
subdesign dramcntl
(
%gio%
gio_clk, % clock from gio bus (33mhz) %
gio_clk2, % freq doubled, phase locked version of gio_clk %
gio_rstB, % reset from gio bus %
gio_read, % read/writeB/preempt control from gio bus %
gio_masdly, % master delay signal from gio bus %
gio_ad[2], % address bit from gio bus, used to capture byte count %
gio_vadr_in, % from gio_cntl pal, indicates valid slot 0 gio address %
local_adh[20], % address/data bus from gio interface transceiver %
local_ad[11..9], % address/data bus from gio interface transceiver %
local_adl[3..1] % address/data bus from gio interface transceiver %
: INPUT;
local_slvdly, % slvdly signal to be buffered to the gio bus %
slvdlyoeB, gio_int,
% control for gio dram data transceiver %
drlehB, drlelB, droehB, droelB, gio_dataleB, gio_dataoeB,
% control for gio address/control transceiver %
gio_adrleB, gio_regoeB, local_regleB, local_regoeB, local_adroeB,
gio_cntl[2..0] % control for gio bus transactions %
: OUTPUT;
%ad16 (cart)%
ad16_aleh, % cartridge address latch enable (high 16 bits) %
ad16_alel, % cartridge address latch enable (low 16 bits) %
ad16_wrB, % cartridge data write control %
ad16_rdB, % cartridge data read control %
ad16_adh[12..10], % cartridge address-data bus %
ad16_ad[3..1] % cartridge address-data bus %
: INPUT;
cart_cntl[2..0], % control for cartridge bus transactions %
ad16_oe0B, % output enable for cartridge-dram0 data bus (quick-switch) %
ad16_oe1B, % output enable for cartridge-dram1 data bus (quick-switch) %
cart_oeB, % output enable for cartridge register data %
cart_int,
force_rst, force_nmi
: OUTPUT;
%dram%
dr0_cntl[2..0], dr1_cntl[2..0],
dr_rasB[1..0], % ras for odd and even dram banks %
dr_casB[1..0], % cas for odd and even dram banks %
dr_weB[1..0], % write enable for odd and even dram banks %
dr_oeB[1..0] % output enable for odd and even dram banks %
: OUTPUT;
)
variable
clock, dr_rasB[1..0], raw0casB, raw1casB, dr_casB[1..0],
dr_weB[1..0], raw0oeB, raw1oeB, dr_oeB[1..0],
dr0_cntl[2..0], dr1_cntl[2..0],
gio_start_ack0, gio_start_ack1,
gio_latch0, gio_latch1, gio_output0, gio_output1,
cart_oeB, ad16_oe0B, ad16_oe1B
: node;
gio_ff, gio_ff_d, gio_p2, % flipflops to select gio phase2 %
gio_rst_d, gio_halfcnt, giod_vadr, force_gio, gio_adrleB, inc_adr,
gio_ack_start, cart_alel1, cart_alel2, cart_alel3, cart_aleh1,
cart_aleh2, cart_aleh3, cart_wr1, cart_wr2, cart_wr3, cart_rd1,
cart_rd2, cart_rd3, cart_adr[3..1], cart_cntl[2..0], cart_enable,
rfsh_carry, rfsh_cnt[9..0], refresh_inc[1..0], dr_noaccess[1..0],
gio_ras0, gio_ras1, gio_start0, gio_start1, gio_adr[3..1],
% OUTPUTS %
drlehB, drlelB, droehB, droelB, gio_cntl[2..0],
gio_int_clr, gio_int_set, gio_int, cart_int_clr, cart_int_set, cart_int
: dff;
% registered copies of bus controls %
giod_read, gio_rd, giod_masdly, gio_size, gio_pend,
kill_busy, gio_busy, gio_regsel, pre_regoe, pre_dataoe, gio_select[11..9],
gio_active, slvdlyoeB, local_slvdly, gio_dataleB, force_rst, force_nmi,
gio_dataoeB, % control for gio dram data transceiver %
local_regleB, gio_regoeB, % control for gio address/control transceiver %
cart_selramB, cart_selreg, cart_sello[11..10],
local_regoeB, local_adroeB, local_adroe_d
: dffe;
cart_banksel : latch;
begin
clock = global(gio_clk2); % 66 MHz clock %
gio_rst_d.clk = clock;
gio_rst_d = !gio_rstB;
%############ gio bus control ##########################%
% 3 ff used to id phase 2 of the gio bus %
gio_ff.clk = gio_clk;
gio_ff.clrn = gio_rstB;
gio_ff = !gio_ff;
gio_ff_d.clk = clock;
gio_ff_d = gio_ff;
gio_p2.clk = clock;
gio_p2 = gio_ff $ gio_ff_d;
giod_masdly.clk = clock;
giod_masdly.ena = gio_p2;
giod_masdly = gio_masdly;
% address space to be accessed by gio transaction
* gio_adr[11..9] (gio_adr[20] == 0)
* 0 product id register 32 bits (r)
* 2 control register 16 bits (w)
* 4 cart interrupt register (write sets cart interrupt) 32 bits (r/w)
* 5 page address (bits 23..20 for dram accesses) 32 bits (r/w)
* 6 gio interrupt register (read clears gio interrupt) 32 bits (r)
* 7 gio control register (same data as gio interrupt register) 32 bits (r)
* (gio_adr[20] == 1)
* dram access (r/w) (1MB pages (w/ page address))
%
gio_select[].clk = clock;
gio_select[].ena = (gio_cntl[] == GIO_VADR);
gio_select[] = local_ad[11..9];
% state bit to indicate that an internal register access is in progress
* canceled by preemption or end of cycle
%
gio_regsel.clk = clock;
gio_regsel.clrn = gio_rstB;
gio_regsel.ena = gio_p2;
gio_regsel = ((gio_cntl[] == GIO_VADR) & !local_adh[20])
# (gio_regsel & !gio_read & !slvdlyoeB);
gio_adr[].clk = clock;
if (gio_cntl[] == GIO_VADR) then gio_adr[] = local_adl[3..1];
elsif (inc_adr) then gio_adr[] = gio_adr[] + 1;
else gio_adr[] = gio_adr[];
end if;
gio_active.clk = clock;
gio_active.clrn = gio_rstB;
gio_active.ena = gio_p2;
gio_active = gio_vadr_in # (gio_active & local_slvdly & !gio_read);
slvdlyoeB.clk = clock;
slvdlyoeB.prn = gio_rstB;
slvdlyoeB.ena = gio_p2;
!slvdlyoeB = gio_vadr_in # (!slvdlyoeB & (!local_slvdly # gio_active));
local_slvdly.clk = clock;
local_slvdly.prn = gio_rstB;
local_slvdly.ena = gio_p2;
!local_slvdly = !gio_read
& ((!local_slvdly & giod_masdly) # !local_regleB
# (!gio_halfcnt & !gio_adrleB & (!drlehB # !drlelB))
# (!giod_read & (gio_cntl[] == GIO_VADR)));
% state bit to indicate that a dram access is in progress
* canceled by preemption for writes only
%
gio_busy.clk = clock;
gio_busy.ena = gio_p2;
gio_busy = ((gio_cntl[] == GIO_VADR) & local_adh[20])
# (gio_busy & !kill_busy
& (gio_halfcnt # (drlehB & drlelB & droehB & droelB)));
gio_pend.clk = clock;
gio_pend.ena = gio_p2;
gio_pend = ((gio_cntl[] == GIO_VADR) & local_adh[20])
# (gio_pend & !kill_busy & !gio_ack_start);
kill_busy.clk = clock;
kill_busy.ena = gio_p2;
kill_busy = gio_read & !gio_dataleB;
gio_cntl[].clk = clock;
if (!gio_p2 & !gio_busy & (gio_adrleB # gio_vadr_in)) then
gio_cntl[] = GIO_VADR;
elsif (!gio_p2 & !gio_rd & gio_regsel & !giod_masdly) then
if (gio_select[11..9] == 5) then gio_cntl[] = WR_GIO_PAGE;
elsif (gio_select[11..9] == 4) then gio_cntl[] = WR_CART_INT;
else gio_cntl[] = GIO_IDLE;
end if;
elsif (!gio_p2 & gio_rd & gio_regsel & giod_vadr) then
if (gio_select[11..9] == 5) then gio_cntl[] = RD_GIO_PAGE;
elsif (gio_select[11..9] == 4) then gio_cntl[] = GRD_CART_INT;
elsif (gio_select[11..9] == 6) then gio_cntl[] = GRD_GIO_INT;
elsif (gio_select[11..9] == 7) then gio_cntl[] = GRD_GIO_INT;
else gio_cntl[] = RD_GIO_ID;
end if;
else gio_cntl[] = GIO_IDLE;
end if;
% read of interrupt register %
% what about preemption??? %
gio_int_clr.clk = clock;
gio_int_clr = !gio_p2 & gio_rd & gio_regsel & giod_vadr
& (gio_select[11..9] == 6);
cart_int_set.clk = clock;
cart_int_set = !gio_p2 & !gio_rd & gio_regsel & !giod_masdly
& (gio_select[11..9] == 4);
cart_int.clk = clock;
cart_int.clrn = gio_rstB;
cart_int = !cart_int_clr & !force_rst & (cart_int # cart_int_set);
force_rst.clk = clock;
force_rst.prn = gio_rstB;
force_nmi.clk = clock;
force_nmi.clrn = gio_rstB;
if (!gio_p2 & !gio_rd & gio_regsel & !giod_masdly & (gio_select[] == 2)) then
force_rst = local_adl[1];
force_nmi = local_adl[2];
else
force_rst = force_rst;
force_nmi = force_nmi;
end if;
%###### gio addresses, control, and register data writes #########%
force_gio.clk = clock;
force_gio.clrn = gio_rstB;
force_gio = (cart_aleh2 & !cart_aleh3 & gio_pend) % page breaks %
# (force_gio & !gio_ack_start);
gio_ras0.clk = clock;
gio_ras0 = ((gio_cntl[] == GIO_VADR) & local_adh[20] & !local_adl[3]
& cart_aleh2 & !cart_alel2)
# (cart_aleh2 & !cart_aleh3 & !gio_adr[3] & gio_pend);
gio_start0.clk = clock;
gio_start0.clrn = gio_rstB;
gio_start0 = ((cart_aleh3 & !cart_alel2) # force_gio) & gio_busy
& ((gio_ras0 & gio_dataleB) # (gio_start0 & !gio_ack_start)
# (!gio_adr[3] & !gio_dataleB & !gio_masdly));
gio_ras1.clk = clock;
gio_ras1 = ((gio_cntl[] == GIO_VADR) & local_adh[20] & local_adl[3]
& cart_aleh2 & !cart_alel2)
# (cart_aleh2 & !cart_aleh3 & gio_adr[3] & gio_pend);
gio_start1.clk = clock;
gio_start1.clrn = gio_rstB;
gio_start1 = ((cart_aleh3 & !cart_alel2) # force_gio) & gio_busy
& ((gio_ras1 & gio_dataleB) # (gio_start1 & !gio_ack_start)
# (gio_adr[3] & !gio_dataleB & !gio_masdly));
% stores next address in external register until current address is freed %
% latch addresses and register data from gio bus %
gio_adrleB.clk = clock;
gio_adrleB.prn = gio_rstB;
!gio_adrleB = gio_rstB & ((!gio_vadr_in & !gio_adrleB)
# !gio_busy # (gio_read & gio_p2));
% latch gio_read from gio bus (same timing as external address latch) %
giod_read.clk = clock;
giod_read.ena = gio_p2 & !gio_adrleB;
giod_read = gio_read;
% latch read/writeB for current cycle (same timing as internal address) %
gio_rd.clk = clock;
gio_rd.ena = (gio_cntl[] == GIO_VADR);
gio_rd = giod_read;
% gio_size, bit 2 from byte count: 1 -> 32 bits, 0 -> 16bits %
gio_size.clk = clock;
gio_size.ena = gio_vadr_in & gio_p2;
gio_size = gio_ad[2];
% delay latching of gio_halfcnt by 1 cycle %
giod_vadr.clk = clock;
giod_vadr = (gio_cntl[] == GIO_VADR);
gio_halfcnt.clk = clock;
if (giod_vadr) then gio_halfcnt = gio_size;
elsif (inc_adr) then gio_halfcnt = gnd;
else gio_halfcnt = gio_halfcnt;
end if;
inc_adr.clk = clock;
inc_adr = gio_halfcnt & (!droehB # !drlehB) & !inc_adr;
%###### gio dram data writes #########%
% latch data from gio bus for dram %
gio_dataleB.clk = clock;
gio_dataleB.prn = gio_rstB;
gio_dataleB.ena = gio_p2;
!gio_dataleB = ((gio_cntl[] == GIO_VADR) & local_adh[20] & !giod_read)
# (!gio_dataleB & gio_masdly & !gio_read);
droehB.clk = clock;
!droehB = (gio_output0 # gio_output1) & !gio_adr[1];
droelB.clk = clock;
!droelB = (gio_output0 # gio_output1) & gio_adr[1];
%####### gio dram data reads #########%
% 1 cycle delay for gio_dataoeB signal %
pre_dataoe.clk = clock;
pre_dataoe.ena = gio_p2;
pre_dataoe = gio_vadr_in & giod_read & local_adh[20];
% drive dram data to gio bus %
gio_dataoeB.clk = clock;
gio_dataoeB.prn = gio_rstB;
gio_dataoeB.ena = gio_p2;
!gio_dataoeB = !gio_read
& (pre_dataoe # (!gio_dataoeB & (giod_masdly # local_slvdly)));
drlehB.clk = clock;
!drlehB = (gio_latch0 # gio_latch1) & !gio_adr[1];
drlelB.clk = clock;
!drlelB = (gio_latch0 # gio_latch1) & gio_adr[1];
%####### gio register data reads #########%
% 1 cycle delay for gio_regoeB signal %
pre_regoe.clk = clock;
pre_regoe.ena = gio_p2;
pre_regoe = gio_vadr_in & giod_read & !local_adh[20];
% drive register data to gio bus %
gio_regoeB.clk = clock;
gio_regoeB.prn = gio_rstB;
gio_regoeB.ena = gio_p2;
!gio_regoeB = !gio_read
& (pre_regoe # (!gio_regoeB & (giod_masdly # local_slvdly)));
local_adroeB.clk = clock;
local_adroeB.ena = gio_p2;
local_adroeB.clrn = gio_rstB;
local_adroeB = ((gio_cntl[] == GIO_VADR) & giod_read & !local_adh[20])
# (local_adroeB & (local_adroe_d # !local_regoeB));
local_adroe_d.clk = clock;
local_adroe_d.ena = gio_p2;
local_adroe_d = !local_adroeB;
local_regoeB.clk = clock;
local_regoeB.ena = gio_p2;
!local_regoeB = local_adroeB & local_adroe_d;
local_regleB.clk = clock;
local_regleB.ena = gio_p2;
!local_regleB = local_adroeB & local_adroe_d;
%################# cartridge (ad16) interface ############################%
% syncronization and edge detect for cartridge controls %
cart_alel1.clk = clock;
cart_alel1 = ad16_alel;
cart_alel2.clk = clock;
cart_alel2 = cart_alel1 & !force_rst;
cart_alel3.clk = clock;
cart_alel3 = cart_alel2;
cart_aleh1.clk = clock;
cart_aleh1 = ad16_aleh;
cart_aleh2.clk = clock;
cart_aleh2 = cart_aleh1 # force_rst;
cart_aleh3.clk = clock;
cart_aleh3 = cart_aleh2;
cart_wr1.clk = clock;
cart_wr1 = !ad16_wrB;
cart_wr2.clk = clock;
cart_wr2 = cart_wr1 & !force_rst;
cart_wr3.clk = clock;
cart_wr3 = cart_wr2;
cart_rd1.clk = clock;
cart_rd1 = !ad16_rdB;
cart_rd2.clk = clock;
cart_rd2 = cart_rd1 & !force_rst;
cart_rd3.clk = clock;
cart_rd3 = cart_rd2;
% enable for quick switches to allow cartridge access to dram %
ad16_oe0B = ad16_aleh # force_rst # cart_alel3 # cart_selramB;
ad16_oe1B = ad16_aleh # force_rst # cart_alel3 # cart_selramB;
% enable for altera's to allow cartridge access to registers %
cart_oeB = ad16_aleh # force_rst # ad16_rdB # !cart_selreg;
% address space to be accessed by cart transaction
(cart_adr[27] == 0) dram access (r/w)
cart_adr[11..10] (cart_adr[27] == 1)
0 gio interrupt register (write sets cart interrupt) 16 bits (r/w)
1 gio control register (same data as gio interrupt register) 16 bits (r/w)
2 cart interrupt register (read clears cart interrupt) 16 bits (r)
%
cart_selreg.clk = clock;
cart_selreg.clrn = gio_rstB;
cart_selreg = (ad16_adh[11] & (cart_cntl[] == CART_ALEH))
# (cart_selreg & (cart_alel2 # !cart_aleh2));
% selects dram access from ad16 interface - normally active %
cart_selramB.clk = clock;
cart_selramB.clrn = gio_rstB;
cart_selramB = (ad16_adh[11] & (cart_cntl[] == CART_ALEH))
# (cart_selramB & (cart_alel2 # !cart_aleh2));
cart_sello[].clk = clock;
cart_sello[].ena = (cart_cntl[] == CART_ALEL);
cart_sello[] = ad16_adh[11..10];
cart_adr[].clk = clock;
if ((cart_cntl[] == CART_ALEL) & !cart_rd2 & !cart_wr2) then
cart_adr[] = ad16_ad[3..1];
elsif ((cart_rd2 & !cart_rd3) # (cart_wr2 & !cart_wr3)) then
cart_adr[] = cart_adr[] + 1;
else
cart_adr[] = cart_adr[];
end if;
% used to block cas for cartridge reads %
cart_banksel.ena = ad16_rdB & ad16_wrB;
cart_banksel = cart_adr[3];
cart_cntl[].clk = clock;
if (cart_alel2 & !cart_alel3) then cart_cntl[] = CART_ALEH;
elsif (cart_alel3 & !cart_aleh2 & cart_aleh3) then cart_cntl[] = CART_ALEL;
elsif (cart_alel3 & !cart_aleh3 & (cart_cntl[] == CART_ALEL)) then
cart_cntl[] = CRD_ZERO;
elsif (!cart_alel3 & !cart_aleh3 & !cart_rd2 & cart_rd3 & cart_selreg) then
if (cart_sello[11]) then cart_cntl[] = CRD_CART_INT;
else cart_cntl[] = CRD_GIO_INT;
end if;
elsif (!cart_alel3 & !cart_aleh3 & !cart_wr2 & cart_wr3
& cart_selreg & !cart_sello[11] & (cart_adr[] == 1)) then
cart_cntl[] = WR_GIO_INT;
else cart_cntl[] = CART_IDLE;
end if;
cart_int_clr.clk = clock;
cart_int_clr = !cart_rd2 & cart_rd3 & cart_selreg
& (cart_sello[] == 2) & (cart_adr[] == 1);
gio_int_set.clk = clock;
gio_int_set = (cart_cntl[] == WR_GIO_INT) & !cart_sello[10];
gio_int.clk = clock;
gio_int.clrn = gio_rstB;
% add hack to set gio_int when cart_int should be set to test gio
interrupt handler %
gio_int = !gio_int_clr & !force_rst & (gio_int # gio_int_set);
%################# refresh counter ########################################%
rfsh_cnt[].clk = clock;
if (gio_rst_d & gio_rstB) then rfsh_cnt[] = 0;
else
rfsh_cnt[5..0] = rfsh_cnt[5..0] + 1;
if (rfsh_carry) then
rfsh_cnt[9..6] = rfsh_cnt[9..6] + 1;
else
rfsh_cnt[9..6] = rfsh_cnt[9..6];
end if;
end if;
% delay carry to simplify high terms %
rfsh_carry.clk = clock;
rfsh_carry = (rfsh_cnt[5..0] == 0);
% stagger bank refresh signals %
refresh_inc[].clk = clock;
refresh_inc[0] = rfsh_carry & (rfsh_cnt[9..6] == 0);
refresh_inc[1] = rfsh_carry & (rfsh_cnt[9..6] == 8);
%################# dram interface ########################################%
% hold off accesses at the start of a cartridge cycle %
dr_noaccess[].clk = clock;
dr_noaccess[0] = (cart_alel2 & !cart_selramB) # force_gio
# (!cart_alel2 & cart_alel3 & cart_adr[3] & !cart_selramB)
# (!cart_alel3 & !cart_aleh2 & dr_noaccess[0]
& (dr1_cntl[] != CART_CAS1));
dr_noaccess[1] = (cart_alel2 & !cart_selramB) # force_gio
# (!cart_alel2 & cart_alel3 & !cart_adr[3] & !cart_selramB)
# (!cart_alel3 & !cart_aleh2 & dr_noaccess[1]
& (dr0_cntl[] != CART_CAS1));
cart_enable.clk = clock;
cart_enable = !cart_aleh2 & !cart_alel2 & !cart_selramB;
(dr_rasB[0], raw0casB, dr_weB[0], raw0oeB, dr0_cntl[],
gio_start_ack0, gio_latch0, gio_output0)
= dr_state (clock, gio_rstB, gio_rst_d, gio_ras0, gio_start0, gio_rd,
gio_halfcnt, refresh_inc[0], dr_noaccess[0],
cart_enable, cart_wr2 & !cart_wr3,
cart_rd2, cart_rd3, !cart_adr[3] & !cart_aleh2);
!dr_casB[0] = !raw0casB
# (!cart_selramB & !cart_banksel & !ad16_rdB & !force_rst);
!dr_oeB[0] = !raw0oeB
# (!cart_selramB & !cart_banksel & !ad16_rdB & !force_rst);
(dr_rasB[1], raw1casB, dr_weB[1], raw1oeB, dr1_cntl[],
gio_start_ack1, gio_latch1, gio_output1)
= dr_state (clock, gio_rstB, gio_rst_d, gio_ras1, gio_start1, gio_rd,
gio_halfcnt, refresh_inc[1], dr_noaccess[1],
cart_enable, cart_wr2 & !cart_wr3,
cart_rd2, cart_rd3, cart_adr[3] & !cart_aleh2);
!dr_casB[1] = !raw1casB
# (!cart_selramB & cart_banksel & !ad16_rdB & !force_rst);
!dr_oeB[1] = !raw1oeB
# (!cart_selramB & cart_banksel & !ad16_rdB & !force_rst);
gio_ack_start.clk = clock;
gio_ack_start = gio_start_ack0 # gio_start_ack1
# (gio_ack_start & !gio_p2);
end;