module = csdatamux

/* set up a new search path */
search_path = search_path + "../../inc"


/* read the verilog sources */

read -f verilog ../src/csdatamux.v

current_design = csdatamux

/* compile restrictions 
set_dont_touch { ne35hd130d/nt01d* }
set_dont_use { ne35hd130d/mbnfnq ne35hd130d/mbnfnr }
set_dont_use { ne35hd130d/jk* } */

/* setup operating conditions */

set_operating_conditions NOM
set_wire_load 256000 -mode top

link 

check_design > csdatamux.lint

/* timing/area constraints */

/* inputs */
set_driving_cell -cell dfntnb {cmd[*]}
set_driving_cell -cell dfntnh {delay_state[*]}
set_driving_cell -cell dfntnh {fifo_data[*]}
set_driving_cell -cell nr04d2 {stop_wen}
set_driving_cell -cell dfntnb {texel_size[*]}
set_driving_cell -cell dfntnb {copy_fill}
set_arrival 6.0 {texel_size[*]}
set_arrival 6.0 {copy_fill}

/* outputs */
set_max_delay 8.5 -to {cs_ew_data[*]}
set_max_delay 8.5 -to {cs_tc_data[*]}
set_max_delay 7.0 -to {tile_addr[*]}
set_max_delay 4.0 -to {we_tile_size, we_tile_attr}
set_max_transition 0.8 current_design
set_load 2.00 {cs_ew_data[*]}
set_load 0.50 {cs_tc_data[*]}
set_load 0.50 {tile_addr[*]}
set_load 0.50 {we_tile_size, we_tile_attr}

max_area 1700

/* compile */

set_structure false

compile -map_effort high -ungroup_all

report -reference

report_constraint -all_violators

write -f edif -o csdatamux.edf -hier csdatamux

quit