set_input_delay 8.0 -clock clk {reset_l};
set_input_delay 3.0 -clock clk {halt};
set_input_delay 3.0 -clock clk {single_step};
set_input_delay 2.5 -clock clk {pc_in_wr_en};
set_input_delay 5.0 -clock clk {pc_data_in};
set_input_delay 5.0 -clock clk {dma_dm_to_rd};
set_input_delay 5.0 -clock clk {dma_rd_to_dm};
set_input_delay 3.0 -clock clk {dma_imem_select};
set_input_delay 8.0 -clock clk {branch_or_addr_unbuf};
set_input_delay 1.5 -clock clk {rd_inst};

set_input_delay 14.0 -clock clk {sushvamt};
set_input_delay 10.5 -clock clk {sualu_cout};
set_input_delay 10.0 -clock clk {sualu_ovr};
set_input_delay 11.0 -clock clk {sualumsb};
set_input_delay 2.0 -clock clk {suexasign};
set_input_delay 2.0 -clock clk {suexbsign};
set_input_delay 5.0 -clock clk {suonesdet_z};

set_output_delay -max 9.0 -clock clk {su_inst};
set_output_delay -max 9.0 -clock clk {su_inst6};
set_output_delay -max 9.0 -clock clk {su_inst15};
set_output_delay -max 9.0 -clock clk {surf_ra}; 
set_output_delay -max 9.0 -clock clk {surf_rb}; 
set_output_delay -max 5.1 -clock clk {surdamux};
set_output_delay -max 4.8 -clock clk {surdbmux};
set_output_delay -max 5.8 -clock clk {suimmmux}; 
set_output_delay -max 5.2 -clock clk {suimmlsmux};
set_output_delay -max 5.8 -clock clk {suvulsoffsetmux};
 
set_output_delay -max 2.0 -clock clk {rd_base};  /* *** does not match suotherctl.con */
set_output_delay -max 4.0 -clock clk {ls_drive_rd_base};  /* *** does not match suotherctl.con */
set_output_delay -max 4.0 -clock clk {rd_offset};  /* *** does not match suotherctl.con */
set_output_delay -max 8.0 -clock clk {rd_elem_num};
set_output_delay -max 1.0 -clock clk {vu_rd_ld_dec_k};  /* *** does not match suotherctl.con */
set_output_delay -max 1.0 -clock clk {vu_rd_st_dec_k};  /* *** does not match suotherctl.con */

set_output_delay -max 4.0 -clock clk {set_broke};
remove_output_delay -clock clk {break_inst_debug};

set_output_delay -max 14.0 -clock clk {sualuamux}; 
set_output_delay -max 14.0 -clock clk {sualubmux};
set_output_delay -max 10.0 -clock clk {sushamux};
set_output_delay -max 10.0 -clock clk {sushbmux};
set_output_delay -max 15.0 -clock clk {sudrivels};
set_output_delay -max 8.0 -clock clk {suslten}; 
set_output_delay -max 3.5 -clock clk {susltlt};  /* *** does not match suotherctl.con */ 
set_output_delay -max 8.0 -clock clk {sualuen};
set_output_delay -max 14.0 -clock clk {sualu};
set_output_delay -max 14.0 -clock clk {sualu_cin};
set_output_delay -max 11.15 -clock clk {shiftamt};

set_output_delay -max 14.0 -clock clk {su_ex_store};
set_output_delay -max 14.0 -clock clk {su_ex_load};
set_output_delay -max 14.0 -clock clk {vu_ex_store};
set_output_delay -max 14.0 -clock clk {vu_ex_load};
set_output_delay -max 14.0 -clock clk {ex_mfc2};
set_output_delay -max 14.0 -clock clk {ex_mtc2};
set_output_delay -max 14.0 -clock clk {ex_cfc2};
set_output_delay -max 14.0 -clock clk {ex_su_byte_ls};
set_output_delay -max 14.0 -clock clk {ex_su_half_ls};
set_output_delay -max 14.0 -clock clk {ex_su_uns_ls};
set_output_delay -max 7.0 -clock clk {chip_sel}; 

set_output_delay -max 14.0 -clock clk {df_ls_drive_ls_in_wb};
set_output_delay -max 14.0 -clock clk {df_pass_thru}; 
set_output_delay -max 6.5 -clock clk {branch_or_addr};

set_output_delay -max 5.0 -clock clk {surf_w};
set_output_delay -max 13.5 -clock clk {surf_wen}; 
set_output_delay -max 8.0 -clock clk {suwben}; 

set_output_delay -max 6.0 -clock clk {vu_comp};
set_output_delay -max 2.0 -clock clk {vu_comp_k};
set_output_delay -max 8.0 -clock clk {vu_func};
set_output_delay -max 8.0 -clock clk {vu_elem};
set_output_delay -max 6.0 -clock clk {vs};
set_output_delay -max 8.0 -clock clk {vt};
set_output_delay -max 1.5 -clock clk {vu_rd_store_type_k};
set_output_delay -max 1.5 -clock clk {rd_cfvc0_k};
set_output_delay -max 1.5 -clock clk {rd_cfvc1_k};
set_output_delay -max 1.5 -clock clk {rd_cfvc2_k};

set_output_delay -max 8.0 -clock clk {ex_ctc2_vc0};
set_output_delay -max 8.0 -clock clk {ex_ctc2_vc1};
set_output_delay -max 8.0 -clock clk {ex_ctc2_vc2};

set_output_delay -max 3.0 -clock clk {acc_wr_reg}; 
set_output_delay -max 3.0 -clock clk {acc_wr_en};

set_output_delay -max 6.0 -clock clk {vu_ld_addr};
set_output_delay -max 6.0 -clock clk {vu_st_addr};
set_output_delay -max 6.0 -clock clk {vu_st_xpose_addr};
set_output_delay -max 10.0 -clock clk {store_xpose_rd};
set_output_delay -max 13.0 -clock clk {load_xpose_wb};

set_output_delay -max 14.0 -clock clk {cp0_address};
set_output_delay -max 14.0 -clock clk {cp0_write}; 
set_output_delay -max 10.0 -clock clk {cp0_enable}; 
set_output_delay -max 14.0 -clock clk {ex_mfc0};

set_output_delay -max 13.0 -clock clk {imem_dma_cycle};
remove_output_delay  -clock clk {su_nop_debug};
remove_output_delay  -clock clk {vu_nop_debug};
set_output_delay -max 14.0 -clock clk {link_pc_delay_pc}; 
set_output_delay -max 13.0 -clock clk {pc};
set_output_delay -max 13.0 -clock clk {rd_inst_buf};

set_load 0 su_nop_debug
set_load 0 vu_nop_debug
set_load 0 break_inst_debug

set_driving_cell -cell ni01d5 -pin z {rd_inst};

/*** to sudp ***/
set_load .40 {surf_ra}; 
set_load .40 {surf_rb}; 
set_load .85 {surdamux};
set_load .80 {surdbmux};
set_load .50 {suimmmux}; 
set_load .55 {suimmlsmux}; 
set_load .65 {suvulsoffsetmux};

set_load .40 {surf_w};
set_load .40 {surf_wen}; 
set_load .80 {suwben}; 
 
set_load .5 {su_inst[14]};
set_load .5 {su_inst[13]};
set_load .5 {su_inst[12]};
set_load .5 {su_inst[11]};
set_load .5 {su_inst[10]};
set_load .5 {su_inst[9]};
set_load .5 {su_inst[8]};
set_load .5 {su_inst[7]};
set_load .35 {su_inst[5]};
set_load .35 {su_inst[4]};
set_load .35 {su_inst[3]};
set_load .35 {su_inst[2]};
set_load .35 {su_inst[1]};
set_load .35 {su_inst[0]};
set_load .70 {su_inst6};
set_load .70 {su_inst15};

set_load .40 {sualuamux}; 
set_load .40 {sualubmux};
set_load .30 {sushamux};
set_load .30 {sushbmux};
set_load .90 {sudrivels};
set_load .35 {suslten}; 
set_load .20 {susltlt}; 
set_load .40 {sualuen};
set_load .45 {sualu};
set_load .35 {shiftamt};
set_load .40 {sualu_cin};
set_load .30 {link_pc_delay_pc};

set_load .35 {rd_base};
set_load .35 {ls_drive_rd_base};
set_load .35 {rd_offset};
set_load .35 {rd_elem_num};
set_load .35 {vu_rd_ld_dec_k};
set_load .35 {vu_rd_st_dec_k};

set_load .70 {set_broke};

set_load .45 {su_ex_store};
set_load .45 {su_ex_load};
set_load .45 {vu_ex_store};
set_load .45 {vu_ex_load};
set_load .70 {ex_mfc2};
set_load .70 {ex_mtc2};
set_load .45 {ex_cfc2};
set_load .70 {ex_su_byte_ls};
set_load .70 {ex_su_half_ls};
set_load .70 {ex_su_uns_ls};
set_load .45 {chip_sel};
set_load .45 {df_ls_drive_ls_in_wb};
set_load .70 {df_pass_thru};
set_load .2 {branch_or_addr};
 
set_load 2.3 {vu_comp_k};
set_load 2.3 {vu_comp};
set_load 2.3 {vu_func};
set_load 2.8 {vu_elem};
set_load 2.2 {vs}; 
set_load 1.6 {vt}; 
set_load 1.5 {vu_rd_store_type_k};
set_load 1.8 {rd_cfvc0_k};
set_load 1.8 {rd_cfvc1_k};
set_load 1.8 {rd_cfvc2_k};
set_load 1.9 {ex_ctc2_vc0};
set_load 1.9 {ex_ctc2_vc1};
set_load 1.9 {ex_ctc2_vc2};
set_load 2.0 {acc_wr_reg}; 
set_load 1.2 {acc_wr_en};
set_load 1.4 {vu_ld_addr};
set_load 1.5 {vu_st_addr};
set_load 1.5 {vu_st_xpose_addr};
set_load 1.7 {store_xpose_rd};
set_load 1.2 {load_xpose_wb};

set_load .70 {cp0_address}; 
set_load 1.75 {cp0_write}; 
set_load .40 {cp0_enable}; 
set_load 1.7 {ex_mfc0};
set_load .70 {imem_dma_cycle};
set_load 1.9 {pc};

set_load .7 {rd_inst_buf};

group_path -name non_diff_group -to all_outputs();
group_path -default -to {issue/is_taken_ff/*/*, issue/is_clr_taken_ff/*/*, issue/pc_mux/pc_ff/*/*, set_broke, susltlt, rd_cfvc0_k, rd_cfvc1_k, rd_cfvc2_k, vu_rd_store_type_k, vu_rd_ld_dec_k, vu_rd_st_dec_k, rd_offset, rd_base, surdamux, sudrivels}

group_path -name isff_group -to {issue/is_taken_ff/*/*, issue/is_clr_taken_ff/*/*}
group_path -name pcff_group -to {issue/pc_mux/pc_ff/*/*}
group_path -name su -to { set_broke }
group_path -name vu1 -to { rd_cfvc0_k, rd_cfvc1_k, rd_cfvc2_k, vu_rd_store_type_k }
group_path -name ls -to { vu_rd_ld_dec_k, vu_rd_st_dec_k, rd_offset }
group_path -name slt -to { susltlt }
group_path -name rdamux -to { surdamux }
group_path -name rd_base -to { rd_base }
group_path -name drive_group -to {sudrivels};