////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module:      rcp_test_tssi.v
// description: dumps out rcp tssi file
//
// designer:    Tony DeLaurier
// date:        4/25/95
//
////////////////////////////////////////////////////////////////////////

module rcp_test_tssi();

`define RDRAM0 reality.rdram_0.rdram_near_model_0
`define RDRAM1 reality.rdram_1.rdram_near_model_0
`define RDRAM2 reality.rdram_2.rdram_near_model_0
`define RDRAM3 reality.rdram_3.rdram_near_model_0

  integer tab_file_ptr;		// output file pointer
  integer idx;			// bus bit counter
  integer vector_count;		// vector counter
  reg smp_clk;			// sample clock
  reg dly_clk;			// delay clock
  
  reg bus_ctrl_rac_oe;		// active-high oe for bus_ctrl_rac
  reg bus_data_rac_oe[8:0];	// active-high oe's for bus_data_rac

  reg freeze_vclk;		// freeze_vclk flag

  // delayed signals

  reg BusCtrl0_drive_curr;    
  reg [8:0] BusData0_drive_curr; 

  reg BusCtrl1_drive_curr;    
  reg [8:0] BusData1_drive_curr; 

  reg BusCtrl2_drive_curr;    
  reg [8:0] BusData2_drive_curr; 

  reg BusCtrl3_drive_curr;    
  reg [8:0] BusData3_drive_curr; 

  reg tx_clk_curr;            
  reg v_ref_curr;             
  reg pif_clock_curr;         
  reg clock_curr;             
  reg reset_l_curr;           
  reg test_curr;              
  reg c_ctl_pgm_curr;         
  reg bus_enable_curr;        
  reg bus_ctrl_curr;          
  reg [8:0] bus_data_curr;          
  reg ad16_aleh_curr;         
  reg ad16_alel_curr;         
  reg ad16_read_curr;         
  reg ad16_write_curr;        
  reg [15:0] ad16_data_curr;         
  reg tst_ad16_enable_l_curr; 
  reg pif_rsp_curr;           
  reg pif_cmd_curr;           
  reg abus_data_curr;         
  reg abus_word_curr;         
  reg abus_clock_curr;        
  reg vbus_sync_curr;         
  reg vbus_clock_curr;        
  reg vclk_enable_l_curr;     
  reg [6:0] vbus_data_curr;         
  reg int_curr;               
  reg p_valid_curr;           
  reg e_valid_curr;           
  reg e_ok_curr;              
  reg [31:0] sys_ad_curr;            
  reg sys_ad_enable_l_curr;   
  reg [4:0] sys_cmd_curr;           


  initial vector_count = 0;

  // freeze vclk
  initial 
  begin
    if (!$test$plusargs("freeze_vclk_false") && $test$plusargs("rcp_test_tssi"))
     begin
       wait(`SYSTEM_READY);
       @(posedge reality.vbus_clock);
       $display($time,"  Freezing vclk");
       reality.cg_0.freeze_vclk = 1;
     end
  end

  // define sample clock
  initial
  begin
  
    smp_clk = 0;
    #3.8 smp_clk = 1;
     
    forever
    begin
      #2 smp_clk = ~smp_clk;
    end // forever
  end // initial
  
  // define delay clock
  initial
  begin

    dly_clk = 1;
    #1.9 dly_clk = 0;

    forever
    begin
      #2 dly_clk = ~dly_clk;
    end // forever
  end // initial

  // input write task
  task printInput;
    input value;
  
    if (value === 0)
      $fwrite(tab_file_ptr, "D");
    else if (value === 1)
      $fwrite(tab_file_ptr, "U");
    else
      $fwrite(tab_file_ptr, "D");

  endtask // printInput

  // output write task
  task printOutput;
    input value;
  
    if (vector_count > 100) begin
      if (value === 0)
        $fwrite(tab_file_ptr, "L");
      else if (value === 1)
        $fwrite(tab_file_ptr, "H");
      else
        $fwrite(tab_file_ptr, "X");
    end else 
      $fwrite(tab_file_ptr, "X");

  endtask // printOutput

  // bidir write task
  task printBidir;
    input value;
    input curr_oe;
    input next_oe;
  
    if (((curr_oe === 0) && (next_oe === 1)) || (curr_oe === 1'bx) || (next_oe === 1'bx))
      $fwrite(tab_file_ptr, "Z");
    else begin
      if (curr_oe === 1) // chip driving
      begin
        if (value === 0)
          $fwrite(tab_file_ptr, "L");
        else if (value === 1)
          $fwrite(tab_file_ptr, "H");
        else
          $fwrite(tab_file_ptr, "X");
      end
      else if (curr_oe === 0) // tester driving
      begin
        if (value === 0)
          $fwrite(tab_file_ptr, "D");
        else if (value === 1)
          $fwrite(tab_file_ptr, "U");
        else
          $fwrite(tab_file_ptr, "D");
      end
      else // curr_oe unknown
        $fwrite(tab_file_ptr, "Z");
    end // else

  endtask // printBidir

  // rac bidir write task
  task printRacBidir;
    input value;
    input oe;

    if (oe === 1) // tester not driving
    begin
      if (value === 0)
        $fwrite(tab_file_ptr, "L");
      else if (value === 1)
        $fwrite(tab_file_ptr, "H");
      else
        $fwrite(tab_file_ptr, "X");
    end
    else if (oe === 0) // tester driving
    begin
      if (value === 0)
        $fwrite(tab_file_ptr, "D");
      else if (value === 1)
        $display("ERROR: rdram is driving 1 ????????");
      else
        $fwrite(tab_file_ptr, "D");
    end
    else // oe unknown
      $fwrite(tab_file_ptr, "Z");

  endtask // printRacBidir

initial
  begin
    `ifdef RDRAM_23_PRESENT
	$display("rcp_test_tssi: 8MB SYSTEM Configuration");
    `else
      `ifdef RDRAM_1_PRESENT
	$display("rcp_test_tssi: 4MB SYSTEM Configuration");
      `else
	$display("rcp_test_tssi: 2MB SYSTEM Configuration");
      `endif
    `endif

    BusCtrl0_drive_curr <= 1'b1;
    BusCtrl1_drive_curr <= 1'b1;
    BusCtrl2_drive_curr <= 1'b1;
    BusCtrl3_drive_curr <= 1'b1;

    BusData0_drive_curr <= 9'h1ff;
    BusData1_drive_curr <= 9'h1ff;
    BusData2_drive_curr <= 9'h1ff;
    BusData3_drive_curr <= 9'h1ff;
  end

  // delay all signals of interest by one cycle 
  always @(dly_clk)
  begin

    BusCtrl0_drive_curr    <= `RDRAM0.BusCtrl_drive;
    BusData0_drive_curr[8] <= `RDRAM0.BusData_drive[8];
    BusData0_drive_curr[7] <= `RDRAM0.BusData_drive[7];
    BusData0_drive_curr[6] <= `RDRAM0.BusData_drive[6];
    BusData0_drive_curr[5] <= `RDRAM0.BusData_drive[5];
    BusData0_drive_curr[4] <= `RDRAM0.BusData_drive[4];
    BusData0_drive_curr[3] <= `RDRAM0.BusData_drive[3];
    BusData0_drive_curr[2] <= `RDRAM0.BusData_drive[2];
    BusData0_drive_curr[1] <= `RDRAM0.BusData_drive[1];
    BusData0_drive_curr[0] <= `RDRAM0.BusData_drive[0];

    `ifdef RDRAM_1_PRESENT
       BusCtrl1_drive_curr    <= `RDRAM1.BusCtrl_drive;
       BusData1_drive_curr[8] <= `RDRAM1.BusData_drive[8];
       BusData1_drive_curr[7] <= `RDRAM1.BusData_drive[7];
       BusData1_drive_curr[6] <= `RDRAM1.BusData_drive[6];
       BusData1_drive_curr[5] <= `RDRAM1.BusData_drive[5];
       BusData1_drive_curr[4] <= `RDRAM1.BusData_drive[4];
       BusData1_drive_curr[3] <= `RDRAM1.BusData_drive[3];
       BusData1_drive_curr[2] <= `RDRAM1.BusData_drive[2];
       BusData1_drive_curr[1] <= `RDRAM1.BusData_drive[1];
       BusData1_drive_curr[0] <= `RDRAM1.BusData_drive[0];
    `endif

    `ifdef RDRAM_23_PRESENT
       BusCtrl2_drive_curr    <= `RDRAM2.BusCtrl_drive;
       BusData2_drive_curr[8] <= `RDRAM2.BusData_drive[8];
       BusData2_drive_curr[7] <= `RDRAM2.BusData_drive[7];
       BusData2_drive_curr[6] <= `RDRAM2.BusData_drive[6];
       BusData2_drive_curr[5] <= `RDRAM2.BusData_drive[5];
       BusData2_drive_curr[4] <= `RDRAM2.BusData_drive[4];
       BusData2_drive_curr[3] <= `RDRAM2.BusData_drive[3];
       BusData2_drive_curr[2] <= `RDRAM2.BusData_drive[2];
       BusData2_drive_curr[1] <= `RDRAM2.BusData_drive[1];
       BusData2_drive_curr[0] <= `RDRAM2.BusData_drive[0];

       BusCtrl3_drive_curr    <= `RDRAM3.BusCtrl_drive;
       BusData3_drive_curr[8] <= `RDRAM3.BusData_drive[8];
       BusData3_drive_curr[7] <= `RDRAM3.BusData_drive[7];
       BusData3_drive_curr[6] <= `RDRAM3.BusData_drive[6];
       BusData3_drive_curr[5] <= `RDRAM3.BusData_drive[5];
       BusData3_drive_curr[4] <= `RDRAM3.BusData_drive[4];
       BusData3_drive_curr[3] <= `RDRAM3.BusData_drive[3];
       BusData3_drive_curr[2] <= `RDRAM3.BusData_drive[2];
       BusData3_drive_curr[1] <= `RDRAM3.BusData_drive[1];
       BusData3_drive_curr[0] <= `RDRAM3.BusData_drive[0];
    `endif

    tx_clk_curr            <= reality.tx_clk;
    v_ref_curr             <= reality.v_ref;
    pif_clock_curr         <= reality.pif_clock;
    clock_curr             <= reality.clock;
    reset_l_curr           <= reality.reset_l;
    test_curr              <= reality.test;
    c_ctl_pgm_curr         <= reality.c_ctl_pgm;
    bus_enable_curr        <= reality.bus_enable;
    bus_ctrl_curr          <= reality.bus_ctrl;
    bus_data_curr          <= reality.bus_data;
    ad16_aleh_curr         <= reality.ad16_aleh;
    ad16_alel_curr         <= reality.ad16_alel;
    ad16_read_curr         <= reality.ad16_read;
    ad16_write_curr        <= reality.ad16_write;
    ad16_data_curr         <= reality.ad16_data;
    tst_ad16_enable_l_curr <= reality.rcp_0.tst_ad16_enable_l[0];
    pif_rsp_curr           <= reality.pif_rsp;
    pif_cmd_curr           <= reality.pif_cmd;
    abus_data_curr         <= reality.abus_data;
    abus_word_curr         <= reality.abus_word;
    abus_clock_curr        <= reality.abus_clock;
    vbus_sync_curr         <= reality.vbus_sync;
    vbus_clock_curr        <= reality.vbus_clock;
    vclk_enable_l_curr     <= reality.rcp_0.vclk_enable_l;
    vbus_data_curr         <= reality.vbus_data;
    int_curr               <= reality.int;
    p_valid_curr           <= reality.p_valid;
    e_valid_curr           <= reality.e_valid;
    e_ok_curr              <= reality.e_ok;
    sys_ad_curr            <= reality.sys_ad;
    sys_ad_enable_l_curr   <= reality.rcp_0.sys_ad_enable_l[0];
    sys_cmd_curr           <= reality.sys_cmd;

  end // always

  reg [1:256*8] rcp_tssi_fn;

  initial 
  begin
    if ($test$plusargs("rcp_test_tssi"))
    begin
  
      if ($getstr$plusarg("tssi_name=", rcp_tssi_fn) == 1) 
        tab_file_ptr = $fopen(rcp_tssi_fn);
      else
        tab_file_ptr = $fopen("rcp_test_tssi.slf");
	
      forever @(smp_clk) 
      begin

	$fwrite(tab_file_ptr, "%d.0  ", vector_count * 100);
        vector_count = vector_count + 1;
  	`ifdef RDRAM_23_PRESENT
          bus_ctrl_rac_oe    = BusCtrl0_drive_curr    & BusCtrl1_drive_curr    & BusCtrl2_drive_curr    & BusCtrl3_drive_curr;
          bus_data_rac_oe[8] = BusData0_drive_curr[8] & BusData1_drive_curr[8] & BusData2_drive_curr[8] & BusData3_drive_curr[8];
          bus_data_rac_oe[7] = BusData0_drive_curr[7] & BusData1_drive_curr[7] & BusData2_drive_curr[7] & BusData3_drive_curr[7];
          bus_data_rac_oe[6] = BusData0_drive_curr[6] & BusData1_drive_curr[6] & BusData2_drive_curr[6] & BusData3_drive_curr[6];
          bus_data_rac_oe[5] = BusData0_drive_curr[5] & BusData1_drive_curr[5] & BusData2_drive_curr[5] & BusData3_drive_curr[5];
          bus_data_rac_oe[4] = BusData0_drive_curr[4] & BusData1_drive_curr[4] & BusData2_drive_curr[4] & BusData3_drive_curr[4];
          bus_data_rac_oe[3] = BusData0_drive_curr[3] & BusData1_drive_curr[3] & BusData2_drive_curr[3] & BusData3_drive_curr[3];
          bus_data_rac_oe[2] = BusData0_drive_curr[2] & BusData1_drive_curr[2] & BusData2_drive_curr[2] & BusData3_drive_curr[2];
          bus_data_rac_oe[1] = BusData0_drive_curr[1] & BusData1_drive_curr[1] & BusData2_drive_curr[1] & BusData3_drive_curr[1];
          bus_data_rac_oe[0] = BusData0_drive_curr[0] & BusData1_drive_curr[0] & BusData2_drive_curr[0] & BusData3_drive_curr[0];
	`else
  	  `ifdef RDRAM_1_PRESENT
            bus_ctrl_rac_oe    = BusCtrl0_drive_curr    & BusCtrl1_drive_curr;
            bus_data_rac_oe[8] = BusData0_drive_curr[8] & BusData1_drive_curr[8];
            bus_data_rac_oe[7] = BusData0_drive_curr[7] & BusData1_drive_curr[7];
            bus_data_rac_oe[6] = BusData0_drive_curr[6] & BusData1_drive_curr[6];
            bus_data_rac_oe[5] = BusData0_drive_curr[5] & BusData1_drive_curr[5];
            bus_data_rac_oe[4] = BusData0_drive_curr[4] & BusData1_drive_curr[4];
            bus_data_rac_oe[3] = BusData0_drive_curr[3] & BusData1_drive_curr[3];
            bus_data_rac_oe[2] = BusData0_drive_curr[2] & BusData1_drive_curr[2];
            bus_data_rac_oe[1] = BusData0_drive_curr[1] & BusData1_drive_curr[1];
            bus_data_rac_oe[0] = BusData0_drive_curr[0] & BusData1_drive_curr[0];
	  `else
            bus_ctrl_rac_oe    = BusCtrl0_drive_curr;
            bus_data_rac_oe[8] = BusData0_drive_curr[8];
            bus_data_rac_oe[7] = BusData0_drive_curr[7];
            bus_data_rac_oe[6] = BusData0_drive_curr[6];
            bus_data_rac_oe[5] = BusData0_drive_curr[5];
            bus_data_rac_oe[4] = BusData0_drive_curr[4];
            bus_data_rac_oe[3] = BusData0_drive_curr[3];
            bus_data_rac_oe[2] = BusData0_drive_curr[2];
            bus_data_rac_oe[1] = BusData0_drive_curr[1];
            bus_data_rac_oe[0] = BusData0_drive_curr[0];
	  `endif
	`endif

        printInput(tx_clk_curr);					// tx_clk
        printInput(v_ref_curr);						// v_ref
	if ($test$plusargs("dontcare_outputs_false") || !`SYSTEM_READY) 
        begin
          printOutput(pif_clock_curr);					// pif_clock_pad
          printOutput(clock_curr);					// mclock_pad
        end else begin
	  $fwrite(tab_file_ptr, "X");
	  $fwrite(tab_file_ptr, "X");
        end

        printInput(reset_l_curr);					// reset_l_pad
        printInput(test_curr);						// test_pad
        printInput(c_ctl_pgm_curr);					// c_ctl_pgm
        printOutput(bus_enable_curr);					// bus_enable_rac
	printRacBidir(bus_ctrl_curr, bus_ctrl_rac_oe); 			// bus_ctrl_rac
        for (idx = 0; idx < 9; idx = idx + 1)
          printRacBidir(bus_data_curr[idx], bus_data_rac_oe[idx]);	// bus_data_rac[8:0]
        printOutput(ad16_aleh_curr);					// ad16_aleh_pad
        printOutput(ad16_alel_curr);					// ad16_alel_pad
        printOutput(ad16_read_curr);					// ad16_read_pad
        printOutput(ad16_write_curr);					// ad16_write_pad
        for (idx = 0; idx < 16; idx = idx + 1)
          printBidir(ad16_data_curr[idx], (!tst_ad16_enable_l_curr), (!reality.rcp_0.tst_ad16_enable_l[0]));	// ad16_data_pad[15:0]
        printInput(pif_rsp_curr);					// pif_rsp_pad
        printOutput(pif_cmd_curr);					// pif_cmd_pad
        printOutput(abus_data_curr);					// abus_data_pad
        printOutput(abus_word_curr);					// abus_word_pad
        printOutput(abus_clock_curr);					// abus_clock_pad
        printOutput(vbus_sync_curr);					// vbus_sync_pad
        printBidir(vbus_clock_curr, (!vclk_enable_l_curr), (!reality.rcp_0.vclk_enable_l)); 		// vclk_pad
        for (idx = 0; idx < 7; idx = idx + 1)
          printOutput(vbus_data_curr[idx]);				// vbus_data_pad[6:0]
        printOutput(int_curr);						// int_pad
        printInput(p_valid_curr);					// p_valid_pad
        printOutput(e_valid_curr);					// e_valid_pad
        printOutput(e_ok_curr);						// e_ok_pad
        for (idx = 0; idx < 32; idx = idx + 1)
          printBidir(sys_ad_curr[idx], (!sys_ad_enable_l_curr), (!reality.rcp_0.sys_ad_enable_l[0]));	// sys_ad_pad[31:0]
        for (idx = 0; idx < 5; idx = idx + 1)
          printBidir(sys_cmd_curr[idx], (!sys_ad_enable_l_curr), (!reality.rcp_0.sys_ad_enable_l[0]));	// sys_cmd_pad[4:0]
        printOutput(tx_clk_curr);					// rx_clk

        $fdisplay(tab_file_ptr);

      end // forever
    end // if
  end // initial

endmodule // rcp_test_tssi