iotestcmd.c
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/*************************************************************************
*
* File: iotestcmd.c
*
* This file contains the main test command table.
*
* $Header: /root/leakn64/depot/rf/sw/n64os20l/iosim/src/iotestcmd.c,v 1.2 2002/05/30 05:52:50 whs Exp $
*
*/
#include <stdio.h>
#include "trace.h"
#include "iomap.h"
#include "iotest.h"
/***********************************************************************
* Global definitions
*/
int errorTotal = 0;
int errorCount = 0;
/***********************************************************************
* Global variables
*/
/*
* Test Command Table
* - This is the main command table where each test/task from the
* input file gets executed.
*/
TstCmd TstCmdTbl[] = {
/*
* Test Description Routine RoutineName
* ID
* ===================================================================
*/
{ 0, "Config RDRAM", rdramConfig, "rdramConfig" },
{ 1, "Config PI Domain 1", piConfigDom1, "piConfigDom1" },
{ 2, "Config PI Domain 2", piConfigDom2, "piConfigDom2" },
{ 3, "Config AI", AiTestInit, "AiTestInit" },
{ 5, "W/R RDRAM (1B)", rdramTestSglRw, "rdramTestSglRw" },
{ 6, "W/R RDRAM (2B)", rdramTestSglRw, "rdramTestSglRw" },
{ 7, "W/R RDRAM (3B)", rdramTestSglRw, "rdramTestSglRw" },
{ 8, "W/R RDRAM (4B)", rdramTestSglRw, "rdramTestSglRw" },
{ 9, "W/R RDRAM (2-word)", rdramTestBlkRw, "rdramTestBlkRw" },
{ 10, "W/R RDRAM (4-word)", rdramTestBlkRw, "rdramTestBlkRw" },
{ 11, "W/R RDRAM (8-word)", rdramTestBlkRw, "rdramTestBlkRw" },
{ 12, "W/R RDRAM (4B) to pages", rdramTestPgRw, "rdramTestPgRw" },
{ 13, "Init RDRAM", rdramInit, "rdramInit" },
{ 14, "Cpu Wait", CpuWait, "CpuWait" },
{ 15, "Ebus R/W to pages", EbusTestPgRw, "EbusTestPgRw" },
{ 20, "W/R PI Reg", PiTestReg, "PiTestReg" },
{ 21, "PI IO Read", PiTestIoRead, "PiTestIoRead" },
{ 22, "PI IO Write", PiTestIoWrite, "PiTestIoWrite" },
{ 23, "PI DMA", PiTestDma, "PiTestDma" },
{ 24, "PI IO Dump", MemDump, "MemDump" },
{ 25, "PI Compare", MemCompare, "MemCompare" },
{ 26, "PI Status", PiTestStatus, "PiTestStatus" },
{ 27, "PI DMA Pages", PiTestDmaPg, "PiTestDmaPg" },
{ 30, "W/R SI Reg", SiTestReg, "SiTestReg" },
{ 31, "SI IO Read", SiTestIoRead, "SiTestIoRead" },
{ 32, "SI IO Write", SiTestIoWrite, "SiTestIoWrite" },
{ 33, "SI DMA", SiTestDma, "SiTestDma" },
{ 34, "SI Dump", MemDump, "MemDump" },
{ 35, "SI Compare", MemCompare, "MemCompare" },
{ 36, "SI Status", SiTestStatus, "SiTestStatus" },
{ 37, "SI DMA Pages", SiTestDmaPg, "SiTestDmaPg" },
{ 40, "W/R AI Reg", AiTestReg, "AiTestReg" },
{ 43, "AI DMA", AiTestDma, "AiTestDma" },
{ 45, "AI Compare", AiCompareData, "AiCompareData" },
{ 46, "AI Status", AiTestStatus, "AiTestStatus" },
{ 47, "AI DMA Pages", AiTestDmaPg, "AiTestDmaPg" },
{ 48, "AI Start DMA", AiStartDma,"AiStartDma" },
{ 49, "AI Length Decrement", AiCompareLength,"AiCompareLength" },
/* 50 is reserved for VI */
{ 60, "W/R SP Reg", SpTestReg, "SpTestReg" },
{ 61, "SP IO Read", SpTestIoRead, "SpTestIoRead" },
{ 62, "SP IO Write", SpTestIoWrite, "SpTestIoWrite" },
{ 63, "SP DMA", SpTestDma, "SpTestDma" },
{ 64, "SP IO Dump", MemDump, "MemDump" },
{ 65, "SP Compare", MemCompare, "MemCompare" },
{ 66, "SP Status", SpTestStatus, "SpTestStatus" },
{ 67, "SP DMA Pages", SpTestDmaPg, "SpTestDmaPg" },
/* 70 is reserved for DP CMD */
{ 70, "RDP List", RDPList, "RDPList" },
{ 71, "RDP List Loop", RDPListLoop, "RDPListLoop" },
{ 72, "RDP List Counter", RDPListCounter, "RDPListCounter"},
/* 80 is reserved for DP SPAN */
{ 100, "Mem Read", MemRead, "MemRead" },
{ 101, "Mem Read-Compare", MemReadCompare, "MemReadCompare" },
{ 102, "Mem Write", MemWrite, "MemWrite" },
{ 103, "Mem Write-Read", MemWriteRead, "MemWriteRead" },
{ 104, "Mem Poll Status", MemPollStatus, "MemPollStatus" },
{ 105, "Mem Compare", MemCompare, "MemCompare" },
{ 106, "Mem Dump", MemDump, "MemDump" },
{ 107, "Mem Read-Until", MemReadUntil, "MemReadUntil" },
{ 108, "Mem Read-Compare-Masked",MemReadCompMask,"MemReadCompMask" },
{ 109, "Mem Read-Write", MemReadWrite, "MemReadWrite" },
{ -1, "", NULL, "" },
};
/***********************************************************************
* Routines
*/
int
rdramConfig(int rdram1, int size, int a3, int a4)
{
if (size == 0) {
size = (rdram1) ? 4 : 2;
}
RdramInit(size);
return(1);
}
int
piConfigDom1(int lat, int pwd, int pgs, int rls)
{
_TRACE(DLOG, printf(
"\tPI Config Dom1: lat=%x, pwd=%x, pgs=%x, rls=%x\n",
lat, pwd, pgs, rls));
PiConfigDomain(PI_DOMAIN1_REG, lat, pwd, pgs, rls);
return(1);
}
int
piConfigDom2(int lat, int pwd, int pgs, int rls)
{
_TRACE(DLOG, printf(
"\tPI Config Dom2: lat=%x, pwd=%x, pgs=%x, rls=%x\n",
lat, pwd, pgs, rls));
PiConfigDomain(PI_DOMAIN2_REG, lat, pwd, pgs, rls);
return(1);
}
/*
* Stub routine to delay CPU clock cycles
*/
int
CpuWait(int count, int a2, int a3, int a4)
{
int i;
/* This generates a 4 clock delay in verilog model */
for (i = 0; i < count; i++)
IO_WRITE(MI_NOOP_REG, 0);
return(1);
}