test011.v
2.7 KB
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//
// test011 "RAS again" hazard test
//
`define PAGE0_ADDR 32'h00000000
`define PAGE1_ADDR 32'h00000800
`define PAGE0_D_DATA 64'h00000000_00000000
`define PAGE1_D_DATA 64'hffffffff_ffffffff
`define PAGE0_E_DATA 8'h00
`define PAGE1_E_DATA 8'hff
task test011;
begin
fork
test011_cmd;
test011_data;
join
end
endtask
task test011_cmd;
reg [CBUS_DATA_SIZE-1:0] address;
integer i;
begin
for (i = 0; i < 4; i = i + 1)
begin
cbus_dma_write(`DMA_UNMASKED, `DMA_UP, `PAGE0_ADDR,
BUS_DEVICE_MI, -1, 8);
cbus_dma_write(`DMA_UNMASKED, `DMA_UP, `PAGE1_ADDR,
BUS_DEVICE_MI, -1, 8);
end
for (i = 0; i < 4; i = i + 1)
begin
cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, `PAGE0_ADDR,
BUS_DEVICE_MI, 3, 8);
cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, `PAGE1_ADDR,
BUS_DEVICE_MI, 3, 8);
end
for (i = 0; i < 4; i = i + 1)
begin
cbus_dma_write(`DMA_UNMASKED, `DMA_UP, `PAGE0_ADDR,
BUS_DEVICE_MI, -1, 8);
cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, `PAGE1_ADDR,
BUS_DEVICE_MI, 3, 8);
cbus_dma_write(`DMA_UNMASKED, `DMA_UP, `PAGE1_ADDR,
BUS_DEVICE_MI, -1, 8);
cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, `PAGE0_ADDR,
BUS_DEVICE_MI, 3, 8);
end
end
endtask
task test011_data;
integer i, j;
begin
for (i = 0; i < 4; i = i + 1)
begin
dbus_data_out = `PAGE0_D_DATA;
ebus_data_out = `PAGE0_E_DATA;
while (!dma_start)
@(posedge clock);
@(posedge clock);
dbus_data_out = `PAGE1_D_DATA;
ebus_data_out = `PAGE1_E_DATA;
while (!dma_start)
@(posedge clock);
@(posedge clock);
end
for (i = 0; i < 4; i = i + 1)
begin
while (!dma_start)
@(posedge clock);
check_data("test011", `PAGE0_D_DATA, dbus_data_reg,
`PAGE0_E_DATA, ebus_data_reg);
@(posedge clock);
while (!dma_start)
@(posedge clock);
check_data("test011", `PAGE1_D_DATA, dbus_data_reg,
`PAGE1_E_DATA, ebus_data_reg);
@(posedge clock);
end
for (i = 0; i < 4; i = i + 1)
begin
dbus_data_out = `PAGE0_D_DATA;
ebus_data_out = `PAGE0_E_DATA;
while (!dma_start)
@(posedge clock);
@(posedge clock);
while (!dma_start)
@(posedge clock);
check_data("test011", `PAGE1_D_DATA, dbus_data_reg,
`PAGE1_E_DATA, ebus_data_reg);
@(posedge clock);
dbus_data_out = `PAGE1_D_DATA;
ebus_data_out = `PAGE1_E_DATA;
while (!dma_start)
@(posedge clock);
@(posedge clock);
while (!dma_start)
@(posedge clock);
check_data("test011", `PAGE0_D_DATA, dbus_data_reg,
`PAGE0_E_DATA, ebus_data_reg);
@(posedge clock);
end
end
endtask