<!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1"> <meta name="GENERATOR" content="Mozilla/4.78 [en] (X11; U; Linux 2.4.7-10 i686) [Netscape]"> <title> RCP Verification </title> </head> <body> <center> <h1> BCP Legacy Verification</h1></center> When we ported all rcp legacy tests to BCP, we believed that it was very useful if we can run all tests upon one simulator and run as long as we can. As a result, we split all tests into two groups: component level tests and simulator level tests. <p>1. Component level tests <p> There are two sets of tests in this group. RSP and VI which were used to test RSP and VI at component level, in another word, all the tests are not run on the "final/full" chip. The porting of two are very straightforward since we did not change anything about those two componet. The VI part came from RSP Misc part and RSP test was from first four sets of tests old RSP tests. <p> Those two tests are put at the very beginning nightly regressions. <p>2. Simulator level tests: <p> For BCP, we only keep one simulator which is ported from old iosim. In new BCP sim.ipc, we add the following functions to support all new features and all old tests: <p> (1) Add reading and writing (single or block) xz values <br> (2) Keep persistent connection between client and sim.ipc. <br> (3) Backdoor memory read and write <br> (4) Vi singnal snooping to dump all vi output. <br> (5) Vi table file dump. <br> (6) Backdoor old rdram file read and write <br> (7) Backdoor old rsp data read <br> (8) rsp trace functions <br> (9) rsp dmem data comparison <br> (10) Ask verilog side to display certain message for debug purpose. <br> (11) Zero time (verilog clk) operation. <br> (12) Output interrupt info with reture code. <br> (13) Change rdram configure into initDDR() (test id = 200) <p><font size=+1>2.1 Old iosim test porting</font> <br><font size=+1> (1) ai changes</font> <br><font size=+1> . change rdram config to InitDDR</font> <br><font size=+1> . Add line 49 (t 104) check AI dma status before moving on. (BUG 1367)</font> <br><font size=+1> (2) pi : <font color="#FF0000"> (TO DO)</font></font> <br><font size=+1> (3) sp changes</font> <br><font size=+1> . change rdram config to initDDR</font> <br><font size=+1> (4) si : <font color="#FF0000">(TO DO)</font></font> <br> (5) rdram change to bcp_ri.tst. What the test does are: <br> * Write data 1/x/z at each bit <br> * Write data containing x/z values <br> * Same as above, but check via memory backdoor <br> * Backdoor write, check for memory read <br> * Memory single walk (0/1/x/z), both byte, half word and word <br> * memory block walk, for all sizes. <br> * random memory backdoor access test <br> To do: <br> (1) different mode test <br> (2) RI register test <br> (3) different vendor test <br> <br> (6) ebus: <font color="#FF0000"><font size=+1>(TO DO)</font></font> <p><font size=+1>2.2 RSP(sim) test</font> <p> First four sets of tests are component level tests(see above), the last three are also port to iosim. <p> All the tests start from assembler source code, and use rdpsim1201 to generate IMEM(sp instruction) and DMEM (data segment), then run it on rspsim c simulator, dump final DMEM data and gather all SU VU DM register data at each write step as well. The result will be the comparison of final DMEM data and SU/VU/DM trace data. <p> (1) DMA test <br> The DM trace data does not matched. Checked with RCP, RCP does not either(RCP test itselg did not check DM data). <br> It seemed that rspsim is out of date.(For example, c-sim does not have DMA_FULL signal) <br> (2) pin and pin_single(single step) test <br> All tests arre ported to iosim and succeed. <p><font size=+1>2.3 RDP(sim) test</font> <p> All the DP tests will use backdoor rdram read(via x64 mode) to dowload rdram file , use iosim to dma rdplist to dp and run it, then compare the frame buffer with hardware result(from indy). <p><font size=+1> TEX test 039 coverage bits have two line difference</font> <br> We cannot make dp tests against one simulator so far. <p><font size=+1>2.4. MISC</font> <p> VI test are in component level tests. <p> Backend Iosim are ported to iosim, vi_snoop are added to support vi signal dumping . <br> h18, h32 and v32 does not work but the result are matched with rcp(not true for h32 and v32 any more). <p> Other video test are also ported and put into nightly regression. <p>2.5 Iorand <br> Test range 0, 1, 8-13 15-20 passed. <br> </body> </html>