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<center><font size="+2">SI System Level DV Test Plan</font></center>
<p>Reference: <br>
<a href="../hw/si-spec.html">SI Spec</a>
<br>
<a href="si-dv.html">SI DV Test Plan</a>
<br>
Verilog test file(vsim/tests/si_test.v) </p>
<p>To do list: <br>
(1) <strike>Frank will make SI worked both in master and slave mode.</strike>
Both Frank and Bill have provided master models for slave mode
testing. I am using Bills model for basic operation and Franks model
for random bit time, bit time violations(frame error), truncated commands,
collisions, some resets, and reserved commands.<br>
(2) Jctrl compatibility test <br>
(3) Try to use serial protocol to monitor outgoing data. <br>
(4) CPU level test. (Waiting until Frank integrating R4300 is done)
<br>
* Write MIPS code to
driven SI, compile and link with existing libultra. <br>
* Load final rom
into flash <br>
* Let MIPS run
it. <br>
(5) Done: <strike>Haishan write backdoor ipc task for jctrl.
</strike><br>
(6) Rumble pak support. (After Frank done with hardware)<br>
(7) Done: <strike>Update Local Controller tests after Frank makes
changes</strike><br>
(8) Done: <strike>Iorand tests</strike></p>
<a href="#SI_System_Level_DV_Test_Plan">SI System Level DV Test Plan</a>
<br>
<a href="#SI_System_Level_DV_Test_Descriptions">SI System Level DV Test
Descriptions</a>
<p><br>
</p>
<h3><a name="SI_System_Level_DV_Test_Plan"></a>
SI System Level DV Test Plan</h3>
<p>1. SI Register test</p>
<p> * SI_STATUS register (0x4800018). <br>
(1) READ when test
starts and check that it is 0 after system start(/reset). <br>
(2) Write data
to SI_STATUS with the following pattern, and read back and check data (should
be ignored) <br>
cycle through defined bits setting each to 1 while other defined bits
are set to 0 and unused bits are set to x<br>
cycle through defined bits setting each to 0 while other defined bits
are set to 1 and unused bits are set to x<br>
one bit(from bit 0 to 31) is 1, all others are 0 <br>
one bit is 0, all others are 1<br>
(3) use register_test
routine to test that rw bits can be toggled to 1 and 0, that ro bits
can't be written, and try random write patterns.<br>
<br>
</p>
<p> * SI_DRAM_ADDR <br>
(1) Verify that bits
[2:0] are ignored in DMAs (i.e verify 8-byte align is forced)<br>
(2) Fill pattern as above
(2 and 3) and make sure data reads as expected. <br>
(3) Test addr crossing
page(2k) boundary<br>
-- Actual write/read done in SI DMA test case: SiTestDmaSpecificAddrs
</p>
<p> * SI_DMA_WRITE, SI_DMA_READ, SI_RAM <br>
Will be tested
in DMA part </p>
<p> * SI_CONFIG (0x480001C) <br>
* SI_CTRL(0x0480000C) <br>
As in (2 and 3) for
SI_STATUS, test all defined bits of SI_COFNIG and SI_CTRL. </p>
<p> For RW bit, test if
it was correctly set. <br>
R only bit, check if
it can be changed. <br>
When tests are done,
set to "reset" status. <br>
<br>
Test Case for all of "SI Register test": SiTestRegisters</p>
<p>2. PIO test <br>
R/W to SI_RAM (from 0x1fc007c0 to 0x1fc007ff),
and verify that write is ignored and reads return 0.</p>
<p> Test case for
"PIO test": done in SiTestRegisters <br>
</p>
<p>3. SI DMA test </p>
<p> * 3.1 DMA Write test <br>
3.1.1Set
SI_DMA_ADDR to the following kinds of addr: <br>
(1) Perfect address (align 8)<br>
Test Case: SiTestValidCtrlCmds<br>
(2) Not align to 8 byte(test all cased from 1-7)<br>
Test Case: SiTestDmaSpecificAddrs<br>
(3) Cross 2k page boundry<br>
Test Case: SiTestDmaSpecificAddrs<br>
(4) x36 mode address<br>
Test Case: SiTestDmaSpecificAddrs<br>
(5) x64 mode address (lower 16 MBytes)<br>
Test Case: SiTestDmaSpecificAddrs <br>
(6) Cross DDR bank(at least, check bank 0/1 and
2/3 cross)<br>
Test Case: SiTestDmaSpecificAddrs <br>
(7) Other boundaries: 16bytes, 32bytes, 64bytes, 128bytes, 256bytes
, 512bytes, 1K, 4K, 8K, 16K, 32K, 64K, 128K, 256K, 512K, 1M, 2M, 4M<br>
Test Case: SiTestDmaSpecificAddrs<br>
(8) Walk 1’s: Test SI DMA Writes (and Reads) with starting addresses
defined by the bit sequence below (r stands for random). Do this for both
x36 and x64 addresses.<br>
Test Case: <span class="SpellE">SiTestDmaWalkBits</span></p>
<p style="margin-left: 1.5in; "><span style="font-family: "Courier New"; ">
00000000000000000000000000000000<br>
00000000000000000000000000001000<br>
0000000000000000000000000001r000<br>
000000000000000000000000001rr000<br>
00000000000000000000000001rrr000<br>
0000000000000000000000001rrrr000<br>
<span style="mso-spacerun:yes"> </span><span style="mso-spacerun:yes">
</span>:<br>
0000000001rrrrrrrrrrrrrrrrrrr000<br>
000000001rrrrrrrrrrrrrrrrrrrr000<br>
00000001rrrrrrrrrrrrrrrrrrrrr000<br>
00000010rrrrrrrrrrrrrrrrrrrrr000<o:p></o:p></span></p>
<p>
(9) Walk 0’s: Test SI DMA Writes (and Reads) with starting addresses
defined by the bit sequence below (r stands for random). Do this
for both x36 and x64 addresses.<br>
Test Case: <span class="SpellE">SiTestDmaWalkBits</span></p>
<p style="margin-left: 1.5in; "><span style="font-family: "Courier New"; ">
00000010111111111111111111100000<br>
000000101111111111111111110rr000<br>
00000010111111111111111110rrr000<br>
0000001011111111111111110rrrr000<br>
000000101111111111111110rrrrr000<br>
00000010111111111111110rrrrrr000<br>
<span style="mso-spacerun:yes"> </span><span style="mso-spacerun:yes">
</span>:<br>
0000001010rrrrrrrrrrrrrrrrrrr000<br>
000000100rrrrrrrrrrrrrrrrrrrr000<br>
00000010rrrrrrrrrrrrrrrrrrrrr000<br>
0000000rrrrrrrrrrrrrrrrrrrrrr000<br>
<o:p></o:p></span></p>
<p><br>
3.1.2 Fill
a pattern into memory via memory backdoor access. <br>
Then,
write any value(including x,z values) to SI_DMA_WRITE address, read data
from SI_STATUS, then check the following items <br>
(1) DMA_BUSY is set or not (value might be depend on each cases,
double check DMA can be started) <br>
(2) If DMA_BUSY is set, poll until done with a timeout. <br>
Check that finishes within reasonable time. <br>
(3) Check if DMA_ERR is 0 <br>
(4) Check if INT is set and also check on reply code to see if
int is set. <br>
Write any value to clear SI_STATUS, then read back to see if all bits
are expected(e.g, INT is clear?, etc)</p>
<p>
Test Case: SiTestValidCtrlCmds,
SiTestDmaSpecificAddrs, <span class="SpellE">SiTestDmaWalkBits</span>
, SiRandomTests, SiTestDmaXs, and most other test cases<br>
</p>
<p> * 3.2 DMA Read Test <br>
Test
all the different address cases(refer to DMA write) with: <br>
(1) All joychannels with valid supported command (0/1/255)<br>
* Set data to SI controller by SI controller backdoor(at least walk
through all buttons). <br>
* Write any data to SI_DMA_WRITE(to see if DMA can be started)
<br>
* Test DMA_BUSY is set or not <br>
* If DMA_BUSY is set(read from SI_STATUS), then polling until
is done <br>
* check is DMA_ERR is 0 <br>
* check INT bit (remember to check from reply code also) <br>
* compare data in memory with SI buffer. <br>
* check if response is correct for each channel. <br>
reply and also compare with data you pre-set via si controller backdoor. </p>
<p>
Test Case:
SiTestValidCtrlCmds<span class="GramE">, SiTestDmaSpecificAddrs</span>
, <span class="SpellE">SiTestDmaWalkBits</span><br>
</p>
<p> (2) Pick
up a few typical case in (1) , when DMA_BUSY is set, do <br>
Write to any of DMA register(DMA_DRAM_ADDR, SI_DMA_WRITE, SI_DMA_READ,
<br>
Then read SI_STATUS, check if DMA_ERR bit is set of not.</p>
<p>
Test Case:
SiTestDmaBusyError<br>
<br>
(3)
Test invalid command for each joychannel and local ctrlr and combinations.</p>
<p>
Test Case:
SiTestInvalidCtrlrCmds, SiTestCtrlrErrViaBD<br>
</p>
<p> (4)
Set error mode, then create error cases(illegal rx/snd size, frame errors,
collisions, reset and timeout), then check to see if the second byte
of reply is correctly set.</p>
<p>
Test Case:
SiTestInvalidCtrlrCmds, SiTestCtrlrErrViaBD</p>
<p> (5) Test unsupported pass through
commands (i.e. 4 - 254)<br>
</p>
<p>
Test Case:
SiTestValidCtrlCmds<span class="GramE">, </span>SiTestInvalidCtrlrCmds,
SiTestCtrlrErrViaBD</p>
<p>4. SI channel reset test <br>
Start a DMA read with button/stick query
for all controllers. Set the JCRST bit in SI_CTRL to start a joy channel
reset. Reset the JCRST bit after 805 us. Check the result of
the DMA read and verify that all controllers have the controller reset
error bit set. Do another DMA read with button/stick query and verify
that it completes normally.<br>
</p>
<p> Test Case:
SiTestJChannelReset<br>
</p>
<p>5. Local controller Tests <br>
Set data(e.g, button press, etc) via local
controller backdoor. (walk through all buttons && random patterns)
<br>
Check results with what was set through
the backdoor. </p>
<p> Test Case:
Cycles through all buttons in SiTestDmaSpecificAddrs. Most
other tests also test local controller buttons and x,y.</p>
<p> Local controller single command dectection test.
<br>
With SI_CONFIG bit 23 set to 0, issue a
command with block byte (byte 0) set to 0. Verify that the command
works normally.<br>
With SI_CONFIG bit 23 set to 1, issue a command
with byte 0 set to 0, check that all returned bits are 1s.</p>
<p> Test Case:
SiTestSingleCmdDetection<br>
</p>
<p> SI_CONFIG [21:16] button rate control. <br>
Set it to different rates, then measure the how
long in sim time it takes to see the data via DMA. Check if is in reasonable
range</p>
<p> Test Case:
SiTestLCtrlButRate <br>
</p>
<p><span style="mso-spacerun:yes"> </span>JSRST (L, R,
START pressed at same time reset stick reference)<br>
<span style="mso-spacerun:yes"> </span>Test that if
the L, R, and START buttons are pressed <span class="GramE">simultaneously<span style="mso-spacerun:yes"></span>
on</span> the Local controller, the stick reference is reset.</p>
<p> Test Case:
SiTestLCtrlJSRST<span class="GramE"></span></p>
<p> Test local controller button sample deglitching.<br>
Set buttons to 0<br>
Set button rate to 1 unless specified
otherwise<br>
Use default jc_div = 31, tXfer
= tHigh = tLow = 2000,<br>
jitter = 0<br>
Set buttons on via bd for 1.25
sample period, verify no<br>
change in button state<br>
Set buttons off via bd, verify
no change in button state<br>
Verify buttons don't show up
in dma button query within<br>
the max time they would have
shown up if we didn't turn them off.<br>
Set buttons on for 2.25 sample
period, verify they don't show as on<br>
set buttons off, verify they
don't show as on<br>
Verify buttons don't show up
in dma button query within<br>
the max time they would have
shown up if we didn't turn them off.<br>
</p>
<p> Test Case:
SiTestLCtrlButDeglitch<br>
</p>
<p> Test local controller X,Y movement<br>
For (+x, -y), (+x, +y), (-x, -y), and (-x, +y)
counts:<br>
Cmd x,y to move part way
to limit via bd and see that<br>
lctrl DMA button/xy query indicates
that they get there.<br>
Do an lctrl button test without
changing x,y input and<br>
verify that x,y in lctrl DMA button/xy
query doesn't change<br>
Cmd x and y beyond x,y limits and
see that the querried<br>
value pegs at the limits.
Verify that subsequent movement<br>
behaves normally.<br>
<br>
Use jitter during the tests</p>
<p> Test Case:
SiTestLCtrlJsxy<br>
<span class="GramE"></span></p>
<p> Test local controller X,Y sample deglitching.<br>
Use backdoor parameters:<br>
xglitch[0], xglitch[1]
, yglitch[0], and yglitch[1]<br>
to create glitches on the respective
x and y pulse signals.<br>
Verify that the X and Y do not change.
<br>
</p>
<p> Test Case:
SiTestLCtrlJsxyDeglitch<br>
<br>
</p>
<p>6. Test Slave mode <br>
Using Bill's master model, in slave mode setup
jctrl 1 to receive cmds from the master. Request the master model
to send each of the valid cmds (0,1,255), get the response from the
local controller, prepare and transmit the response to the master, retrieve
and verify the data received by the master. Test getting the lctrl
response in a separate DMA after receiving the cmd from the master. Test
getting the lctrl response for button/joystick x,y in the same DMA in which
the master cmd is received.</p>
<p> While doing slave mode transactions verify expected
behavior of all assoiated register bits and interrupts. This includes at
least, SI_CONFIG JC_SLAVE, SI_CTRL XMIT, BUSY, REQ, SI_STATUS bits
assoiated with DMA's used during slave mode transactions, and interrupt indications.</p>
<p> Test Joy Channel resets commanded by master while in slave
mode. <br>
</p>
<ol>
<li>with rcv active (before cmd rqstd) start a reset, after reset should
have completed, check, should get reset error bit set (plus maybe no response)</li>
<li>with rcv active (before cmd rqstd) start a reset, after it should
have completed, rqst cmd and check, should get reset error bit set (plus
maybe no response</li>
<li>with rcv active (before cmd rqstd) start a reset, during reset,
check, should get reset error bit set (plus maybe no response)</li>
<li>before start cmd receive start a reset, start rcv during reset,
check, should get reset error bit set</li>
<li>reset during reception of a cmd from the master, (use Franks backdoor
reset for this one)</li>
</ol>
Using Frank's master model:
<ol>
<li>Use the backdoor rsp_random setting to test randomly stretched bit
pulses within the spec limits.</li>
<li>Use the backdoor to generate bit timing violations to test the frame
error detection. Verify that the frame error bit gets set.</li>
<li>Use the backdoor to disable the master model during a command transmition
to the slave to test truncated commands. Verify that truncated commands
cause a no response error and that a good command can be received after
64us.</li>
<li>Use the backdoor to force a collision during trasnmission of the
slave response to the master. Verify that the collision error is indicated
in the error bits.</li>
<li>Verify that the SI can receive random commands in the range 4 to
254 with the number of bytes received indicated by bits [2:0] of the cmd.<br>
</li>
</ol>
<p></p>
<p> Test Case:
SiTestSlave<br>
</p>
<p>7 Random tests <br>
Run tests with random controller
cmds, random expected responses via backdoor, random failures, random addresses
for write and read DMA buffers. </p>
<p> Test Case:
SiTestRandom<br>
</p>
<p>8. Iorand test. <br>
Pick up a few typical cases, and fit it into
iorand test frame. <br>
</p>
<p> Test Case:
SiTestRandEnv runs the following tests in the Iorand environment:</p>
<blockquote>
<blockquote>SiTestRandom(1, ForceFail_None, 0, 0);<br>
SiTestRandom(1, ForceFail_None, StartWithXs, 0);<br>
SiTestValidCtrlCmds(1, 0, 0, 0);<br>
SiTestInvalidCtrlrCmds(1, 0, 0, 0);<br>
SiTestCtrlrErrViaBD(1, CtrlQueryStatus, 0, 0);<br>
SiTestDmaBusyError(1, SI_DMA_WR_REG, PIF_RAM_START, 0);<br>
SiTestSingleCmdDetection(1, 1, 0, 0);<br>
SiTestJChannelReset(1, 0, 0, 0);<br>
SiTestDmaStress(num_iterations);<br>
<br>
</blockquote>
</blockquote>
<p>9. Test SI interrupt mask/unmask<br>
Test that when the SI interrupt mask bit is set
in the MI_INTR_MASK_REG, the interrupt shows up in the lsb of int_l.<br>
Test that when the SI interrupt mask bit is not
set in the MI_INTR_MASK_REG, the interrupt does not show up in the lsb
of int_l.</p>
<p> Test Case:
All DMA tests check for the existance of the interrupt after each DMA.<br>
A SiTestRandom() test is run with the SI int mask bit not set to
test that case.<br>
<br>
</p>
<p> </p>
<p><br>
</p>
<h3><br>
</h3>
<h3><a name="SI_System_Level_DV_Test_Descriptions"></a>
SI System Level DV Test Descriptions</h3>
<h3>Overview</h3>
The nightly SI regressions are run by invoking the function SiRunTests()
which then invokes the set of tests to be performed. Either
iosim with the input file "bcp_si.tst" or the executable "si_test" can be
used to invoke SiRunTests().<br>
<br>
To get debug outputs, use -d 0x0141 on the isoim or si_test cmd line.<br>
<br>
SiRunTests ( testmask, levels, reserved, seed)<br>
<br>
if seed not 0, use seed to initialize
with srandom<br>
<br>
run a test if testmask == 0 or
bit(test_num) is set in testmask<br>
and levels == 0 or test_lvl <
levels. For example:<br>
levels
== 0<br>
run lvl 0, 1, 2, 3, ...<br>
levels
== 1<br>
run lvl 0<br>
levels
== 2<br>
run lvl 0, 1<br>
levels
== 3<br>
run lvl 0, 1, 2
<blockquote>levels is also passed to most test routines so it can limit
the amount of test cases based on level. Most test routines ignore
the levels arg, but it is used by some tests.<br>
</blockquote>
<br>
<tt> test_num test_lvl<br>
|
/<br>
</tt><tt> TEST( 29, 0, SiTestRegisters
</tt><tt> ( levels, 0,
0,
seed) );<br>
</tt><tt> TEST( 0, 0, SiTestValidCtrlCmds
( levels, 0,
0,
seed) );</tt><br>
<tt> TEST( 1, 0, SiTestInvalidCtrlrCmds
( levels, 0,
0,
seed) );<br>
TEST( 2, 2, SiTestCtrlrErrViaBD
( levels, CtrlQueryStatus, 0,
seed) );<br>
TEST( 3, 1, SiTestCtrlrErrViaBD
( levels, CtrlReset, 0,
seed) );<br>
TEST( 4, 0, SiTestCtrlrErrViaBD
( levels, CtrlQueryButtons, 0,
seed) );<br>
TEST( 5, 1, SiTestCtrlrErrViaBD
( levels, CtrlJcUnsupCmd, 0,
seed) );<br>
TEST( 6, 1, SiTestCtrlrErrViaBD
( levels, CtrlNoXmitRand, 0,
seed) );<br>
TEST( 7, 2, SiTestDmaBusyError
( levels, SI_DMA_WR_REG, SI_RAM,
0) );<br>
TEST( 8, 1, SiTestDmaBusyError
( levels, SI_DMA_RD_REG, SI_RAM,
0) );<br>
TEST( 9, 0, SiTestDmaBusyError
( levels, SI_DRAM_ADDR_REG, 0x40,
0) );<br>
TEST( 10, 1, SiTestSingleCmdDetection ( levels,
0,
0,
seed) );<br>
TEST( 11, 0, SiTestSingleCmdDetection ( levels,
1,
0,
seed) );<br>
TEST( 12, 0, SiTestJChannelReset
( levels, 0,
0,
seed) );<br>
TEST( 13, 0, SiTestDmaSpecificAddrs
( levels, 0,
0,
seed) );<br>
TEST( 14, 0, SiTestDmaSpecificAddrs
( levels, 1,
0,
seed) );<br>
TEST( 15, 0, SiTestDmaWalkBits
( levels, 0,
0,
seed) );<br>
TEST( 16, 3, SiTestDmaWalkBits
( levels, 1,
0,
seed) );<br>
TEST( 17, 1, SiTestDmaWalkBits
( levels, 0,
1,
seed) );<br>
TEST( 18, 1, SiTestDmaWalkBits
( levels, 1,
1,
seed) );<br>
TEST( 19, 1, SiTestRandom
( 5, ForceFail_None, StartWithXs,
seed) );<br>
TEST( 20, 2, SiTestRandom
( 10, ForceFail_None, 0,
seed) );<br>
TEST( 21, 3, SiTestRandom
( 10, ForceFail_Random, 0,
seed) );<br>
TEST( 22, 2, SiTestRandom
( 10, ForceFail_None, JChannel_Resp_Rand,
seed) );<br>
TEST( 23, 2, SiTestLCtrlJSRST
( levels, 0,
0,
seed) );<br>
TEST( 24, 1, SiTestLCtrlButRate
( levels, 0,
0,
seed) );<br>
TEST( 25, 1, SiTestLCtrlJsxy
( levels, LCTRL_SOMEJITTER, 0,
seed) );<br>
TEST( 26, 2, SiTestRandom
( 1, ForceFail_ClearSiIntMask, 0,
seed) );<br>
</tt><tt> TEST( 27, 2, SiTestLCtrlButDeglitch
( levels, 0,
0,
seed) );<br>
</tt><tt> TEST( 28, 2, SiTestLCtrlJsxyDeglitch</tt><tt>
( levels, 0,
0,
seed) );</tt><br>
<tt> TEST( 30, 2, SiTestBugFixes
</tt><tt> ( levels, 0,
0,
seed) );</tt><br>
<tt> TEST( 31, 2, SiTestSlave
</tt><tt> ( levels, 0,
0,
seed) );</tt><br>
<br>
<br>
<br>
Tests other than the register tests use a common set of lower level
routines for:<br>
<ul>
<li>Initializing test data structures and default parameter values</li>
<li>Setting up simulation backdoor parameters per the intent of
the test</li>
<li>Setting up failure cases if the test specifies<br>
</li>
<li>Setting up DMA buffers</li>
<li>DMA write (with timeout) to provide controller commands to SI</li>
<li>DMA read (with timeout) to get results of controller commands</li>
<li>Check DMA results with expected values</li>
</ul>
Tests fill in an SiDmaTestParam data structure that specifies everything
about a DMA write, DMA read, backdoor setup, forced failures, and
all expected results of the DMA read (including expected failures).
That data structure is then passed to lower level routines to perform the
test. Sometimes aspects of the test need to be checked specifically
by the high level test routine, but frequently, no additional checks are
required other than what is done by the low level routines.<br>
<br>
Since all the tests use common low level routines, every test automatically
checks most aspects of the DMA's and other common aspects of tests. For
Example:<br>
<ul>
<li>Before every DMA start:</li>
<ul>
<li>DMA_ERR bit is checked</li>
<li>DMA_BUSY bit is checked</li>
<li>SI interrupt in MI_INTR_REG is checked</li>
<li>interrupt in lsb of int_l is checked</li>
</ul>
<li>After every DMA start:</li>
<ul>
<li>DMA_ERR bit is checked</li>
<li>DMA_BUSY bit is checked</li>
</ul>
<li>On every DMA completion:</li>
<ul>
<li> there is a timeout on DMA_BUSY</li>
<li>DMA_ERR bit is checked</li>
<li>SI status reg interrupt pending bit is checked</li>
<li>SI interrupt in MI_INTR_REG is checked</li>
<li>interrupt in lsb of int_l is checked</li>
<li>status is cleared</li>
</ul>
<li>When appropriate, after DMA read completion</li>
<ul>
<li>guard bands arround DMA buffer are checked</li>
<li>data in DMA buffer is compared to expected values</li>
</ul>
</ul>
The checks take expected failures into consideration when testing error
cases.<br>
<br>
Most tests supply random values for parameters that are not specifically
being tested. For example, if we are specifically testing local
controller X,Y movement, the joy channel controllers are issued random
commands with random expected values setup via backdoor writes. The
results of those commands are automatically checked. While we are
doing most tests, local controller button and X,Y movement are tested with
random expected values setup via backdoor. X,Y movement tests can
span multiple unrelated test cases. The results are automatically
checked.<br>
<br>
When checking local controller X,Y movement during any test, verifies
that the expected X,Y is reached within the expected max time and that
the position doesn't change after reaching the expected position until
the next backdoor X,Y move commands are issued. During movement,
each X,Y sample is checked to see that it is moving closer to the target
values. Once an X,Y movement is started during a test, no new X,Y
movement backdoor cmds will be issued until the previous movement has been
completely verified or a reset has been performed. When resets are
commanded, it is verified that X,Y goes to and stays at 0.<br>
<br>
When checking local controller buttons, it is verified that the expected
button values show up within the computed max time for 3 button samples.<br>
<br>
Random DMA buffer addresses are used except when testing specific DMA
buffer locations. <br>
Memory size is determinined dynamically and random addresses are taken
from the memory available. <br>
<br>
There are several global parameters that have a default value that
can be temporarily modified during specific tests or for debugging<br>
<br>
<blockquote>use_rsp_echo[4]
default: { 0, 1, 1, 1 }<br>
Set array element 1 - 3 to 0 to disable use of response echo for corresponding
jc ctrlr.<br>
<br>
use_rsp_rand[4]
default: [ 0, 0, 0, 0 ] <br>
Set array element 1 - 3 to non-zero to enable response randomization
for the corresponding jc ctrlr. This is normally only turned on for
specific tests, as it increases the time required to perform the tests.<br>
<br>
no_random_jsrst
default: 0<br>
Set to non-zero to prevent Joystick reset button combinations (JSRST
- Start, L, and R) when using random button values in tests. Even
if no_random_jsrst is zero, a JSRST button combination will not be produced
by the random buttton generator if it has done so within the last 20 calls.<br>
<br>
random_seed
default: 0x0badface<br>
This is the random seed that is used unless it is overridden by passing
a non-zero seed parameter to SiRunTests or a specific test.<br>
<br>
si_use_io_read_io_write default: 0<br>
Set to non-zero to force use of IO_READ/IO_WRITE rather than backdoor
writes or extended read/writes.<br>
<br>
stop_tests_on_err
default: 0<br>
Set to non-zero to terminate entire test run at end of a test that
fails.<br>
<br>
stop_test_on_err
default: 0<br>
Set to non-zero to terminate the current test on detection of a failure.<br>
<br>
<br>
</blockquote>
<h3>Description of each test</h3>
<br>
<tt><br>
<b>TEST( 29, 0, SiTestRegisters
( levels, 0,
0,
seed) );</b></tt>
<blockquote>Do a pin reset and then check SI_STATUS, SI_CONFIG, and
SI_CTRL for correct reset initialization.<br>
<br>
For SI_STATUS, SI_CONFIG, SI_CTRL, and SI_DRAM_ADDR<br>
<ul>
<li>Write data with the following pattern, and read back and
check data for correct values </li>
</ul>
cycle through defined bits setting each to 1 while other defined bits
are set to 0 and unused bits are set to x<br>
cycle through defined bits setting each to 0 while other defined bits
are set to 1 and unused bits are set to x<br>
one bit(from bit 0 to 31) is 1, all others are 0 <br>
one bit is 0, all others are 1<br>
<ul>
<li>use register_test routine to test that rw bits can be toggled
to 1 and 0, that ro bits can't be written, and try random write patterns.</li>
</ul>
R/W to SI_RAM (from 0x1fc007c0 to 0x1fc007ff), and verify that write is
ignored and reads return 0.<br>
</blockquote>
<tt> <b><br>
<b>TEST( 0, 0, SiTestValidCtrlCmds
( levels, 0,
0,
seed) );</b></b></tt><b> </b>
<blockquote>Test non-error cases for Local and JCtrl cmds.
This tests most aspects of SI ctrlr cmd/response that are expected to complete
without errors.<br>
<br>
Tests all supported cmd types (button, type/status, reset) and random
unsupported (i.e. pass through) commands. Tests same cmd types to
all controllers and different mixes of commands to controlleers. Tests
all cmd types with tx size 0 (no xmit).<br>
<br>
Uses random DMA buffer addressses and random values for expected values
setup via backdoor.<br>
</blockquote>
<b><tt> <b><br>
TEST( 1, 0, SiTestInvalidCtrlrCmds ( levels, 0,
0,
seed) );<br>
</b></tt> </b>
<blockquote>Test ctrlr cmds with errors in the cmd fields.<br>
<br>
Tests all supported cmd types (button, type/status, reset) and random
unsupported (i.e. pass through) commands. Tests all cmd types with
tx size 0 (no xmit).<br>
<br>
tx_size too big for any cmd (i.e. > 5)<br>
invalid tx_size for the cmd<br>
rx_size too big for any cmd (i.e. > 4)<br>
rx_size 0<br>
invalid rx_size for the cmd<br>
<b> <br>
</b></blockquote>
<b> <tt><b> TEST( 2, 2, SiTestCtrlrErrViaBD
( levels, CtrlQueryStatus, 0,
seed) );</b></tt> </b>
<blockquote>Force errors via joy channel backdoor for controller
type/status query on all combinations of jc 1, jc 2, and jc 3. A
query with no errors is done on the local controller.<br>
<br>
Test no response from disabled ctrlr<br>
Test collision err set via backdoor<br>
Test frame err set via backdoor<br>
</blockquote>
<b><br>
<tt><b>TEST( 3, 1, SiTestCtrlrErrViaBD
( levels, CtrlReset, 0,
seed) );<br>
</b></tt> </b>
<blockquote>Force errors via joy channel backdoor for controller
reset cmd on all combinations of jc 1, jc 2, and jc 3. A cmd with
no errors is done on the local controller.<br>
<br>
Test no response from disabled ctrlr<br>
Test collision err set via backdoor<br>
Test frame err set via backdoor<br>
</blockquote>
<b><br>
<tt><b>TEST( 4, 0, SiTestCtrlrErrViaBD
( levels, CtrlQueryButtons, 0,
seed) );<br>
</b></tt>
</b>
<blockquote>Force errors via joy channel backdoor for controller
button/xy query on all combinations of jc 1, jc 2, and jc 3. A query
with no errors is done on the local controller.<br>
<br>
Test no response from disabled ctrlr<br>
Test collision err set via backdoor<br>
Test frame err set via backdoor<br>
</blockquote>
<b><br>
<tt><b>TEST( 5, 1, SiTestCtrlrErrViaBD
( levels, CtrlJcUnsupCmd, 0,
seed) );<br>
</b></tt>
</b>
<blockquote>Force errors via joy channel backdoor for
random unsupported (pass through) controller queries on all combinations
of jc 1, jc 2, and jc 3. A query with no errors is done on the local
controller.<br>
<br>
Test no response from disabled ctrlr<br>
Test collision err set via backdoor<br>
Test frame err set via backdoor<br>
</blockquote>
<b><br>
<tt><b>TEST( 6, 1, SiTestCtrlrErrViaBD
( levels, CtrlNoXmitRand, 0,
seed) );<br>
</b></tt>
</b>
<blockquote>Force errors via joy channel backdoor for
random controller cmds with tx_size set to 0 query on all combinations
of jc 1, jc 2, and jc 3. A query with no errors is done on the local
controller.<br>
<br>
Since there should be no cmd transmitted to joy channel controllers
when tx_size is 0, these tests are expected to behave the same as 'no xmit'
cmds without any joy channel controller forced fails.<br>
<br>
Test no response from disabled ctrlr<br>
Test collision err set via backdoor<br>
Test frame err set via backdoor<br>
</blockquote>
<b><br>
<tt><b>TEST( 7, 2, SiTestDmaBusyError
( levels, SI_DMA_WR_REG, </b></tt><tt><b>data_to_write,
0) );<br>
</b></tt>
</b>
<blockquote>Test ability to create and clear DMA
busy errors.<br>
Write to SI DMA WRITE register while DMA is busy to cause error.<br>
Uses button queries with random expected values for buttons and x,y.<br>
The default value written to the register is PIF_RAM_START.<br>
<b> <br>
</b></blockquote>
<b> <tt><b>TEST( 8, 1, SiTestDmaBusyError
( levels, SI_DMA_RD_REG, data_to_write</b></tt><tt><b>
, 0) );<br>
</b></tt>
</b>
<blockquote>Test ability to create and clear DMA
busy errors.<br>
Write to SI DMA READ register while DMA is busy to cause error.<br>
Uses button queries with random expected values for buttons and x,y.<br>
The default value written to the register is PIF_RAM_START.<br>
<b> <br>
</b></blockquote>
<b> <tt><b>TEST( 9, 0, SiTestDmaBusyError
( levels, SI_DRAM_ADDR_REG, data_to_write,
0) );<br>
</b></tt>
</b>
<blockquote>Test ability to create and clear
DMA busy errors.<br>
Write to SI DMA ADDR register while DMA is busy to cause error.<br>
Uses button queries with random expected values for buttons and x,y.<br>
The default value written to the register is 0x40.<br>
<b> <br>
</b></blockquote>
<b> <tt><b>TEST( 10, 1, SiTestSingleCmdDetection
( levels, sgl_err_bit = 0, 0,
seed) );<br>
</b></tt>
</b>
<blockquote>Test single cmd indicated by block
byte = 0<br>
Try with SI_CONFIG bit 23 set to 0 so single cmd should not be detected
and the commands should work normally.<br>
<br>
Try with lc, j1, j2, and j3 block byte 0 and with j1, j2, j3 block
byte 0 but lc block byte FF .<br>
<b> <br>
</b></blockquote>
<b> <tt><b>TEST( 11, 0, SiTestSingleCmdDetection
( levels, 1</b></tt><tt><b>sgl_err_bit = 1, 0,</b></tt><tt><b>
seed) );<br>
</b></tt>
</b>
<blockquote>Test single cmd indicated by block
byte = 0<br>
Try with SI_CONFIG bit 23 set to 1 to cause all 1's to be returned
by DMA read.<br>
<br>
Try with lc, j1, j2, and j3 block byte 0 and with j1, j2, j3 block
byte 0 but lc block byte FF .<br>
<b> <br>
</b></blockquote>
<b> <tt><b>TEST( 12, 0, SiTestJChannelReset
( levels, 0,
0,
seed) );<br>
</b></tt>
</b>
<blockquote>Do a DMA write to SI with button/xy
querries for all controllers. Start an SI DMA read. While the
DMA read is busy, set the JCRST bit to cause a reset of all joy channel
controllers.<br>
<br>
Wait 805 microsec and clear the JCRST. Do an SI DMA read
and verify that the controller reset error bit is set for all controllers.<br>
<br>
Do another button/xy querry to verify that controllers are operating
normally.<br>
<b> <br>
</b></blockquote>
<b> <tt><b>TEST( 13, 0, SiTestDmaSpecificAddrs
( levels, writes,
0,
seed) );<br>
</b></tt>
</b>
<blockquote>Test SI DMA writes from buffers
at interesting addresses.<br>
This also tests aspects of SI ctrlr cmd/response that are expected
to complete without errors.<br>
<br>
Start write with DMA buffer at non-8byte alligned addr for lsbs 1,2,3,4,5,6,7.
SI should ignore the lsbs.<br>
<br>
Do DMA writes with buffers that cross boundaries: 16bytes, 32bytes,
64bytes, 128bytes, 256bytes , 512bytes, 1K, 2K, 4K, 8K, 16K, 32K, 64K, 128K,
256K, 512K, 1M, 2M, 4M<br>
includes jctrl and lctrl cmds/response check<br>
walks through bit set for each jctrl/lctrl
button<br>
random x/y's<br>
includes random write values to start write/read DMAs<br>
Before doing DMAs with buffer that crosses megabyte boundary (or 2
megabyte for 64 bit mode) zero 32 bytes at addr 0 and megabyte boundaries.<br>
<br>
check crossing bank 0/1 (already done above) and 2/3<br>
bank 0/1 crossed when bit 6 goes from 0->1 for address under 1M
(i.e. starting at 64-8 == 0x00000040 - 8)<br>
bank 2/3 crossed when bit 6 goes from 0->1 for address over 1M
(i.e. starting at 0x00101040 - 16)<br>
<br>
do x64 mode, bank crossing starting dma buffer at 0x01201080 - 16<br>
<b> <br>
</b></blockquote>
<b> <tt><b>TEST( 14, 0, SiTestDmaSpecificAddrs
( levels, reads,
0,
seed) );<br>
</b></tt>
</b>
<blockquote>Test SI DMA reads to interesting
addresses.<br>
This also tests aspects of SI ctrlr cmd/response that are expected
to complete without errors.<br>
<br>
Start read with DMA buffer at non-8byte alligned addr for lsbs 1,2,3,4,5,6,7.
SI should ignore the lsbs.<br>
<br>
Do DMA reads with buffers that cross boundaries: 16bytes, 32bytes,
64bytes, 128bytes, 256bytes , 512bytes, 1K, 2K, 4K, 8K, 16K, 32K, 64K, 128K,
256K, 512K, 1M, 2M, 4M<br>
includes jctrl and lctrl cmds/response check<br>
walks through bit set for each jctrl/lctrl
button<br>
random x/y's<br>
includes random write values to start write/read DMAs<br>
Before doing DMAs with buffer that crosses megabyte boundary (or 2
megabyte for 64 bit mode) zero 32 bytes at addr 0 and megabyte boundaries.<br>
<br>
check crossing bank 0/1 (already done above) and 2/3<br>
bank 0/1 crossed when bit 6 goes from 0->1 for address under 1M
(i.e. starting at 64-8 == 0x00000040 - 8)<br>
bank 2/3 crossed when bit 6 goes from 0->1 for address over 1M
(i.e. starting at 0x00101040 - 16)<br>
<br>
do x64 mode, bank crossing starting dma buffer at 0x01201080 - 16<br>
<b> <br>
</b></blockquote>
<b> <tt><b>TEST( 15, 0, SiTestDmaWalkBits
( levels, writes, walk_ones,
seed) );<br>
</b></tt>
</b>
<blockquote>Walk 1’s: Test SI DMA
Writes with starting addresses defined by the bit sequence below (r stands
for random). Do this in separate loops for x36 addresses and x64 addresses.<br>
<br>
<span style="font-family: "Courier New"; ">
00000000000000000000000000000000<br>
00000000000000000000000000001000<br>
0000000000000000000000000001r000<br>
000000000000000000000000001rr000<br>
00000000000000000000000001rrr000<br>
0000000000000000000000001rrrr000<br>
<span style="mso-spacerun:yes"> </span><span style="mso-spacerun:yes">
</span>:<br>
0000000001rrrrrrrrrrrrrrrrrrr000<br>
000000001rrrrrrrrrrrrrrrrrrrr000<br>
00000001rrrrrrrrrrrrrrrrrrrrr000<br>
00000010rrrrrrrrrrrrrrrrrrrrr000</span><br>
<br>
</blockquote>
<b> <tt><b>TEST( 16, 3, SiTestDmaWalkBits
( levels, reads, walk_ones,
seed) );<br>
</b></tt>
</b>
<blockquote>Walk 1’s: Test SI DMA
Reads with starting addresses defined by the bit sequence below (r stands
for random). Do this in separate loops for x36 addresses and x64 addresses.<br>
<br>
<span class="SpellE"></span><span style="font-family: "Courier New"; ">
00000000000000000000000000000000<br>
00000000000000000000000000001000<br>
0000000000000000000000000001r000<br>
000000000000000000000000001rr000<br>
00000000000000000000000001rrr000<br>
0000000000000000000000001rrrr000<br>
<span style="mso-spacerun:yes">
</span><span style="mso-spacerun:yes"> </span>:<br>
0000000001rrrrrrrrrrrrrrrrrrr000<br>
000000001rrrrrrrrrrrrrrrrrrrr000<br>
00000001rrrrrrrrrrrrrrrrrrrrr000<br>
00000010rrrrrrrrrrrrrrrrrrrrr000</span><br>
<br>
</blockquote>
<b> <tt><b>TEST( 17, 1, SiTestDmaWalkBits
( levels, writes, walk_zeros,
seed) );<br>
</b></tt>
</b>
<blockquote>Walk 0’s: Test SI
DMA Writes with starting addresses defined by the bit sequence below (r
stands for random). Do this in separate loops for x36 addresses and x64
addresses.</blockquote>
<blockquote><span style="font-family: "Courier New"; ">
00000010111111111111111111100000</span><br>
<span style="font-family: "Courier New"; ">
000000101111111111111111110rr000</span><br>
<span style="font-family: "Courier New"; ">
00000010111111111111111110rrr000</span><br>
<span style="font-family: "Courier New"; ">
0000001011111111111111110rrrr000</span><br>
<span style="font-family: "Courier New"; ">
000000101111111111111110rrrrr000</span><br>
<span style="font-family: "Courier New"; ">
00000010111111111111110rrrrrr000</span><br>
<span style="font-family: "Courier New"; "><span style="mso-spacerun:yes">
</span><span style="mso-spacerun:yes"> </span>:</span><br>
<span style="font-family: "Courier New"; ">
0000001010rrrrrrrrrrrrrrrrrrr000</span><br>
<span style="font-family: "Courier New"; ">
000000100rrrrrrrrrrrrrrrrrrrr000</span><br>
<span style="font-family: "Courier New"; ">
00000010rrrrrrrrrrrrrrrrrrrrr000</span><br>
<span style="font-family: "Courier New"; ">
0000000rrrrrrrrrrrrrrrrrrrrrr000</span><br>
<b> <br>
<span style="font-family: "Courier New"; "><o:p></o:p></span></b></blockquote>
<b>
</b>
<blockquote></blockquote>
<b> <tt><b>TEST( 18, 1, SiTestDmaWalkBits
( levels, reads, walk_zeros,
seed) );<br>
</b></tt>
</b>
<blockquote>Walk 0’s: Test
SI DMA Reads with starting addresses defined by the bit sequence below
(r stands for random). Do this in separate loops for x36 addresses and
x64 addresses.<br>
<br>
<span style="font-family: "Courier New"; ">
00000010111111111111111111100000</span><br>
<span style="font-family: "Courier New"; ">
000000101111111111111111110rr000</span><br>
<span style="font-family: "Courier New"; ">
00000010111111111111111110rrr000</span><br>
<span style="font-family: "Courier New"; ">
0000001011111111111111110rrrr000</span><br>
<span style="font-family: "Courier New"; ">
000000101111111111111110rrrrr000</span><br>
<span style="font-family: "Courier New"; ">
00000010111111111111110rrrrrr000</span><br>
<span style="font-family: "Courier New"; "><span style="mso-spacerun:yes">
</span><span style="mso-spacerun:yes"> </span>:</span><br>
<span style="font-family: "Courier New"; ">
0000001010rrrrrrrrrrrrrrrrrrr000</span><br>
<span style="font-family: "Courier New"; ">
000000100rrrrrrrrrrrrrrrrrrrr000</span><br>
<span style="font-family: "Courier New"; ">
00000010rrrrrrrrrrrrrrrrrrrrr000</span><br>
<span style="font-family: "Courier New"; ">
0000000rrrrrrrrrrrrrrrrrrrrrr000</span><br>
<br>
<span style="font-family: "Courier New"; "><o:p></o:p></span></blockquote>
<b> <tt><b>TEST( 19, 1,
SiTestRandom
( 5, ForceFail_None, StartWithXs,
seed) );</b></tt>
</b>
<blockquote>Do SI DMA
tests with random values for addresses, expected ctrlr buttons, x, y, type,
and status.<br>
no forced failures, write Xs to start regs<br>
num_random_tests: 5<br>
<b> <br>
</b></blockquote>
<b> <tt><b>TEST( 20,
2, SiTestRandom
( 10, ForceFail_None, 0,
seed) );<br>
</b></tt>
</b>
<blockquote>Do SI DMA
tests with random values for addresses, expected ctrlr buttons, x, y, type,
and status.<br>
no forced failures<br>
num_random_tests: 10<br>
<b> <br>
</b></blockquote>
<b> <tt><b>TEST( 21,
3, SiTestRandom
( 10, ForceFail_Random, 0,
seed) );<br>
</b></tt>
</b>
<blockquote>Do SI
DMA tests with random values for addresses, expected ctrlr buttons, x, y,
type, and status.<br>
Use random forced failures for each controller.<br>
num_random_tests: 10<br>
<b> <br>
</b></blockquote>
<b> <tt><b>TEST(
22, 2, SiTestRandom
( 10, ForceFail_None, JChannel_Resp_Rand,
seed) );<br>
</b></tt>
</b>
<blockquote> Do
SI DMA tests with random values for addresses, expected ctrlr buttons, x,
y, type, and status.<br>
no forced failures, enable response randomization<br>
num_random_tests: 10<br>
<b> <br>
</b></blockquote>
<b> <tt><b>TEST(
23, 2, SiTestLCtrlJSRST
( levels, 0,
0,
seed) );<br>
</b></tt>
</b>
<blockquote>
Set local ctrlr L, R, and START at same time to reset stick reference<br>
Start with x,y non-zero and verify that after JSRST, x,y goes to zero.<br>
Verify that button status H[7] (i.e. JSRST) gets set.<br>
<b> <br>
</b></blockquote>
<b> <tt><b>TEST(
24, 1, SiTestLCtrlButRate ( levels, num_tests = default</b></tt><tt><b>
, random_rates = false, seed) );</b></tt>
</b>
<blockquote>
<b>
</b>
<p>Verify
for several rates that local controller buttons values set via the backdoor
are seen in DMA button query within 3 button sample periods. With
the backdoor writes sync'd to the sample times so the writes are just
after a sample time, verify that the expected values do not show earlier
than 25 us before 3 button sample periods and do show up no more than
25 us after 3 sample periods.</p>
<p>Use sample
rates with but_rate 1, 2 (i.e the default), and 10. The but_rate 0
case is special because it is so fast that we expect the change to be seen
with no need for any explicit wait time.</p>
<p>Other
rates can be specified in the default rates array or by function argument.
Slower rates require a long time to perform the test.<br>
</p>
<p>Sync with
button samples by disable button samples, set button rate, enable button
samples. Then, for each test at this rate, set button value via backdoor,
read at 100 us before 3 button sample periods and keep reading as
fast as possible until the change is seen. Since the writes
are sync'd to happen just after a button sample, the change should be seen
close to 3 button periods after the write.</p>
<p>Do 2 tests
per but_rate or as specified by argument.<br>
</p>
</blockquote>
<b><tt><b><br>
TEST( 25, 1, SiTestLCtrlJsxy
( levels, LCTRL_SOMEJITTER, 0,
seed) );<br>
</b></tt>
</b>
<blockquote>
<b>
</b>
<p>Test
local controller X,Y movement</p>
<p> For
(+x, -y), (+x, +y), (-x, -y), and (-x, +y) counts:</p>
<blockquote>
cmd via bd to move part way to limit,<br>
do button request until dest reached<br>
and no movement verified after reached<br>
cmd via bd to move past the limit,<br>
do button request until dest reached<br>
and no movement verified after reached<br>
cmd via bd to move part way away from limit<br>
do button request until dest reached<br>
and no movement verified after reached</blockquote>
<p> Use
jitter mask 0xFF during the tests to give jitter up to 256 ns added to pulse
timing values.</p>
<p> When
checking local controller X,Y movement during any test, verifies that the
expected X,Y is reached within the expected max time and that the position
doesn't change after reaching the expected position until the next backdoor
X,Y move commands are issued. During movement, each X,Y sample is
checked to see that it is moving closer to the target values. Once
an X,Y movement is started during a test, no new X,Y movement backdoor cmds
will be issued until the previous movement has been completely verified
or a reset has been performed. When resets are commanded, it is verified
that X,Y goes to and stays at 0.<br>
<b><br>
</b></p>
<b> </b></blockquote>
<b> <tt><b>
TEST( 26, 2, SiTestRandom
( 1, ForceFail_ClearSiIntMask, 0,
seed) );<br>
</b></tt>
</b>
<blockquote>
Test that when the SI interrupt mask bit is not set in the MI_INTR_MASK_REG,
the interrupt does not show up in the lsb of int_l.<br>
<br>
All other DMA tests verify that the int does appear if the SI interrupt
mask bit is set.<br>
<br>
num_random_tests: 1<br>
<b>
<br>
</b></blockquote>
<b> <b><tt>
TEST( 27, 2, SiTestLCtrlButDeglitch ( levels, </tt></b><tt><b>
button_rate = 1</b></tt><b><tt>,
0, seed) );<br>
</tt></b>
</b>
<blockquote>
<b>
</b>
<p>
Test local controller button sample deglitching.</p>
<p>
Set buttons to 0<br>
Set button rate to 1 or as specifed by argument<br>
Use default jc_div = 31, tXfer = tHigh = tLow = 2000, jitter = 0<br>
Set buttons on via bd for 1.25 sample period, verify no change in button
state<br>
Set buttons off via bd, verify no change in button state<br>
Verify buttons don't show up in dma button query within the max time
they would have shown up if we didn't turn them off.<br>
Set buttons on for 2.25 sample period, verify they don't show as on<br>
set buttons off, verify they don't show as on<br>
Verify buttons don't show up in dma button query within the max time
they would have shown up if we didn't turn them off.
</p>
</blockquote>
<br>
<b><b><tt>
TEST( 28, 2, SiTestLCtrlJsxyDeglitch</tt><tt> ( levels,
0,
0,
seed) )<b><b><tt>;<br>
</tt></b></b></tt></b></b>
<blockquote>
<p>
Test local controller X,Y sample deglitching.</p>
</blockquote>
<blockquote>
Set x,y to 0<br>
Use default jc_div = 31, tXfer = tHigh = tLow = 2000,<br>
jitter
= 0<br>
Cause xglitch=0x01 via backdoor, verify no change in x,y state<br>
Cause xglitch=0x10 via backdoor, verify no change in x,y state<br>
Cause yglitch=0x01 via backdoor, verify no change in x,y state<br>
Cause yglitch=0x10 via backdoor, verify no change in x,y state</blockquote>
<b><b><tt><br>
TEST( 30, 2, SiTestBugFixes</tt><tt>
( levels, 0,
0,
seed) )<b><b><tt>;<br>
</tt></b></b></tt></b></b>
<blockquote>
<p>
This test is for testing specific miscellaneous bug fixes. It can
be used to test fixes for bugs that show up for random values that may or
may not occur in other tests.</p>
</blockquote>
<blockquote>
It currently tests the fix for bug bug 1481 - SI lctrl error bits anomaly
for unsupported cmd with invalid tx size<br>
</blockquote>
<br>
<b><b><tt> TEST( 31, 2, SiTest</tt><tt>Slave
( levels, 0,
0,
seed) )<b><b><tt><b><b><tt>;<br>
</tt></b></b></tt></b></b></tt></b></b>
<blockquote>
<p>
Using Bill's master model, in slave mode setup jctrl 1 to receive cmds
from the master. Request the master model to send each of the valid
cmds (0,1,255), get the response from the local controller, prepare
and transmit the response to the master, retrieve and verify the data received
by the master. Test getting the lctrl response in a separate DMA after
receiving the cmd from the master. Test getting the lctrl response
for button/joystick x,y in the same DMA in which the master cmd is received.</p>
<p>
While doing slave mode transactions verify expected behavior of all assoiated
register bits and interrupts. This includes at least, SI_CONFIG JC_SLAVE,
SI_CTRL XMIT, BUSY, REQ, SI_STATUS bits assoiated with DMA's used during
slave mode transactions, and interrupt indications.</p>
</blockquote>
<blockquote>
<p>
Test Joy Channel resets commanded by master while in slave mode. <br>
</p>
</blockquote>
<blockquote>
<ol>
<li> with rcv active (before cmd rqstd) start a reset, after reset
should have completed, check, should get reset error bit set (plus maybe
no response)</li>
<li> with rcv active (before cmd rqstd) start a reset, after it should
have completed, rqst cmd and check, should get reset error bit set (plus
maybe no response</li>
<li> with rcv active (before cmd rqstd) start a reset, during reset,
check, should get reset error bit set (plus maybe no response)</li>
<li> before start cmd receive start a reset, start rcv during reset,
check, should get reset error bit set</li>
<li> reset during reception of a cmd from the master, (use Franks backdoor
reset for this one</li>
</ol>
Using Frank's master model:
</blockquote>
<blockquote>
<ol>
<li> Use the backdoor rsp_random setting to test randomly stretched
bit pulses within the spec limits.</li>
<li> Use the backdoor to generate bit timing violations to test the
frame error detection. Verify that the frame error bit gets set.</li>
<li> Use the backdoor to disable the master model during a command
transmition to the slave to test truncated commands. Verify that truncated
commands cause a no response error and that a good command can be
received after 64us.</li>
<li> Use the backdoor to force a collision during trasnmission of the
slave response to the master. Verify that the collision error is indicated
in the error bits.</li>
<li> Verify that the SI can receive random commands in the range 4
to 254 with the number of bytes received indicated by bits [2:0] of the
cmd.<br>
</li>
</ol>
</blockquote>
<blockquote><b><br>
</b></blockquote>
<br>
<b>
<br>
<br>
<br>
</b>
<p><b><br>
</b></p>
<b>
</b>
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