/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: tc.v,v 1.1.1.1 2002/05/17 06:14:58 blythe Exp $
////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: tc
// description: Texture Coordinate Unit
//
// designer: Tony DeLaurier
// date: 7/6/94
//
////////////////////////////////////////////////////////////////////////
module tc (gclk, st_span, ncyc, s, t, w, min_level, detail_en, sharp_en,
lod_en, persp_en, copy, samp_type, tlut_en, max_level, prim_tile,
load, shift_coord, tile_adrs, tile_data, we_tile_size, we_tile_attr,
clr_ind_a, clr_ind_b, clr_ind_c, clr_ind_d, l_frac,
s_frac_rg, t_frac_rg, s_frac_ba, t_frac_ba, adrs_bnk0l,
adrs_bnk1l, adrs_bnk2l, adrs_bnk3l, adrs_bnk0h, adrs_bnk1h,
adrs_bnk2h, adrs_bnk3h, adrs_a, adrs_b_ba, adrs_c, adrs_d_ba,
adrs_b_rg, adrs_d_rg, swap_rg, swap_ba, tile_tex_type_1d,
tile_tex_size_1d, palette, odd_t, a_three, a_twelve);
input gclk; // RDP gated clock
input st_span; // start span
input ncyc; // 0: 1-cycle mode, 1: 2-cycle mode
// pixel data
input [15:0] s; // persp. divided texture image coord.
input [15:0] t; // persp. divided texture image coord.
input [15:0] w; // inverse normalized depth
// attribute data
input [4:0] min_level; // minimum lod fraction clamp
input detail_en; // enable detailed texture
input sharp_en; // enable sharpened texture
input lod_en; // use lod in tile indices determination
input persp_en; // enable perspective correction
input copy; // copy mode enabled
input samp_type; // filter enabled
input tlut_en; // enable texture lookup table
// primitive data
input [2:0] max_level; // number of mipmaps -1 or -2
input [2:0] prim_tile; // base tile index of primitive
input load; // load_tile, load_block or load_tlut
input shift_coord; // treat coord as 12.3 instead of 10.5
// from command interface unit
input [2:0] tile_adrs; // tile write address
input [47:0] tile_data; // tile input data
input we_tile_size; // write enable for tile size data
input we_tile_attr; // write enable for tile attribute data
// from texture memory unit
input [7:0] clr_ind_a; // color index texel a
input [7:0] clr_ind_b; // color index texel b
input [7:0] clr_ind_c; // color index texel c
input [7:0] clr_ind_d; // color index texel d
// to color combine unit
output [8:0] l_frac; // lod fraction for 3rd-axis interpolation
// to texture filter unit
output [7:0] s_frac_rg; // s interp fraction to filter (RG)
output [7:0] t_frac_rg; // t interp fraction to filter (RG)
output [7:0] s_frac_ba; // s interp fraction to filter (BA)
output [7:0] t_frac_ba; // t interp fraction to filter (BA)
// to texture memory unit
output [7:0] adrs_bnk0l; // sorted address to low bank 0
output [7:0] adrs_bnk1l; // sorted address to low bank 1
output [7:0] adrs_bnk2l; // sorted address to low bank 2
output [7:0] adrs_bnk3l; // sorted address to low bank 3
output [7:0] adrs_bnk0h; // sorted address to high bank 0
output [7:0] adrs_bnk1h; // sorted address to high bank 1
output [7:0] adrs_bnk2h; // sorted address to high bank 2
output [7:0] adrs_bnk3h; // sorted address to high bank 3
output [4:0] adrs_a; // address of texel a <12,3:0>
output [4:0] adrs_b_ba; // address of texel b (ba banks) <12,3:0>
output [4:0] adrs_c; // address of texel c <12,3:0>
output [4:0] adrs_d_ba; // address of texel d (ba banks) <12,3:0>
output [4:0] adrs_b_rg; // address of texel b (rg banks) <12,3:0>
output [4:0] adrs_d_rg; // address of texel d (rg banks) <12,3:0>
output swap_rg; // swap texels (RG)
output swap_ba; // swap texels (BA)
output [2:0] tile_tex_type_1d;// tile_tex_type delayed 1 cycle
output [1:0] tile_tex_size_1d;// tile_tex_size delayed 1 cycle
output [3:0] palette; // palette for 4-bit color index
output odd_t; // odd line
output a_three; // base_address[3]
output a_twelve; // address a[12]
// tile data
wire [3:0] shift_s; // right shift
wire [3:0] shift_t; // right shift
wire [11:0] sl; // tile offset in image space
wire [11:0] tl; // tile offset in image space
wire [11:0] sh; // tile end in image space
wire [11:0] th; // tile end in image space
wire [3:0] mask_s; // coord. mask
wire [3:0] mask_t; // coord. mask
wire mir_s; // enable mirror
wire mir_t; // enable mirror
wire clamp_s; // coord. clamp enabled
wire clamp_t; // coord. clamp enabled
wire [8:0] line; // line width in 64-bit words
wire [8:0] tmem_adrs; // tmem start address
wire [2:0] tile_tex_type; // tile texel type
wire [1:0] tile_tex_size; // tile texel size
// wires
wire persp_dis; // perspective divide disabled
wire [18:0] s_w; // s over w (over, under, s,11.5)
wire [18:0] t_w; // t over w
wire [15:0] s_clamped; // s clamped
wire [15:0] t_clamped; // t clamped
wire [2:0] l_tile; // tile index into tile memory
wire load_8d; // load delayed 8 cycles
wire load_9d; // load delayed 9 cycles
wire load_10d; // load delayed 10 cycles
wire [12:0] s_adrs; // passed to address module
wire [12:0] t_adrs; // passed to address module
wire [4:0] s_frac; // fraction passed to fraction module
wire [4:0] t_frac; // fraction passed to fraction module
wire mask_en_s; // mask enabled s
wire mask_en_t; // mask enabled t
wire [3:0] s_all_one; // s all ones -0, -1 , -2, -3
wire [3:0] s_all_zero; // s all zeros +0, +1, +2, +3
wire [3:0] t_all_one; // t all ones
wire [3:0] t_all_zero; // t all zeros
wire wrap_bit_s; // s wrap bit
wire wrap_bit_t; // t wrap bit
wire [12:0] a; // address A before interleave
wire [12:0] b_adder; // address B adder input
wire [12:0] c_adder; // address C adder input
wire [12:0] d_adder; // address D adder input
wire shift; // shift B_rg and D_rg address deltas
wire flip; // flip address C and D interleave bit
wire yuv_tex; // tile texel type is yuv
wire copy_1d; // copy delayed 1 cycle
// instance divide module
assign persp_dis = !persp_en || load;
tc_div div (.w(w), .s(s), .t(t), .dis(persp_dis),
.gclk(gclk), .sw_out(s_w), .tw_out(t_w));
// instance lod module
tc_lod lod (.gclk(gclk), .s(s_w), .t(t_w), .st_span(st_span), .ncyc(ncyc),
.min_level(min_level), .max_level(max_level),
.detail_en(detail_en), .sharp_en(sharp_en), .lod_en(lod_en),
.prim_tile(prim_tile), .load(load), .tlut_en(tlut_en),
.l_frac_out(l_frac), .l_tile(l_tile),
.load_8d(load_8d), .load_9d(load_9d), .s_clamped(s_clamped), .t_clamped(t_clamped));
// instance tile memory module
tc_tilemem tilemem (.gclk(gclk), .tile_adrs(tile_adrs), .tile_data(tile_data),
.we_tile_size(we_tile_size), .we_tile_attr(we_tile_attr),
.l_tile(l_tile), .tex_type_2d(tile_tex_type),
.tex_size_2d(tile_tex_size), .line_2d(line),
.tmem_adrs_2d(tmem_adrs), .palette_4d(palette),
.clamp_t_1d(clamp_t), .mir_t_1d(mir_t),
.mask_t_1d(mask_t), .shift_t(shift_t),
.clamp_s_1d(clamp_s), .mir_s_1d(mir_s),
.mask_s_1d(mask_s), .shift_s(shift_s), .sl(sl), .sh(sh),
.tl(tl), .th(th));
// instance coordinate adjust modules
tc_adj adj_s (.gclk(gclk), .c_w(s_clamped), .load_8d(load_8d), .load_9d(load_9d),
.shift_c(shift_s), .cl(sl), .ch(sh), .mask_c(mask_s),
.mir_c(mir_s), .shift_coord(shift_coord), .clamp_c(clamp_s),
.copy(copy), .c_adrs(s_adrs), .c_frac_1d(s_frac),
.mask_en_1d(mask_en_s), .c_all_zero(s_all_zero),
.c_all_one(s_all_one), .wrap_bit_1d(wrap_bit_s));
tc_adj adj_t (.gclk(gclk), .c_w(t_clamped), .load_8d(load_8d), .load_9d(load_9d),
.shift_c(shift_t), .cl(tl), .ch(th), .mask_c(mask_t),
.mir_c(mir_t), .shift_coord(shift_coord), .clamp_c(clamp_t),
.copy(copy), .c_adrs(t_adrs), .c_frac_1d(t_frac),
.mask_en_1d(mask_en_t), .c_all_zero(t_all_zero),
.c_all_one(t_all_one), .wrap_bit_1d(wrap_bit_t));
// instance address module
tc_adrs adrs (.gclk(gclk), .tex_type(tile_tex_type),
.tex_size(tile_tex_size), .s_adrs(s_adrs), .t_adrs(t_adrs),
.line(line), .tmem_adrs(tmem_adrs), .load_9d(load_9d),
.copy(copy), .samp_type(samp_type),
.mask_en_s(mask_en_s), .mask_en_t(mask_en_t),
.mir_s(mir_s), .mir_t(mir_t), .s_all_one(s_all_one),
.wrap_bit_s(wrap_bit_s), .s_all_zero(s_all_zero),
.t_all_one(t_all_one[0]), .wrap_bit_t(wrap_bit_t),
.t_all_zero(t_all_zero[0]), .a(a), .b_adder(b_adder),
.c_adder(c_adder), .d_adder(d_adder), .shift(shift),
.flip(flip), .odd_t(odd_t), .yuv_tex_1d(yuv_tex),
.load_10d(load_10d), .copy_1d(copy_1d),
.tex_type_1d(tile_tex_type_1d), .tex_size_1d(tile_tex_size_1d),
.a_three(a_three));
assign a_twelve = a[12];
// instance fraction module
tc_frac frac (.gclk(gclk), .s_frac(s_frac), .t_frac(t_frac),
.copy_1d(copy_1d), .yuv_tex(yuv_tex), .a_byte(a[1]), .tlut_en(tlut_en),
.s_frac_ba_out(s_frac_ba), .t_frac_ba_out(t_frac_ba),
.s_frac_rg_out(s_frac_rg), .t_frac_rg_out(t_frac_rg),
.swap_ba_1d(swap_ba), .swap_rg_1d(swap_rg));
// instance address sort module
tc_sort sort (.gclk(gclk), .a(a), .b_adder(b_adder), .c_adder(c_adder),
.d_adder(d_adder), .shift(shift), .odd_t(odd_t),
.flip(flip), .tlut_en(tlut_en), .load_10d(load_10d),
.clr_ind_a(clr_ind_a), .clr_ind_b(clr_ind_b),
.clr_ind_c(clr_ind_c), .clr_ind_d(clr_ind_d),
.adrs_bnk0l(adrs_bnk0l), .adrs_bnk1l(adrs_bnk1l),
.adrs_bnk2l(adrs_bnk2l), .adrs_bnk3l(adrs_bnk3l),
.adrs_bnk0h(adrs_bnk0h), .adrs_bnk1h(adrs_bnk1h),
.adrs_bnk2h(adrs_bnk2h), .adrs_bnk3h(adrs_bnk3h),
.adrs_a_1d(adrs_a), .adrs_b_ba_1d(adrs_b_ba),
.adrs_c_1d(adrs_c), .adrs_d_ba_1d(adrs_d_ba),
.adrs_b_rg_1d(adrs_b_rg), .adrs_d_rg_1d(adrs_d_rg));
endmodule // tc