/*********************************************************/
/*                                                       */
/* kp13ts64_r01w01_70c3p                                */
/*                                                       */
/* Verilog model for 32kx8 XPM embedded module.          */
/* Parallel(8-bit) program, Parallel(8-bit) read         */
/*                                                       */
/* Created by: Chung Eng     chungeng@kilopass.com       */
/* version 1.0               Feb 11, 2005                */
/* version 1.1               April 19, 2005              */
/* version 1.2               July 22, 2005               */
/* version 1.3               Aug. 03, 2005               */
/*                                                       */
/* Modified by: Jason Chen   j.chen@kilopass.com         */
/* version 1.4               Aug 04, 2005                */
/*                                                       */
/*                                                       */
/*                                                       */
/* 1.0 -- initial version.                               */
/* 1.1 -- added warning message and enhanced timing check*/
/* 1.2 -- fixed timing in specify.                       */
/*        added function to prohibit 0 overwritten 1.    */
/*        changed output to undefine data to tOHA, tOHRE,*/
/*        and tOHCEB.                                    */
/*        added warning message while READEN is < tACC.  */
/* 1.3 -- added addr to fuse sensitivity list.           */
/*        added tCSRST. removed tCES. changed tRSCEB to  */
/*        tRSRD.                                         */
/*        enhanced checking maximum CPUMPEN assertion.   */
/*        checked A[n:9] in WRTEST model.                */
/* 1.4 -- update release changes                         */
/*                                                       */
/*                                                       */
/* This software and documentation is the confidential   */
/* and proprietary information of Kilopass Technology,   */
/* Inc ("Kilopass"). ("Confidential Information").       */
/* You shall not disclose such Confidential Information  */
/* and shall use it only in accordance with the terms of */
/* the license agreement you entered into with Kilopass. */
/*                                                       */
/* KILOPASS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT */
/* THE SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR    */
/* IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED     */
/* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A          */
/* PARTICULAR PURPOSE, OR NON-INFRINGEMENT. KILOPASS     */
/* SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY       */
/* LICENSEE AS A RESULT OF USING, MODIFYING OR           */
/* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.        */
/*                                                       */
/* Developed by Kilopass Technology, Inc., California    */
/* USA For inquiries, contact us via information posted  */
/* on www.kilopass.com                                   */
/*                                                       */
/* Copyright (c) 2002 - 2005 Kilopass Technology, Inc.   */
/* All rights reserved.                                  */
/*                                                       */
/*********************************************************/
//Thu Aug  4 15:08:35 PDT 2005

`timescale 1ns / 1ns
`celldefine

module kp13ts64_r01w01_70c3p
         (
	  D, A, DIN, CEB, CLE, DLE,
          PGMEN, READEN, RSTB, WEB, CPUMPEN 
         );

parameter DATA_WIDTH  = 1;
parameter ADDR_WIDTH  = 16;
parameter TADDR_WIDTH = 9;
parameter CADDR_WIDTH = 9;

parameter XPM_DEPTH    = 1 << ADDR_WIDTH;
parameter WRTEST_DEPTH = 1 << TADDR_WIDTH;

parameter TDEC   = 5;
parameter WRTEST = 2;

parameter CLOCK_PERIOD = 2;
parameter TACC = 70;

output 	       D;             // data out
input  [ADDR_WIDTH-1:0] A;    // address 
input  	       DIN;	      // data in
input          CEB;           // chip enable, active low
input          CLE;           // command latch enable
input          DLE;           // data latch enable
input          PGMEN;         // program enable
input          READEN;        // read enable
input          RSTB;          // reset, active low
input          WEB;           // data latch wen and program wen, active low
input          CPUMPEN;       // charge pump enable high

wire           din;           // data input
wire   [ADDR_WIDTH-1:0] addr; // address 
wire   [TADDR_WIDTH-1:0] taddr;// address for test array
wire           rd_en;         // read enable
wire           pg_en;         // program enable
wire           ceb;           // chip enable, active low
wire           dle;           // data latch enable
wire           cle;           // command latch enable
wire           rstb;          // reset, active low
wire           web;           // data latch wen and program wen, active low
wire           cpumpen;       // charge pump enable.

reg            dout;
reg            mem [XPM_DEPTH-1:0]; // memory array
reg            tmem [WRTEST_DEPTH-1:0]; // 512 x 8 test (spare) mem array
reg            ckrboard [XPM_DEPTH-1:0]; // checkerboard for testdec read mode
reg            d_latch;  // data latch for program
reg    [CADDR_WIDTH-1:0] c_latch; // cmd latch for test mode

reg            tdec_latch;
reg            twr_latch;

reg            tm_tdec;
reg            tm_twr;

reg            read_op;
reg            prog_op;
reg            latch_pg_data;
reg            latch_cmd;
reg            cmd_en;

reg    [ADDR_WIDTH-1:0] ckaddr;

reg            tprob;
reg            prog_data;
reg            fuse;
reg            fbit;
reg            valid_fuse;
reg           invalid_taddr;
reg    [5:0]  msb_addr;

reg  [5:0]     count;
reg            rclk;
reg  [ADDR_WIDTH-1:0] dly1;
reg  [ADDR_WIDTH-1:0] dly2;
reg  [ADDR_WIDTH-1:0] a_latch;
reg            p1;
reg            new_addr;
reg            xr15;
reg            xr14;
reg            xr13;
reg            xr12;
reg            xr11;
reg            xr10;
reg            xr9;
reg            xr8;
reg            xr7;
reg            xr6;
reg            xr5;
reg            xr4;
reg            xr3;
reg            xr2;
reg            xr1;
reg            xr0;
reg            addr_toggle;
reg            valid_rd;
reg            invalid_rd;
reg            douti;
reg            m0;
reg            m1;
reg            mpulse;
reg            rdly1;
reg            rdly2;

wire           axr15;
wire           axr14;
wire           axr13;
wire           axr12;
wire           axr11;
wire           axr10;
wire           axr9;
wire           axr8;
wire           axr7;
wire           axr6;
wire           axr5;
wire           axr4;
wire           axr3;
wire           axr2;
wire           axr1;
wire           axr0;
wire           addr_chg;

integer        f, g;

parameter DEL  = 1,
          DEL2 = 2,
          HIGH = 1,
          LOW  = 0,
          LOWs  = 8'h00,
          HIGHs = 8'hFF;

initial  // initialize the memory cells to be all 0's
         // checkerboard 4-FF's and 4-00's. 
   begin
   mem_initial;
   output_initial;
   regs_initial;
   end

//-----------------------------
//
// buffering
//
//-----------------------------

assign  din     = DIN;
assign  addr    = A;
assign  taddr   = A[TADDR_WIDTH-1:0];
assign  rd_en   = READEN;
assign  pg_en   = PGMEN;
assign  ceb     = CEB;
assign  dle     = DLE;
assign  cle     = CLE;
assign  rstb    = RSTB;
assign  web     = WEB;
assign  cpumpen = CPUMPEN;

//-----------------------------
//
// Data output 
//
//-----------------------------
wire dout_i = douti;  

buf (D, dout_i);

//-----------------------------
//
// operation definitions
//
//-----------------------------
always @(ceb or dle or cle or 
         web or rstb or rd_en or pg_en) begin
  if (~ceb) begin
    write_read_op;
  end
end

always @(ceb or addr) begin
  if (~ceb) begin
    check_fuse;
    wrtest_addr;
  end
end

//----------------------------
//
// memory cycle
//
//----------------------------
always @(addr or taddr or prog_op or read_op or ceb or
         tm_tdec or tm_twr or invalid_taddr ) begin : MEMORY_CYCLE
  casez ({prog_op, read_op})
    2'b00 : begin
      if (ceb) begin
        $display ("XPM is in stand by mode.");
      end
    end 
    2'b10 : begin
      write_test_and_mem;
    end
    2'b01 : begin
      read_tm_and_mem;
    end
    2'b11 : begin
      $display ("Invald operation to read while XPM programming.");
    end
    default: begin
      read_tm_and_mem;
    end
  endcase
end

//-----------------------------
//
// memory initial
//
//-----------------------------
task mem_initial;
integer iDFP;
integer iTFP;
integer iCKFP;

begin

  d_latch = 0;
  c_latch = 0;
  tdec_latch = 0;
  twr_latch = 0;
  tm_tdec = 0;
  tm_twr = 0;
  read_op = 0;
  prog_op = 0;
  latch_pg_data = 0;
  latch_cmd = 0;
  cmd_en = 0;
  tprob = 0;
  prog_data = 0;
  fuse = 0;
  fbit = 0;
  valid_fuse = 0; 
  invalid_taddr = 0;

// text file to load memory arrays
//  $readmemh ("../dv/mem_file.txt", mem);
//  $readmemh ("../dv/tmem_file.txt", tmem);
// initial memory to 0's
  for (iDFP=0; iDFP<XPM_DEPTH; iDFP=iDFP+1) mem[iDFP] = LOWs;
  for (iTFP=0; iTFP<WRTEST_DEPTH; iTFP=iTFP+1) tmem[iTFP] = LOWs;
  for (iCKFP=0; iCKFP<4096; iCKFP=iCKFP+1)  begin
    ckaddr = iCKFP;
    if (ckaddr[0]==1) begin : ODD_ADDRESS
      ckrboard[ckaddr] = HIGH;
    end
    if (ckaddr[0]==0) begin : EVEN_ADDRESS
      ckrboard[ckaddr] = LOW;
    end

  end
end
endtask

//-----------------------------
//
// outputs initial
//
//-----------------------------
task output_initial;
begin
     #0 dout = 'bx; // initialize the output
     #0 ckaddr = 0;
end
endtask

//-----------------------------
//
// write and read operations
//
//-----------------------------
task write_read_op;
begin
  read_op = ~dle & ~cle &  web & rstb & rd_en & ~pg_en;
  prog_op = ~dle & ~cle & ~web & rstb & ~rd_en & pg_en & cpumpen;
  latch_pg_data = dle & ~cle & ~web & rstb;

  cmd_en = cle & ~pg_en & ~dle;
  latch_cmd = cmd_en & ~web & rstb;

  latches_reset;
  latch_tm_cmd;
  latch_prog_data;
end
endtask

//-----------------------------
//
// latch test command (9 modes)
//
//-----------------------------
task latch_tm_cmd;
begin
  if (latch_cmd)  begin : LOAD_ADDR_TO_C_LATCH
    c_latch = addr[CADDR_WIDTH-1:0];

    tdec_latch = addr[TDEC];  // addr bit 5
    twr_latch  = addr[WRTEST];// addr bit 2
    
    test_modes;
  end 
end
endtask

//----------------------------
//
// generate test modes
//
//-----------------------------
task test_modes;
begin
  if (tdec_latch & cle) begin
    @ (posedge web) begin
       tm_tdec <= c_latch[TDEC];
    end
  end
  if (twr_latch & cle) begin
    @ (posedge web) begin
      tm_twr <= c_latch[WRTEST];
    end
  end
end
endtask

//----------------------------
//
// check wrtest mode address
//
//-----------------------------
task wrtest_addr;
begin
  if (tm_twr) begin
    invalid_taddr = (|addr[ADDR_WIDTH-1:TADDR_WIDTH] === 1'b1);
    if (invalid_taddr) begin
      $display ("\n Invalid address in WRTEST mode, A[n:9] must be 0's.");
    end
  end
end
endtask

//-----------------------------
//
// reset data latch and cmd latch
//
//-----------------------------
task latches_reset;
begin
  if (~rstb) begin : LATCHES_RESET
    d_latch = 'b0;
    c_latch = 'b0;

    tdec_latch = 0;
    twr_latch = 0;

    tm_tdec = 0;
    tm_twr  = 0;

    prog_data = 0;
    fuse = 0;

    invalid_taddr = 0;

    test_modes;
  end
end
endtask

//-----------------------------
//
// check fused bits
//
//-----------------------------
task check_fuse;
begin
  if (~ceb) begin
    if (tm_twr) begin
      if (~invalid_taddr) begin
        fbit = tmem[taddr];
      end
    end
    else begin
      fbit = mem[addr];
    end
    valid_fuse = (^(fbit) !== 1'bx);
    if (valid_fuse) begin
      fuse = fbit;
    end
    else begin
      fuse = 0;
    end
  end
end
endtask

//-----------------------------
//
// latch program data
//
//-----------------------------
task latch_prog_data;
begin
  if (latch_pg_data) begin : LOAD_DIN_TO_D_LATCH
    if (tm_twr) begin
      d_latch = din | fuse;
    end
    else begin
      d_latch = din | d_latch | fuse;
    end
  end
end
endtask

//-----------------------------
//
// write test mode and memory
//
//-----------------------------
task write_test_and_mem;
begin
  if (prog_op) begin : WRITE
    if (tm_twr) begin : WRTEST_MODE
      if (~invalid_taddr) begin
        tmem[taddr] = d_latch;
      end
    end
    else begin : WRITE_MEM
      mem[addr] = d_latch;
      prog_data = d_latch; // for warning message
    end
  end
end
endtask

//-----------------------------
//
// read testdec, test write and memory 
//
//-----------------------------
task read_tm_and_mem;
begin
  if (read_op) begin : READ
    if (tm_tdec) begin : READ_TDEC
      dout = ckrboard[addr];   // read checkerboard
    end
    else 
    if (tm_twr) begin : READ_WRTEST_MODE
      if (~invalid_taddr) begin
        dout = tmem[addr];  // read write test mode
      end
    end
    else 
    begin : READ_MEM
      dout = mem[addr];
    end          
  end
end
endtask

//-----------------------------
//
// register initials
//
//-----------------------------
task regs_initial;
begin
  count = 0;
  rclk = 0;
  dly1 = 0;
  a_latch = 0;
  p1 = 0;
  new_addr = 0;
  xr15 = 0;
  xr14 = 0;
  xr13 = 0;
  xr12 = 0;
  xr11 = 0;
  xr10 = 0;
  xr9 = 0;
  xr8 = 0;
  xr7 = 0;
  xr6 = 0;
  xr5 = 0;
  xr4 = 0;
  xr3 = 0;
  xr2 = 0;
  xr1 = 0;
  xr0 = 0;
  addr_toggle = 0;
  valid_rd = 0;
  invalid_rd = 0;
  dout = 0;
  m0 = 0;
  m1 = 0;
  mpulse = 0;
end
endtask

//-----------------------------
//
// valid read pulse width.
//
//-----------------------------

always @ (ceb) begin : INTERNAL_CLOCK
  rclk = 0;
  if (~ceb) begin
    forever begin
      # (CLOCK_PERIOD/2)
      rclk = ~rclk;
    end
  end
end

always @ (posedge rclk or rstb) begin : LATCH_ADDR
  if (~rstb) begin
    a_latch <= 0;
  end
  else begin
    dly1 <= addr;
    dly2 <= dly1;
    a_latch <= dly2;
  end
end

always @ (negedge new_addr) begin : NEW_ADDR_RESET_XOR
  xr15 = 0;
  xr14 = 0;
  xr13 = 0;
  xr12 = 0;
  xr11 = 0;
  xr10 = 0;
  xr9 = 0;
  xr8 = 0;
  xr7 = 0;
  xr6 = 0;
  xr5 = 0;
  xr4 = 0;
  xr3 = 0;
  xr2 = 0;
  xr1 = 0;
  xr0 = 0;
end

always @ (addr or a_latch or rstb) begin : CHECK_ADDR
  if (~rstb) begin
    xr15 = 0;
    xr14 = 0;
    xr13 = 0;
    xr12 = 0;
    xr11 = 0;
    xr10 = 0;
    xr9 = 0;
    xr8 = 0;
    xr7 = 0;
    xr6 = 0;
    xr5 = 0;
    xr4 = 0;
    xr3 = 0;
    xr2 = 0;
    xr1 = 0;
    xr0 = 0;
  end
  else begin
    xr15 = addr[15]^a_latch[15];
    xr14 = addr[14]^a_latch[14];
    xr13 = addr[13]^a_latch[13];
    xr12 = addr[12]^a_latch[12];
    xr11 = addr[11]^a_latch[11];
    xr10 = addr[10]^a_latch[10];
    xr9 = addr[9]^a_latch[9];
    xr8 = addr[8]^a_latch[8];
    xr7 = addr[7]^a_latch[7];
    xr6 = addr[6]^a_latch[6];
    xr5 = addr[5]^a_latch[5];
    xr4 = addr[4]^a_latch[4];
    xr3 = addr[3]^a_latch[3];
    xr2 = addr[2]^a_latch[2];
    xr1 = addr[1]^a_latch[1];
    xr0 = addr[0]^a_latch[0];
  end
end

always @ (posedge rclk or rstb) begin : ADDR_TOGGLE
  if (~rstb) begin
    addr_toggle = 0;
  end
  else begin
    addr_toggle = |{
                    xr15, xr14, xr13, xr12,
                    xr11, xr10, xr9, xr8,
                    xr7,  xr6,  xr5, xr4,
                    xr3,  xr2,  xr1, xr0
                       };
  end
end

// asynchr address changes

   assign axr15 = addr[15]^a_latch[15];
   assign axr14 = addr[14]^a_latch[14];
   assign axr13 = addr[13]^a_latch[13];
   assign axr12 = addr[12]^a_latch[12];
   assign axr11 = addr[11]^a_latch[11];
   assign axr10 = addr[10]^a_latch[10];
   assign axr9 = addr[9]^a_latch[9];
   assign axr8 = addr[8]^a_latch[8];
   assign axr7 = addr[7]^a_latch[7];
   assign axr6 = addr[6]^a_latch[6];
   assign axr5 = addr[5]^a_latch[5];
   assign axr4 = addr[4]^a_latch[4];
   assign axr3 = addr[3]^a_latch[3];
   assign axr2 = addr[2]^a_latch[2];
   assign axr1 = addr[1]^a_latch[1];
   assign axr0 = addr[0]^a_latch[0];

   assign addr_chg = |{
                    axr15, axr14, axr13, axr12,
                    axr11, axr10, axr9,  axr8,
                    axr7,  axr6,  axr5,  axr4,
                    axr3,  axr2,  axr1,  axr0
                       };


always @ (posedge rclk or addr_toggle or
          rstb) begin : START_PULSE
  if (~rstb) begin
    p1 <= 0;
  end
  else begin
    p1 <= addr_toggle;
  end
  new_addr = addr_toggle & ~p1;
end

always @ (posedge rclk or invalid_rd or
          rstb) begin : MESSAGE_PULSE
  if (~rstb) begin
    m1 <= 0;
    m0 <= 0;
  end
  else begin
    m1 <= invalid_rd;
    m0 <= m1;
  end
  mpulse = invalid_rd & ~m0;
end

always @ (mpulse or count) begin : READ_WARNING
  if (mpulse & count == 6'h00) begin
    $display ("\n READEN assertion is less than access time, output data are in undefined value. %0t:", $time);
  end
end

always @ (posedge rclk or rd_en or rstb) begin
  if (~rstb) begin
    rdly1 <= 0;
    rdly2 <= 0;
  end
  else begin
    rdly1 <= rd_en;
    rdly2 <= rdly1;
  end
end

always @ (negedge rdly2 or ceb) begin : FALLING_READ_RESET
  if (ceb) begin
    count = 0;
  end
  else if (~rdly2) begin
    count = 0;
  end
end

always @ (posedge rclk) begin : SYN_RESET
  if (~rd_en) begin
    valid_rd = 0;
  end
end

always @ (posedge rclk or new_addr or rd_en or
          rstb) begin : VALID_READ
  if (new_addr | ~rstb | ceb) begin
    count = 0;
    valid_rd = 0;
    invalid_rd = 0;
  end
  else if (rd_en) begin : READ_COUNTER
    if (count == 6'h3F) begin
      count = count;
    end
    else begin
      count = count + 1;
    end
  end
  if (count >= TACC/2 - 1 & rd_en) begin: ACC_TIME 
    valid_rd = ~ceb;
  end
  else if (count >= 6'h02 & count <= TACC/2 &
           ~rd_en) begin: LESS_THAN_ACC 
    invalid_rd = 1;
  end
end

always @ (posedge rclk or valid_rd or invalid_rd
          or rstb or ceb) begin
  if (~rstb) begin
    douti <= 'bx;
  end
  else if (valid_rd) begin
    douti<= dout;
  end
  else if (invalid_rd | ~rd_en | ceb) begin: TOHRE_AND_TOHCEB
    douti <= 'bx;
  end
end

always @ (addr_chg) begin: TOHA
  if (addr_chg) begin
    douti <= 'bx;
  end
end

specify

  specparam rd_rise = 70;
  specparam rd_fall = 70;
  specparam rd_en_rise = 70;
  specparam rd_en_fall = 70; 
  specparam ceb_rise = 70;
  specparam ceb_fall = 70;

// for timing checking
// write cycle timing
  specparam tRW     = 20;
  specparam tRS     = 20;
  specparam tRH     = 20;
  specparam tAS     = 25;
  specparam tDS     = 20;
  specparam tDLES   = 20;
  specparam tWWL    = 20;
  specparam tWWH    = 50;
  specparam tDLEH   = 20;
  specparam tDH     = 20;
  specparam tPES    = 1000;
  specparam tPW     = 50000;
  specparam tPEH    = 5000;
  specparam tAH     = 25;
  specparam tRPGM   = 1000;

// program cycle timing with internal charge pump
  specparam tCPS    = 1000;
  specparam tCPPW   = 50000;
  specparam tCPH    = 1000;

// read cycle timing
  specparam tRSRD   = 20;
  specparam tCSRST  = 20;
  specparam tCE     = 70;
  specparam tACC    = 70;
  specparam tREADEN = 70;
  specparam tREW    = 20; 
  specparam tRWH    = 70;
  specparam tCEW    = 20; 
  specparam tCWL    = 70;

// testdec timing
  specparam tRSCLE  = 20;
  specparam tTWS    = 25;
  specparam tCLES   = 15;
  specparam tWW     = 20;
  specparam tCLEH   = 15;
  specparam tTWH    = 30;
  specparam tRDES   = 100;
  specparam tREADENT= 70;
  specparam tACCT   = 70;

// wrtest timing
  specparam tRDEP   = 100;
  specparam tWS     = 1000;
  specparam tWH     = 5000;

/*
// for functional checking
// write cycle timing
  specparam tRW     = 1;
  specparam tRS     = 1;
  specparam tRH     = 1;
  specparam tAS     = 1;
  specparam tDS     = 1;
  specparam tDLES   = 1;
  specparam tWWL    = 1;
  specparam tWWH    = 1;
  specparam tDLEH   = 1;
  specparam tDH     = 1;
  specparam tPES    = 1;
  specparam tPW     = 1;
  specparam tPEW    = 1;
  specparam tPEH    = 1;
  specparam tAH     = 1;
  specparam tRPGM   = 1;
  specparam tPGM    = 1;

// program cycle timing with internal charge pump
  specparam tCPS    = 1;
  specparam tCPPW   = 1;
  specparam tCPH    = 1;

// read cycle timing
  specparam tRSRD   = 1;
  specparam tCSRST  = 1;
  specparam tCE     = 1;
  specparam tACC    = 1;
  specparam tREADEN = 1;
  specparam tOHA    = 1;
  specparam tREW    = 1;
  specparam tRWH    = 1;
  specparam tOHRE   = 1;
  specparam tCEW    = 1;
  specparam tCWL    = 1;
  specparam tOHCEB  = 1;

// testdec timing
  specparam tRSCLE  = 1;
  specparam tTWS    = 1;
  specparam tCLES   = 1;
  specparam tCLEH   = 1;
  specparam tTWH    = 1;
  specparam tRDES   = 1;
  specparam tREADENT= 1;
  specparam tACCT   = 1;

// wrtest timing
  specparam tRDEP   = 1;
  specparam tWS     = 1;
  specparam tWH     = 1;
*/

  (A *> D)      = (rd_rise, rd_fall, 0,0,0,0);  
  (READEN *> D) = (rd_en_rise, rd_en_fall, 0,0,0,0);
  (CEB *> D)    = (ceb_rise, ceb_fall, 0,0,0,0);

  $width (negedge RSTB, tRW,  0, tprob);
  $width (negedge WEB &&& DLE==1'b1, tWWL, 0, tprob);
  $width (posedge WEB, tWWH, 0, tprob);
//  $width (negedge WEB &&& PGMEN==1'b1, tPW,  0, tprob);
  $width (posedge WEB &&& PGMEN==1'b1, tRPGM, 0, tprob);
  $width (negedge WEB &&& PGMEN==1'b1, tCPPW, 0, tprob);
  $width (posedge CEB, tCEW, 0, tprob);
  $width (negedge CEB, tCWL, 0, tprob);
  $width (negedge READEN, tREW, 0, tprob);
  $width (posedge READEN, tRWH, 0, tprob);

  $setup (posedge RSTB, posedge READEN, tRSRD, tprob); //
  $setup (negedge RSTB, posedge READEN, tRSRD, tprob); //

  $setup (posedge DIN, negedge WEB, tDS, tprob);
  $setup (negedge DIN, negedge WEB, tDS, tprob);

  $hold  (posedge WEB, posedge DIN, tDH, tprob);
  $hold  (posedge WEB, negedge DIN, tDH, tprob);

  $setup (posedge DLE, negedge WEB, tDLES, tprob);
  $setup (negedge DLE, negedge WEB, tDLES, tprob);

  $hold  (posedge WEB, posedge DLE, tDLEH, tprob);
  $hold  (posedge WEB, negedge DLE, tDLEH, tprob);

  $setup (posedge A, negedge WEB &&& CLE==1'b0, tAS, tprob);
  $setup (negedge A, negedge WEB &&& CLE==1'b0, tAS, tprob);

  $hold  (posedge WEB &&& PGMEN==1'b1, posedge A, tAH, tprob);
  $hold  (posedge WEB &&& PGMEN==1'b1, negedge A, tAH, tprob);

  $hold  (posedge RSTB, posedge A, tRS, tprob);
  $hold  (posedge RSTB, negedge A, tRS, tprob);

  $hold  (negedge PGMEN, posedge RSTB, tRH, tprob); //
  $hold  (negedge PGMEN, negedge RSTB, tRH, tprob); //

  $setup (posedge CEB, negedge RSTB, tCSRST, tprob); //
  $setup (negedge CEB, negedge RSTB, tCSRST, tprob); //

  $setup (posedge PGMEN, negedge WEB, tPES, tprob);
  $setup (negedge PGMEN, negedge WEB, tPES, tprob);

  $hold  (posedge WEB &&& PGMEN==1'b1, posedge PGMEN, tPEH, tprob);
  $hold  (posedge WEB &&& PGMEN==1'b1, negedge PGMEN, tPEH, tprob);

  $setup (posedge CPUMPEN, negedge WEB, tCPS, tprob);
  $setup (negedge CPUMPEN, negedge WEB, tCPS, tprob);

  $hold  (posedge WEB &&& PGMEN==1'b1, posedge CPUMPEN, tCPH, tprob);
  $hold  (posedge WEB &&& PGMEN==1'b1, negedge CPUMPEN, tCPH, tprob);

// testdec
  $hold  (posedge RSTB, posedge CLE, tRSCLE, tprob);
  $hold  (posedge RSTB, negedge CLE, tRSCLE, tprob);

  $setup (posedge A, negedge WEB &&& CLE==1'b1, tTWS, tprob);
  $setup (negedge A, negedge WEB &&& CLE==1'b1, tTWS, tprob);

  $hold  (posedge WEB &&& PGMEN==1'b0, posedge A, tTWH, tprob);
  $hold  (posedge WEB &&& PGMEN==1'b0, negedge A, tTWH, tprob);

  $setup (posedge CLE, negedge WEB, tCLES, tprob);
  $setup (negedge CLE, negedge WEB, tCLES, tprob);
  $hold  (posedge WEB, posedge CLE, tCLEH, tprob);
  $hold  (posedge WEB, negedge CLE, tCLEH, tprob);

  $setup (posedge WEB, posedge READEN, tRDES, tprob);
  $setup (negedge WEB, posedge READEN, tRDES, tprob);

// write test
  $setup (posedge PGMEN, posedge READEN, tRDEP, tprob);
  $setup (negedge PGMEN, posedge READEN, tRDEP, tprob);

endspecify

//------------------------------
//
//  report the time of every timing violation
//
//------------------------------
always @ (tprob) begin : REPORT_VIOLATION
   $display ("\n Timing violation found %0t:", $time);
   end

warning_msg wmsg (addr, rd_en, pg_en, ceb, cle, dle, web, rstb, latch_cmd, tm_twr, d_latch, prog_data, din, fuse, cpumpen);

endmodule

//---------------------------
//
// warning messages.
//
//---------------------------

module warning_msg (addr, rd_en, pg_en, ceb, cle, dle, web, rstb, latch_cmd, tm_twr, d_latch, prog_data, din, fuse, cpumpen);

parameter DIN_WIDTH   = 1;
parameter DATA_WIDTH  = 1;
parameter ADDR_WIDTH  = 16;
parameter TADDR_WIDTH = 9;

input  [ADDR_WIDTH-1:0] addr;
input         rd_en;
input         pg_en;
input         ceb;
input         cle;
input         dle;
input         web;
input         rstb;
input         latch_cmd;
input         tm_twr;
input         d_latch;
input         prog_data;
input         din;
input         fuse;
input         cpumpen;

always @ (ceb or rd_en or pg_en or cle or dle ) begin : WARNING_MESSAGE
  if (rd_en & pg_en & ~ceb) begin
    $display ("Invalid operations. Cannot program and read in the same time.");
  end
  if (cle & dle & ~ceb) begin
    $display ("Invalid commands. Cannot be latch data and test command in the same time.");
 end
  if (dle & pg_en & ~ceb) begin
    $display ("Invalid operation. Cannot latch data and program enable in the same time.");
  end
end

always @ (latch_cmd or addr) begin : INVALID_TEST_MODES
  if (latch_cmd & |addr[TADDR_WIDTH-1:0]) begin
    if (|{addr[TADDR_WIDTH-1:6],~addr[5],addr[4:0]}) begin
      if (|{addr[TADDR_WIDTH-1:3],~addr[2],addr[1:0]}) begin
        $display ("Invald test mode, address = %h.", addr);
      end
    end
  end
end

reg  [ADDR_WIDTH-1:0] addr_latch;
reg  hold_addr;
reg  local_rst;   // for address warning
wire toggle_addr;
wire xor0;
wire xor1;
wire xor2;
wire xor3;
wire xor4;
wire xor5;
wire xor6;
wire xor7;
wire xor8;
wire xor9;
wire xor10;
wire xor11;
wire xor12;
wire xor13;
wire xor14;

wire clk = web;
reg  [1:0] currentstate, nextstate;

initial
  begin
  #0
  addr_latch = 0;
  hold_addr = 0;
  local_rst = 0;
end

// State machine for address warning

parameter ST0 = 2'b00,
          ST1 = 2'b01,
          ST2 = 2'b10,
          ST3 = 2'b11;

always @ (posedge dle or tm_twr) begin:TM_RESET_SM
  if (tm_twr) begin
    currentstate <= ST0;
  end
end

always @ (posedge clk or currentstate) begin:ADDR_LATCH
  if (currentstate == 2'b01) begin
    addr_latch <= addr;
  end
end

always @ (posedge clk or negedge rstb or posedge local_rst) begin:SEQ
    if (~rstb | local_rst) begin
      currentstate <= ST0;
    end
    else begin
      currentstate <= nextstate; 
    end
  end

always @ (dle or cle or pg_en or ceb or currentstate) begin:COMB
  if (~ceb) begin
  case (currentstate)
    ST0: begin
         if (dle) begin
           nextstate <= ST1;
           hold_addr <= 0;
           addr_latch <= 0;
           local_rst <= 0;
         end
         end
    ST1: begin
         if (~cle) begin
           nextstate <= ST2;
           hold_addr <= 1;
         end
         else begin
           nextstate <= ST0;
         end
         end
    ST2: begin
         if (pg_en) begin
           nextstate <= ST0;
           hold_addr <= 0;
           addr_latch <= 0;
           local_rst <= 1;
         end
         else if (~pg_en | cle) begin
                nextstate <= ST0;
              end
         end
    default: begin
               nextstate <= ST0;
             end
  endcase
  end
end

//XOR BITS
  assign xor14 = {addr[14]^addr_latch[14]} & hold_addr;
  assign xor13 = {addr[13]^addr_latch[13]} & hold_addr;
  assign xor12 = {addr[12]^addr_latch[12]} & hold_addr;
  assign xor11 = {addr[11]^addr_latch[11]} & hold_addr;
  assign xor10 = {addr[10]^addr_latch[10]} & hold_addr;
  assign xor9 = {addr[9]^addr_latch[9]} & hold_addr;
  assign xor8 = {addr[8]^addr_latch[8]} & hold_addr;
  assign xor7 = {addr[7]^addr_latch[7]} & hold_addr;
  assign xor6 = {addr[6]^addr_latch[6]} & hold_addr;
  assign xor5 = {addr[5]^addr_latch[5]} & hold_addr;
  assign xor4 = {addr[4]^addr_latch[4]} & hold_addr;
  assign xor3 = {addr[3]^addr_latch[3]} & hold_addr;
  assign xor2 = {addr[2]^addr_latch[2]} & hold_addr;
  assign xor1 = {addr[1]^addr_latch[1]} & hold_addr;
  assign xor0 = {addr[0]^addr_latch[0]} & hold_addr;

  assign toggle_addr = |{   
                            xor14, xor13, xor12, 
                     xor11, xor10, xor9, xor8, 
                     xor7,  xor6,  xor5, xor4, 
                     xor3,  xor2,  xor1, xor0
                           };

always @ (toggle_addr) begin  
  if (toggle_addr) begin
    $display (" \n Address changed during promgram before time %0t:", $time);
    $display (" address = %h.", addr);
  end
end

// Warning for missing reset, caused accumulating 1's 
// in data latch, prior new program cycle.

wire [DIN_WIDTH-1:0] data_width;

reg         data_width_larger_than_one;
reg         prog_data_not_zero;
reg         compare_data;
reg         prog_data_chk0;

wire        data_mismatch;
wire        display_msg;

reg [1:0]   cst, nst;

wire  dxor;

initial
  begin
    data_width_larger_than_one = 0;
    prog_data_not_zero = 0;
    compare_data = 0;
    prog_data_chk0 = 0;
    cst = 0; 
    nst = 0;
  end

parameter state0 = 2'b00,
          state1 = 2'b01,
          state2 = 2'b10,
          state3 = 2'b11; 

assign data_width = DIN_WIDTH;

always @ (ceb or data_width) begin
  if (~ceb && data_width >= 2 ) begin
    data_width_larger_than_one = 1;
  end
  else begin
    data_width_larger_than_one = 0;
  end
end

always @ (posedge dle or tm_twr) begin:TM_RESET_STM
  if (tm_twr) begin
    cst <= state0;
  end
end

// use 3 clock cycle when missing rstb insertion.

always @ (posedge clk or negedge rstb) begin:SEQ_DATA
  if (~rstb) begin 
    cst <= state0;
  end
  else begin
    cst <= nst;
  end
end

always @ (dle or cle or ceb or rstb or pg_en or web or cst or
          data_width_larger_than_one) begin:COMB_DATA
  if (~ceb & data_width_larger_than_one) begin
    case (cst)
      state0: begin
                if (pg_en & ~web) begin
                  nst <= state1;
                  compare_data <= 0;
                  prog_data_chk0 <= 1;
                end
              end
      state1: begin
                if (cle | ~rstb) begin
                  nst <= state0;
                  prog_data_chk0 <= 0;
                end
                else if (dle & ~web ) begin
                       nst <= state2;
                       compare_data <= 1;
                     end
              end
      state2: begin 
                if (~rstb) begin
                   nst <= state0;
                   prog_data_chk0 <= 0;
                end
                else if (pg_en & ~web) begin
                       nst <= state1;
                       compare_data <= 0;
                     end
              end
      default: begin
                 nst <= state0;
               end
    endcase
  end
end 
              
always @ (compare_data or prog_data or d_latch or 
          prog_data_chk0) begin 
  if (prog_data_chk0) begin
    prog_data_not_zero = | prog_data;
  end
end

 assign dxor = {prog_data^d_latch} & compare_data;

 assign data_mismatch = |dxor;

 assign display_msg = cst == 2'b10 & dle;

always @ (compare_data or data_mismatch or display_msg) begin
  if (compare_data) begin
    if (data_mismatch & display_msg) begin
      $display (" \n Wrong program data at time. %0t:", $time);
      $display (" program data = %h.", d_latch);
      $display (" Missing reset in program cycle.");
    end
    else if (~data_mismatch & display_msg) begin
           $display (" \n The same program data at time. %0t:", $time);
           $display (" program data = %h.", prog_data);
         end
  end
end

// attempt write 0 over 1 warning

reg comparebit;
integer i;
always @ (ceb or dle or web or rstb or fuse or tm_twr or addr) begin
  comparebit = ~ceb & dle & ~web & rstb;
  if (comparebit) begin
    for (i=0; i<DATA_WIDTH; i=i+1) begin
      if (fuse > din) begin
        if (tm_twr & (|addr[ADDR_WIDTH-1:TADDR_WIDTH] === 1'b0)) begin
           $display ("\n    bit%d cannot be overwritten by 0 at address %h,",i,addr);
        end
        else 
        if (~tm_twr) begin
          $display ("\n    bit%d cannot be overwritten by 0 at address %h,",i,addr);
        end 
      end
    end
  end
end

// maximum charge pump assertion 100us warning

reg cpclk;
reg [12:0] counter;
reg cpump_msg;

parameter CLOCK_CYC = 20;
always @ (ceb) begin : CP_CLOCK
  cpclk = 0;
  if (~ceb) begin
    forever begin
      # (CLOCK_CYC/2)
      cpclk = ~cpclk;
    end
  end
end

always @ (posedge cpclk or negedge cpumpen or rstb or ceb) begin: CPUMP_COUNTER
  if (~ceb) begin
    if (~cpumpen | ~rstb) begin
      counter <= 0;
      cpump_msg <= 0;
    end
    else if (counter == 13'h138A) begin: CAP_CYC_5002
      counter <= counter;
    end
    else begin
      counter <= counter + 1;
    end
    if (counter == 13'h1387) begin: CYC_5000
      cpump_msg <= 1;
    end
    if (cpump_msg) begin
      $display ("\n CPUMPEN assertion > 100 microseconds. %0t:", $time);
    end
    if (counter == 13'h1388) begin
      cpump_msg <= 0;
    end
  end
end

endmodule

`endcelldefine