arc_usb1.html
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<TITLE></TITLE>
<META NAME="GENERATOR" CONTENT="StarOffice/5.1 (Linux)">
<META NAME="AUTHOR" CONTENT="bill saperstein">
<META NAME="CREATED" CONTENT="20020731;14470600">
<META NAME="CHANGEDBY" CONTENT="bill saperstein">
<META NAME="CHANGED" CONTENT="20020731;15213000">
<STYLE>
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@page { size: 8.5in 10.96in; margin-left: 1.25in; margin-right: 1.25in; margin-top: 1in; margin-bottom: 1in }
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<BODY>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><FONT FACE="courier, monospace">This
document attempts to describe the protocol flow for the ARC USB 1.1
core. Included in the document are the flow diagrams for each of the
usb transactions, control, bulk data_in, bulk data_out, iso data_in
and iso data_out. The interrupt transaction looks like the bulk
transaction except for the different PID.</FONT></P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><FONT FACE="courier, monospace">There
are several constraints on latency required by the ARC design. They
are listed below:</FONT></P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><FONT FACE="courier, monospace">1)The
most critical latency requirement for the core is the receipt of the
BDT descriptor (via a DMA read access from memory) in NO MORE than
580ns. If the core does not receive the BDT in this time frame, it
NAK's the bulk or control transaction or bit stuffs the iso
transaction. It then awaits for the next token and gets in an
infinite loop with the host. Without control of the BDT, the core is
unable to communicate with the software regarding the type/endpoint
of the transaction requested.</FONT></P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-left: 0.5in; margin-bottom: 0in"><FONT FACE="courier, monospace">The
current bb_chip does not guarantee the 580ns latency for retrieval of
the BDT by the core. In order to solve this problem, it is proposed
that a copy of the BDT's be placed close to the ARC core so that a
memory access will not be necessary. We are only expecting to support
four(4) endpoints in the bb_chip. This requires 64 bytes of storage
for the local BDT's.</FONT></P>
<P ALIGN=JUSTIFY STYLE="margin-left: 0.5in; margin-bottom: 0in"><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-left: 0.5in; margin-bottom: 0in"><FONT FACE="courier, monospace">The
local BDT's will be placed outside of the BVCI interface of the core,
between the BIU and the C/D bus.</FONT></P>
<P ALIGN=JUSTIFY STYLE="margin-left: 0.5in; margin-bottom: 0in"><FONT FACE="courier, monospace">When
the core accesses the BDT memory address, it will access this local
register file instead of starting a C/D DMA access. Similarly, from
the processor side, these registers will be memory mapped to the USB
region on the C/D bus.</FONT></P>
<P ALIGN=JUSTIFY STYLE="margin-left: 0.5in; margin-bottom: 0in"><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-left: 0.5in; margin-bottom: 0in"><FONT FACE="courier, monospace">The
use of local BDT's will eliminate the latency issue encountered when
the core tries to retrieve the descriptors from memory.</FONT></P>
<P ALIGN=JUSTIFY STYLE="margin-left: 0.5in; margin-bottom: 0in"><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><FONT FACE="courier, monospace">2)Another
latency requirement is for DMA writes. The core uses a 16 byte fifo
divided into two 8 byte ping-pong fifos. All DMA writes from the core
are performed as 4 byte writes to memory. Thus, while one fifo is
being filled, the other must be able to be emptied. To fill the 8
byte fifo from usb requires 64bits X 80ns = 5usec. The current
latency of getting onto the C/D bus is 1 usec; so this constraint
should NOT be a problem for the bb_chip design.</FONT></P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><FONT FACE="courier, monospace">3)For
DMA reads from memory, the core needs to return data to the USB bus
within 580ns + 740ns = 1.3usec. Using the local BDT's to retrieve the
descriptor, the entire 1.3usec is the latency required to get the
data from memory. Again, since the latency of the C/D bus is (worst
case 1 usec.), this constraint should NOT be a problem for the
bb_chip design.</FONT></P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><FONT FACE="courier, monospace">The
following diagrams show the protocol flow for the different
transactions using the ARC core.</FONT></P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><IMG SRC="sv6106101.gif" NAME="Object1" ALIGN=LEFT WIDTH=831 HEIGHT=609 BORDER=0><BR CLEAR=LEFT><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><FONT FACE="arial, sans-serif">Control
Transfer</FONT></P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><IMG SRC="sv6106102.gif" NAME="Object2" ALIGN=LEFT WIDTH=847 HEIGHT=621 BORDER=0><BR CLEAR=LEFT><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><FONT FACE="arial, sans-serif">Bulk
Data_IN</FONT></P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><IMG SRC="sv6106103.gif" NAME="Object3" ALIGN=LEFT WIDTH=863 HEIGHT=632 BORDER=0><BR CLEAR=LEFT><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><FONT FACE="arial, sans-serif">Bulk
Data_Out</FONT></P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><IMG SRC="sv6106104.gif" NAME="Object4" ALIGN=LEFT WIDTH=879 HEIGHT=644 BORDER=0><BR CLEAR=LEFT><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><FONT FACE="arial, sans-serif">ISO
Data_IN</FONT></P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><IMG SRC="sv6106105.gif" NAME="Object5" ALIGN=LEFT WIDTH=895 HEIGHT=656 BORDER=0><BR CLEAR=LEFT><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><BR>
</P>
<P ALIGN=JUSTIFY STYLE="margin-bottom: 0in"><FONT FACE="arial, sans-serif">ISO
Data_Out</FONT></P>
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</P>
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</P>
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