BB_SoC_Performance_Validation.html
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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<title>BB SoC Performance Validation</title>
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<h1>BB SoC Performance Validation</h1>
<h2>Goals<br>
</h2>
<br>
The goal of the following test plan is to validate the performance of the
BB SoC with respect to the RCP/4300. BB SoC must have a performance at least
equal to RCP/4300 in all key areas so that we can ensure games that ran on
N64 will run with no problems on the BB Player. These tests target the memory
system, since that is the main change that impacts performance.<br>
<h2>Assumptions</h2>
Chip runs at 62.5 MHz.<br>
<br>
In addition tests will be run (?) at 93.75 MHz.<br>
<h2>Performance Metrics</h2>
The following sections identify the key metrics which should be measured
for RCP/4300 and BB SoC and compared.<br>
<h3>CPU</h3>
Instruction cache fill rate, eg single instruction stream with no loops.<br>
Data cache fill/write-back rates<br>
bcopy bandwidth through DRAM in cached memory space.<br>
bcopy bandwidth through DRAM uncached memory space.<br>
<h3>RSP</h3>
DMEM DMA to/from DRAM<br>
IMEM DMA to/from DRAM<br>
<h3>RDP/VI</h3>
Run all tests below with different size rectangles on different memory page
boundaries. DDR performance should be better than RDRAM for small primitives
and for primitives which are tall and thin. <br>
<br>
fill<br>
copy<br>
texture block load<br>
1 cycle, color write only<br>
1 cycle, color read modify write<br>
1 cycle, color and z read modify write (put color and z in different locations
and check for performance changes)<br>
2 cycle, color write only<br>
2 cycle, color read modify write<br>
2 cycle, color and z read modify write (put color and z in different locations
and check for performance changes)<br>
<br>
<h3>Simultaneous</h3>
Tests targeting the above should be structured so they can be combined easily.
Examples of interesting combined cases:<br>
<br>
Insert VI traffic roughly equivalent to NTSC (if possible).<br>
Insert CPU bcopy through cache.<br>
<h2>Test List<br>
</h2>
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