* * * * * * * * * * * * * *	* * * * * * * * * * * * * * 
				USB Test From ARC

Please set tabstop = 4
* * * * * * * * * * * * * *	* * * * * * * * * * * * * * 

(1) System stall 50 cycles(USB clocks)  

(2) Register Test in DevUsbInit()
	* reset test
	  After system reset, test if the following register have following values(total 31)  

	  Register      Address   Expect value 
					offset
	  "ID_FIELD"    0x00      0x04
      "ID_COMP"     0x04      0xFB
      "OTG_ICTRL"   0x14      0x00
      "OTG_CTRL"    0x1C      0x00
      "INT_ENABLE"  0x84      0x00
      "ERR_STATUS"  0x88      0x00
      "ERR_ENABLE"  0x8C      0x00
      "ADDRESSREG"  0x98      0x00
      "BDT_PAGE1"   0x9C      0x00
      "FRAMENUMLOW" 0xA0  	  0x00 
      "FRAMENUMHI"  0xA4  	  0x00 
      "TOKEN"       0xA8  	  0x00 
      "SOF_THDL"    0xAC  	  0x00 
      "BDT_PAGE2"   0xB0  	  0x00 
      "BDT_PAGE3"   0xB4  	  0x00 
      "ENDPCTL0"    0xC0  	  0x00 
      "ENDPCTL1"    0xC4      0x00 
      "ENDPCTL2"    0xC8  	  0x00 
      "ENDPCTL3"    0xCC  	  0x00 
      "ENDPCTL4"    0xD0  	  0x00 
      "ENDPCTL5"    0xD4  	  0x00 
      "ENDPCTL6"    0xD8  	  0x00 
      "ENDPCTL7"    0xDC  	  0x00 
      "ENDPCTL8"    0xE0  	  0x00 
      "ENDPCTL9"    0xE4  	  0x00 
      "ENDPCTL10"   0xE8  	  0x00 
      "ENDPCTL11"   0xEC  	  0x00 
      "ENDPCTL12"   0xF0  	  0x00 
      "ENDPCTL13"   0xF4  	  0x00 
      "ENDPCTL14"   0xF8  	  0x00 
      "ENDPCTL15"   0xFC  	  0x00

	* Register Read & Write Test
	  Write data 0xff, 0xaa, 0x55, 0x00 with certain mask into the following 9 register, then read back and check the result.
	  Register     Addr Mask
				   offs
	  "ERR_ENABLE" 0x8C 0xff
  	  "ADDRESSREG" 0x98 0xef
      "BDT_PAGE1"  0x9C 0xff
      "BDT_PAGE2"  0xB0 0xff
      "BDT_PAGE3"  0xB4 0xff
      "ENDPCTL0"   0xC0 0x1f
      "ENDPCTL1"   0xC4 0x1f
      "ENDPCTL2"   0xC8 0x1f
      "ENDPCTL3"   0xCC 0x1f

(3) BDT(Buffer Descriptor Table) setup in DevUsbInit()
	Write BDT Address 
	MSByte		 into register BDT_PAGE_01(0x9C) 
	2nd MSBytes  into register BDT_PAGE_02(0xB0) 
	3rd MSBytes  into register BDT_PAGE_03(0xB4)

(4) init setup 
    * Write the following value into the following 8 registers.

	Register	    Addr  Value 
					offset
	"OTG_ICTRL"  	0x14  0x00   
    "OTG_CTRL"   	0x1c  0x00   
    "CONTROL"    	0x94  0x00   
    "INT_ENABLE" 	0x84  0x00   
    "ERR_ENABLE" 	0x8C  0x00   
    "ADDRESSREG" 	0x98  0x00   
    "FRAMENUMLOW"	0xA0  0x00   
    "FRAMENUMHI" 	0xA4  0x00  

    * Write 0 to ENDPCTRL* to disable all endpoints
    * Write 0x0D to ENDPCTRL*(0-3, max 4) to enable endpoints
	* Clear int, enable interface , etc
	  write data into the following reg
	  Register     Addr  Value  comments
				   Offs   
	  "INT_STATUS" 0x80  0xFF   clear all irq
      "INT_ENABLE" 0x84  0x01   enable USB rst interrupt
      "CONTROL"    0x94  0x02   Reset all BDT ODD ping/pong bits
      "CONTROL"    0x94  0x01   VUSB enable
      "OTG_CTRL"   0x1c  0x80   Enable a pull up resistor on D- Data line

(5) Device test
    Once VUSB is enabled, it will start to run the main_proc in vusb_host_ctl.v:9723 
	
	* In main_proc
	    call task usb_reset to reset usb (reset plus is 2.5us)
	    Note: it will cause a reset interrupt
	  In MainEntry.cpp : 142 (in interrupt handler) (progress=1)
        Write 0x0D (Tx enable, Rx enable and perform handshaking) 
		to "ENDPCTL0 (0xC0)" 		 
      	Write 0xB9 to INT_ENABLE(0x84) 
        Write 0x01 to INT_STATUS(0x80) to clear reset int.

    * In verilog side call task simple_device_test(0x8000) in vusb_host_ctl.c:9257  
	    (A) :9290 called tocken_packet task to send out SETUP token at endpoint 0
		(B) :9317 send 1 bytes data packet with DATA0_PID
		(C) :9326 called handshake_in_packet task to wait for USB ACK
		(D) repeat (A)--(C) till handshake is done.

        Trigger interrupt handler to be called (progress=2)
		:205 set 0x01 to "CONTROL"(0x94)
		clear the interrupt bits 
		
		(E) :9372 send out IN_PID tocken
		(F) :9374 called data_in_packet Wait for device to respond data  
			(only data type get checked)
	    (G) :9425 send USB handshake packet

	    Trigger interrupt handler (progress 3)
        Token done interrupt cause by respond data going out
        clear the interrupt bits

        DO (A)--(D) excpet different data in data packet and packet size=2
		The same as the above, interrupt will trigger(progress=4)
		DO (E) (F)
		:9393 send out imcomplete ACK  
		DO (E) (F)
        DO G 

		Trigger interrupt (progress 5), do the same thing as above

		DO (A) --(D) excpet different data in data packet and packet size=3
        The same as the above, interrupt will trigger(progress=6)
        DO (E) (F)
        :9393 send out BAD ACK
        DO (E) (F) 
        DO G 

        Trigger interrupt (progress 7), do the same thing as above

        DO (A) --(D) excpet different data in data packet and packet size=8
        The same as the above, interrupt will trigger(progress=8)
        DO (E) (F)
        DO (G)

        Trigger interrupt (progress 9), do the same thing as above 
		:9442 send out OUT_PID token
		:9449 send out zero length packets
        :9456 wait for USB ACK

        Trigger interrupt (Progress 10), 
		MainEntry.cpp:266 write 0x00 to "INT_ENABLE"(0x84) to disable interrupt 
	    clear interrupt bit
		set g_DoneWithDeviceTest to let MainTestThread run the next test.

Before(linetest has enough delay) run the test, MainEntry.cpp 1031-1065 will turn on the host mode.
   * Read usb_info(0x0c) to see if USB_HOST is there
   * write 0x08 to CONTROL reg(0x94) to enable host mode
   * write 0x20 to OTG_INT_EN(0x14) to enable the interrupt on line changed

(6) linestate_test :9489

	Reset(:9507) usb with k_state(:9505), then changed to J state(:9508) 	
    Trigger interrupt (line state changing <progress 11>) 	
    READ OTAG_ISTAT(0x10), check if it caused by line state changed(mask 0x20)
	READ CONTROL reg(0x94) 
    check if the second MSB(&0x40 is in SE0 state ) is set.
    READ OTG_STAT reg(0x18) and check "line state stable bit"(mask 0x20)
    clear int bits
    
    Reset usb(:9516) then set to jstate
	Trigger interrupt(progress 12)
	READ OTAG_ISTAT(0x10), check if it caused by line state changed(mask 0x20)
    READ CONTROL reg(0x94)
    check if the 1st MSB(&0x80 is in J state ) is set.
    READ OTG_STAT reg(0x18) and check "line state stable bit"(mask 0x20)
	Write 0x20 to INT_ENB(0x84) reg, to enable resume interrupts
    clear int bits

    Change to k_state(:9531)
    Trigger interrrupt(progress 13) 
	Read INT_STATUS to check if it is resume interrupt(mask 0x20)
	READ CONTROL reg(0x94) 
	check J/SE0(0x80 0x40) state is not set
	READ OTG_STAT reg(0x18) and check  "line state stable bit" not set
	write 0x00 to INT_ENB(0x84) reg, to turn off resume interrupt
	write 0x00 to OTG_CTRL(0x1C)
    clear intrrupt bits
	set g_DoneWithLineStateTests to 1

Before otg_test is running, write 0x80 to otg_ICTRL (0x14) to turn on ID interrupts
write 0x08 to OTG_CTRL(0x1c) to turn on vbus power signal(vusb_up_int_bvci.v:1765)
see MainEntry.cpp 1082-1099

(7) otg_test :9558

	Set otg_test timeout 20,000,000ns
	In vusb_otg_lpbck.v, 
	:156 usb_id(id pin from mini connect) will be asserted,       
	:otg_stable_id_r will be set to 1 after 1st 1ms (vusb_up_int_bvci.v:3833)
	:hc_otg_stable_id will be set to 1 
    interrupt is asserted at vusb_up_int_bvci.v:1861
	Condition: more than 1ms, host controller enable and id pin stabled

    Interrrupt handler :425 (progress=14)
	Check if it trigger by id pin
    write 0 to OTG_CTRL (0x1c) to turn off VBUS and data line termintation resistors.	
	READ OTG_STAT(0x18) check if ID(mask 0x80) is turned off 
	clear interrupt bit

	After another 1ms, Interrupt(disconnect) should be trigger again. (progress=15)
    Interrupt : 457 (progress 15)
	check if it trigger by id pin
	write 0x02 to OTG_CTRL(0x1c) to charge vbus signal through a resistor
	write 0x08 to OTG_ICTRL(0x14) to enable session enable interrupt
		alsoturned off id pin interrupt.
	Read OTG_STAT(0x18) check if ID(mask 0x80) is turn off.
	clear interrupt bit

    In vusb_otg_lpbck.v:158 usb_session_vld get turn on.
	After 2ms, vusb_up_int_bvci.v:1899, usb_sess_vld_int_r get asserted.
	
	Interrupt(progress 16):500 otg session valid interrupt
	check if trigger by otg session valid interrupt
	write 0 to OTG_CTRL(0x1c) 
	Read from OTG_STAT(0x18) check if sess_valid get cleared(mask 0x08)
	clear interrupt bit.

	After another 2ms, interrupt again
	Interrupt : 532 (progress 17)
	check if trigger by otg session valid interrupt
	write 0x01 to OTG_CTRL(0x1c) to discharge vbus via resistor
	write 0x01 to OTG_ICTRL(0x14) to turn on A_VBUS_VLD_EN interrupt
	Read from OTG_STAT(0x18) check if sess_valid get cleared(mask 0x08)
    clear interrupt bit.
 
    In vusb_otg_lpbck.v:160 usb_a_vbus_vld will be asserted
	After 2ms, otg_a_vbus_vld should get be triggered
	Interrupt : 574 (progress 18)
	check if trigger by usb_a_bus_vld interrupt
	write 0 to OTG_CTRL(0x1c) 
	READ OTG_STAT(0x18) check if usb_a_bus_vld get clear(mask 0x01)
	clear interrupt bit

	After another 2ms, interrupt again
	Interrupt : 607 (progress 19)
	check if trigger by usb_a_bus_vld interrupt
	write 0x04 to OTG_ICTRL(0x14) to turn on B_Session_end_en interrupt
	READ OTG_STAT(0x18) check if usb_a_bus_vld get clear(mask 0x01)
	clear interrupt bit

    After 2ms (vusb_up_int_bvci.v :1809), usb_b_sess_end_int should be triggered
	Interrupt :649 (progress 20)
	check if it triggered by usb_b_sess_end_int(mask 0x04)
	write 0 to OTG_CTRL(0x1c) 
	READ OTG_STAT(0x18) check if usb_b_sess_end_int  get clear(mask 0x04)	
	clear interrupt bit
	
	After another 2ms, interrupt again
    Interrupt : 682 (Progress 21)
    READ OTG_STAT(0x18) check if usb_b_sess_end_int  get clear(mask 0x04)
	write 0x00 to OTG_ICTRL(0x14) to turn off all interrupt
	clear interrupt bit
	set g_DoneWithOTGTest=1
		
Before simple host echo test, In MainEntry.cpp (1112-1132)	
    write 0x00 to CONTROL(0x94) to disable vusb core.

(8) simple_host_echo_test :9600
    Call HostUsbInit() in usb_init.cpp:199 to set up usb 1.1 Host.
	  * write 0xff to ERR_STAT(0x88) to clear the error reg.
	  * write 0x0E to INT_STAT(0x80) to clear TOK_DNE, SOF_TOK error int
	  * write 0x0E to INT_ENB(0x84)  to setup TOK_DNE, SOF_TOK error int
	  * write 0x30 to OTG_CTRL(0x1c) to turn off/down resistors
	  * write 0x1b to CONTROL(0x94) to set host mode and reset
	  * wait 100 cycles
	  * write 0x09 to CONTROL(0x94) to enable host mode(turn off reset)

   Verilog side 
      * call wait_for_reset to wait for host to do a reset
	  * Wait for SOF with (SOF_PID, #1, at endpnt 0)
      * When SOF is coming,  interrupt:717 (progress 22 will be triggered)
	    check if caused by SOF
		write 0x10(out token, vusb will tx) to TOKEN(0xA8) to write OUT tocken to endpoint 0
		clear interrupt bit
	  * Then wait for out tocken(OUT_PID, #0, endpnt=0)
	  * Wait for DATA from host (DATA0_PID, 8, 0)
	  * When it done, it will trigger Token done interrupt: 738(prog=23)
		check if caused by Token done and tx packets
		write 0x90(in token, vusb will rx) to TOKEN(0xA8)
		clear interrupt bit
	  * Wait for IN tocken:9675 (IN_PID, 0, 0)
	  * Send out packet with PID=DATA0_PID, endpoint=0
      * When Rx is doen, TOK_DONE interrupt will be trigered at :760(prog 24)
		check if it caused by TOK_DONE and rx packet	
		check data in rcv packet
		write 0x00 to CONTROL(0x94) to disable host mode
		write 0x00 to INT_ENB to disable all interrupts
		clear interrupt bit 
		set g_DoneWithHostTest
		MainEntry: 1125-1152
		Wait one cycle and remove all irqs 
	  * Wait for handshake ack packet.
	  

* * * * * *   USB Chapter 9(USB Device Framework) test * * * * * * * * *
At :9911
Only at verilog side :
(1) :9930 get_device_desc():2769
	* Send out SETUP token 
	* Send out Data packet with
	  DATA0_PID
	  length=8
      data (80 06 00 01 00 00 08 00)
    * wait for handshake
    * send out IN_PID token
	* Rx data with 
	  DATA1_PID	
	  packet length=8
    * The descriptor length will be in data[0]
	* Send out GOOD_ACK packet with ACK_PID.
	* Send out OUT token
	* Send out bogus or zero-length packets 
	  The above two step is used to 
	  turn around bus to termintate the setup transfers.
	* Send out Setup tocken
	* send out Send out data packet with
	  DATA0_PID, length=8
	  data (80, 06 00 01 00 00 actual_length 00)
	* wait for handshake
	* Send out IN TOKEN
	* Rx data with DATAX_PID(<=15)
	* Send out GOOD_ACK packet with ACK_PID.
	* Send out bogus or zero-length packets 
      The above two step is used to 
      turn around bus to termintate the setup transfers.

(2) :9937 set_address() : 3979
	* Send out SETUP token 
	* Send out Data packet with
      DATA0_PID
      length=8
      data (00 05 address 00 00 00 00 00)   
    * wait for handshake
    * Send out IN tocken
	* Rx data 
	  The above two step is used to 
	  turn around bus to termintate the setup transfers.

(3) :9944 get_config_desc() :3138
	* Send out SETUP token 
    * Send out Data packet with
      DATA0_PID
      length=8 
      data (80 06 00 02 00 00 ff 01)
	* wait for handshake
	* send out IN_PID token
	* Rx data with  
      DATAX_PID     
    * Send out GOOD_ACK packet with ACK_PID.
    * Send out bogus or zero-length packets
      The above two step is used to 
      turn around bus to termintate the setup transfers.

   * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
    Procedure: set_value(breq, wval, wind, test_num):4115
  
    Parameters: breq           -- Request type 9-configuration 11-interface
                wval           -- Configuration value to be set
                wind           -- wIndex used in set interface
                test_num       -- Base test number for test progress signal
  
    Globals:    usb_clk        -- USB clock
                device_address -- Current USB target address
                hc_pckt_data   -- Transmit and expected packet data
                test_progress  -- Counts test bench progression
  
    Description: This procedure performs a set configuration or set interface
    control transfer to a USB target. The test_num parameter is assigned to
    the global variable test_progress, and incremented as the test proceeds.
    The global device_address is used to determine the current address of the
    target being addressed. For more information on the Set Configuration
    device request see Section 9.4.7 of the USB Spec Version 1.0. For more
    information on the Set Interface device request see Section 9.4.10 of
    the USB Spec Version 1.0.

    * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
	

	* Send out SETUP token
    * Send out Data packet with
      DATA0_PID
      length=8
      if (breq == 9)  // configuration
		 data (0x00 0x09 wval0_low_byte wval0_high_byte 
			  wIndex_low_byte wIndex_high_byte 0 0)
	  else            // interface
	     data (0x01 11, wval0_low_byte wval0_high_byte 
              wIndex_low_byte wIndex_high_byte 0 0)	     

			 
(4) :9955 call set_value(9 1 0 0x9040) : 4115
(5) :9962 call get_device_status() :3494
    * SETUP token
	* DATA (80 0 0 0 0 0 2 0)    
    * handshake
	* IN Token
	* DATA_PID_1 to rx data
	* send out ACK_GOOD
	* turn the bus around (OUT_PID, DATA1_PID)

(6) :9970 call set_feature(2, 0, 1, 0x9050) to set the endpoint 1 feature.
  	  Parameters: rtype          -- 0-device, 1-interface, 2-endpoint.
                  wval           -- The feature selector to be set.
                  wind           -- The interface or endpoint number
                  test_num       -- Base test number for test progress signal

      Globals:    usb_clk        -- USB clock
                  device_address -- Current USB target address
                  hc_pckt_data   -- Transmit and expected packet data
                  test_progress  -- Counts test bench progression
  
    Description: This procedure performs a set feature control transfer to a
    USB target. The rtype parameter selects the destination of the set feature.
    This can be a device, interface, or endpoint. The wval is the feature
    selector to be set within the recipient device, interface, or endpoint.
    And wind selects the interface or endpoint number. The test_num parameter
    is assigned to the global variable test_progress, and incremented as the
    test proceeds. The global device_address is used to determine the current
    address of the target being addressed. For more information on the Set
    Feature device request see Section 9.4.9 of the USB Spec Version 1.0.
  
    Called at :4267
    * Setup tocken
	* DATA (rtype, 3, wval_l wval_h, wind_l, wind_h, 0 0)
    * Wait for handshake
    * Turn bus around   

(7) :9977 get_endpoint_status(1, 0x9058) :3654
	* SETUP token
	* DATA (0x82, 0 0 0 #ENDPNT, 0 02 0)
    * handshake
    * IN_DATA
    * rx data 
	* ACK_GOOD
	* Turn bus around

(8) :9992 call clear_feature(2, 0, 1, 0x9060) : 4408
    Procedure: clear_feature
  
    Parameters: rtype          -- 0-device, 1-interface, 2-endpoint.
                wval           -- The feature selector to be cleared.
                wind           -- The interface or endpoint number
                test_num       -- Base test number for test progress signal
  
    Globals:    usb_clk        -- USB clock
                device_address -- Current USB target address
                hc_pckt_data   -- Transmit and expected packet data
                test_progress  -- Counts test bench progression
  
    Description: This procedure performs a clear feature control transfer to
    a USB target. The rtype parameter selects the destination of the clear
    feature. This can be a device, interface, or endpoint. The wval is the
    feature selector to be cleared within the recipient device, interface,
    or endpoint. And wind selects the interface or endpoint number. The
    test_num parameter is assigned to the global variable test_progress,
    and incremented as the test proceeds. The global device_address is used
    to determine the current address of the target being addressed. For more
    information on the Clear Feature device request see Section 9.4.1 of the
    USB Spec Version 1.0.

	* SETUP token
	* DATA (rtype, 1, wval_l wval_h wind_l wind_h 0 0)
	* handshake
	* Turn around bus
	
(9) :9999 call get_endpoint_status() 
	see (7)

(10) :10014 call set_value(9 1 0 0x9070)
	see (4)

(11) :10021 call get_value(8 1 0 0x9080):3807
	* Send out SETUP token
    * Send out Data packet with
      DATA0_PID
      length=8
      if (breq == 10)  // configuration
         data (0x80 0x10 wval0_low_byte wval0_high_byte
              wIndex_low_byte wIndex_high_byte 0 0)
      else            // interface
         data (0x81 req, wval0_low_byte wval0_high_byte
              wIndex_low_byte wIndex_high_byte 0 0)
	* handshake
	* DATA_IN packet
	* Read data
	* sendout ACK_GOOD
	* turn bus around
	
(12) :10028 call get_value(a 0 1 0x9090)
	see (11)

(13) :10035 call set_value(b 1 1 0x90a0)
	see (4)

(14) :10042 call get_value(a 1 1 0x90b0)
	see (11)

(15) :10049 call set_value(b 0 1 0x90c0)
	see (4)

(16) :10056 call get_value(a 0 1 0x90d0)
	see (11)

(17) :10114 call get_data() try to rx 
     manufacture id string
	 Product id string
	 Serial number string
	 Configuration string
	 Interface1 string

(18) : Test the endpoint Halt Stall usage and the control endpoint Protocol Stall usage.
	10230: stall_test(:8430)
	Procedure: stall_test
    This procedure tests the two types of stalls implemented in USB.
  
    The USB 1.1 spec defines the use stall in two distinct ways. 
    The first usage of stall defined is clarified in the USB 1.1 spec by 
    referring to it as a functional stall. A functional stall is when the 
    Halt Feature associated with an Endpoint is set. Once a function's 
    endpoint is halted the function must continue returning STALL until 
    the condition causing the halt has been cleared through host intervention.
  
    The second usage of the stall handshake is known as protocol stall. 
    Protocol stall is unique to control pipes.  Protocol stall differs from 
    functional stall in meaning and duration. A protocol STALL is returned 
    during the Data or Status stage of a control transfer, and the STALL 
    condition terminates at the beginning of the next control transfer (Setup).

    This procedure is dependant on a diagnostic hook coded into the usb driver
    software running on the USB SIE Adjunct processor.  This code echo's any 
    OUT  DATA transaction recieved by the VUSB SIE and makes it available for
    subsequent IN data transactions.

    * :8453 called set_diag_desc to clear all the error bits in the 
	  Diagnostic register of the target device. :4562
	  A) SETUP 
	  B) DATA0 (0x40, req&0xfe, wval_l wval_h
				wind_l, wind_h, wlen_l, wlen_h)
      C) OUT 
	  D) DATA with given length
	  E) Turn Bus around
   * call set_diag_desc to configure the endpoint 2 as a bidirectional 
	 Bulk enddpoint 
   * :8488 set the feature stall on endpoint 2
   * send out data packet and expect STALL ACK
   * send out IN tocken and expect STALL ACK
   * Send out SETUP tocken and make sure(do the same as above) Stall not
	 cleared. (IN, get stall ack)
   * Clear stall on endpoint2 : 8560
   * call get_diag_desc to check if any error condition
   * Check register to see if we get any interrupt
   * Run bulk_echo_test(2, 0, data_pattern_INC, 0):5311 to make sure stall 
	 condition is removed.
   * Then testing protocol stall
     Setup the protocol stall by
	 1) Invalid setup request
	 2) Bad data field In
	 3) Data field too long
	 check the protocol stall by sending
	 1) IN token
	 2) Out token with data
     clear protocol stall by sending SETUP token.
	
* * * * * * * Chapter 11(HUB) test * * * * * * * * * * 
:10243 ----- :11836 (DOES NOT SUPPORT ANY MORE)

* * * * * * * Checklist test * * * * * * * * * * 
All these tests need diagnostic driver to support. 

(1) :11882 call reset_test: 4910
    :4931 clear all the bits in the diag reg of the target device
    :4947 reset USB
    :4952 get_diag_desc
     then check if target device get reset int or not.
    send out sync, pid, addr, then reset usb
	:5020 called get_diag_desc to check if get some error(token not done)
    :5029 clear all bits in the diag reg
    :5045 send out SETUP token
	:5058 send out sync
    :5056 tx 6 bytes
	:5067 tx pid
    :5082 tx data
    :5103 before token packet done, reset,
	:5108 called get_diag_desc to check if it get error
    :5116 clear all the bits in diag reg 

(2) :11911 resume_test : 5132
	:5150 clear all the bits in the diag reg
	:5162 set to j state
	:5163 stop SOF packets
	:5165 start SOF 
	:5174 detect if device saw the resume
	:5179 clear all the bits in the diag reg
	:5190 set to j state
	:5191 stop SOF packets
	:5196 call usb_resume
    :5197 start SOF
    :5201 call get_diag_desc to check if target device has gone into suspend
	 state.

(3) :12015 crc_bitstuff_test
    :5240 clear all bits in the diag bits
	:5254 configure endpoint 2 as bidirection bulk transfer 
     and crc and bit stuff checking packet
	:send out data packet(OUT, DATA, handshake)
	:rx data packet(IN, DATA, handshake)
	:5284 get_diag_desc to check if error occur

(4) :12026 call get_device_desc():2769
    get the max packet sie

(5) :12078 call tx_pid_test :6211
	:6229 clear all bits in the diag bits
	:6239 run get the configureation descriptor, it required ACT DATA0 DATA1
     PIDs
    :6254 setup endpoint 2 to return stall PIDs
	:6263-6266 send the crc_bitstuff packet to a stakked endpoint to get
	 the stall PID
	:6269 setup endpoint 2 for bulk packet echoing
	:6296,6297 call IN_PID DATA0 to force all endpoint belong to processor
	:6302 restore mormal own operation for all endpoint
	:6316 set endpoint 2 to ignore IN and OUT token
	:6323-6226 send out data packet(OUT DATA handshake)
	:6330 get_diag_desc to check if error occur

(6) :12118 crc_bitstuff_test 

(7) :12349 min_max_data_test : 5534
    :5551 clear all bits
	:5560 test zero length bulk data transfer
	:5572 iso max length(1023) data transfer
	:5588 get_diag_desc to check if error occur    

(8) 12393, 12395, 12399 test address setting after reset

(9) :12444 iso_echo_test

(10) :12489 bto_test :5616 (bus timeout test)
	:5634 clear all error bits
	:5649 config endpoint as an echo enableed bulk out endpoint for packet
	 lengths of length
	:5664 send out OUT token
	:delay (but before bto occur)
	:5670 send out DATA
	:handshake
	:5619 get_diag_desc to check if any error occur
	:5710 send out OUT PID
	: delay after bto occur
	:5716 send out data
	:handshake
	:check error bits
	
(11) :12508 data_toggle_test :5744
	:5768 move ch9 device state from addressed to configured
	:5773 clear all bits 
	:5792 setup endpoint as bidirectional bulk endpoint
	:5827-5836 send a whole packet 
	:5876-5885 send packet as multiple pieces
	:5921,5929 check echo data 
	:6053  get_diag_desc to check if error occur

(12) :12534 handshake_precedence_test:6358
    test cases
	*  Send an in token with bad crc5 to the stalled, disabled and regular
       endpoints.  All of the endpoints should return nothing (BTO).
	* Send a good in token to the stalled endpoint it should return STALL.
	* Send an out token with bad crc5 to the stalled, disabled and regular
	  endpoints.  All of the endpoints should return nothing (BTO).
	* Send a good out token to the stalled endpoint it should return STALL.
	* send a token with bad crc5 to disabled endpoint
	* send out token with bad crc5 to not ready endpoint
	* send out token with bad crc5 to enable endpoint
	* send in token with bad crc5 to enable endpoint
	* Send a good out token to the enabled endpoint it should eventually ACK.
	* Send a good in token to the enabled endpoint it should eventually return 
	  data.    

(13) :12692 single_ended_test:6638
	* :6652 clear all bits
	* :6655 send out OUT token
	* :6660 send out a single ended packet
	* :6665 handshak & check if it bto

(14) :12704 pll_test:6807
	* :6828 clear all bits
	* set Margin clock fast
	* :6843 set CRC and bit stuff checking
	* :6866-6868 send out packet
	* :6890 6891 6901 rx echo data packet
	* :Do the same thing with normal margin clock
	
(15) :12740 bit_stuff_reject_test:7004
	* Send a token packet with 6 consecutive 1's, and confirm that it was
	  rejected by the target.
	* Send a token packet with 7 consecutive 1's, and confirm that it was
      rejected by the target and check that the bit stuff and dfn8 bits 
	  were set.
	* send a packet with bit stuff errors and check that it was rejected by the
	  target.
	*  send a packet with bit stuff errors and check that it was rejected by 
	  the target
	* Start sending a packet then force the idle state.  The prolonged J state
	  will be interpretted as a partial packet with a bit stuff error.  This
	  should be rejected by the target.
	* send the packet again with bit stuff error only on the last bit, and
	  check that it was rejected by the target.

(16) :12851 field_error_reject_test:7387
	* Set CRC and bit stuff checking packet.  This packet generates a bit
	  stuff after the last bit of the packet.
	  To test that invalid PIDs are rejected we will send a token packet with
 	  each of the invalid PID codes to the target followed by a zero length 
	  data packet. The target should ignore both producing a BTO handshake 
	  from the handshake_in procedure.
	* Test that packets with a PID check field error are rejected by the target.	* Test that tokens with a crc5 field error are rejected by the target.
	* Test that packets with a data crc error are rejected by the target.
	* Test that packets with a invalid eop field are rejected by the target.