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<center><font size=+2>USB Test From ARC</font></center>
Arc USB tests consist of the following five tests:
<p>(1)&nbsp;&nbsp; System startup tests
<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; After system reset,
check the following registers
<br>&nbsp;
<table BORDER COLS=3 WIDTH="50%" NOSAVE >
<tr NOSAVE>
<td NOSAVE>
<center>Register</center>
</td>

<td>
<center>Address Offset</center>
</td>

<td>
<center>Expect Value</center>
</td>
</tr>

<tr>
<td>ID_FIELD</td>

<td>
<div align=right>0x00</div>
</td>

<td>
<div align=right>0x04</div>
</td>
</tr>

<tr>
<td>ID_COMP</td>

<td>
<div align=right>0x04</div>
</td>

<td>
<div align=right>0xFB</div>
</td>
</tr>

<tr>
<td>OTG_ICTRL</td>

<td>
<div align=right>0x14</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>OTG_CTRL&nbsp;</td>

<td>
<div align=right>0x1C</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>INT_ENABLE</td>

<td>
<div align=right>0x84</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ERR_STATUS</td>

<td>
<div align=right>0x88</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ERR_ENABLE</td>

<td>
<div align=right>0x8C</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ADDRESSREG</td>

<td>
<div align=right>0x98&nbsp;</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>BDT_PAGE1</td>

<td>
<div align=right>0x9C</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>FRAMENUMLOW</td>

<td>
<div align=right>0xA0</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>FRAMENUMHI</td>

<td>
<div align=right>0xA4</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>TOKEN</td>

<td>
<div align=right>0xA8</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>SOF_THDL</td>

<td>
<div align=right>0xAC</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>BDT_PAGE2</td>

<td>
<div align=right>0xB0</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>BDT_PAGE3</td>

<td>
<div align=right>0xB4</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ENDPCTL0</td>

<td>
<div align=right>0xC0</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ENDPCTL1&nbsp;</td>

<td>
<div align=right>0xC4</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ENDPCTL2</td>

<td>
<div align=right>0xC8</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ENDPCTL3</td>

<td>
<div align=right>0xCC</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ENDPCTL4</td>

<td>
<div align=right>0xD0</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ENDPCTL5</td>

<td>
<div align=right>0xD4</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ENDPCTL6</td>

<td>
<div align=right>0xD8</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ENDPCTL7</td>

<td>
<div align=right>0xDC</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ENDPCTL8</td>

<td>
<div align=right>0xE0</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ENDPCTL9</td>

<td>
<div align=right>0xE4</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ENDPCTL10</td>

<td>
<div align=right>0xE8</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ENDPCTL11</td>

<td>
<div align=right>0xEC</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ENDPCTL12</td>

<td>
<div align=right>0xF0</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ENDPCTL13</td>

<td>
<div align=right>0xF4</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ENDPCTL14</td>

<td>
<div align=right>0xF8</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>

<tr>
<td>ENDPCTL15</td>

<td>
<div align=right>0xFC</div>
</td>

<td>
<div align=right>0x00</div>
</td>
</tr>
</table>

<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Register R/W Test
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Write data 0xff, 0xaa, 0x55, 0x00 with given mask into the following 9
register, then read back and check if they are the same.
<br>&nbsp;
<table BORDER COLS=3 WIDTH="50%" NOSAVE >
<tr>
<td>
<center>Register</center>
</td>

<td>
<center>Address offset</center>
</td>

<td>
<center>MASK</center>
</td>
</tr>

<tr>
<td>ERR_ENABLE</td>

<td>
<div align=right>0x8C</div>
</td>

<td>
<div align=right>0xff</div>
</td>
</tr>

<tr>
<td>&nbsp;ADDRESSREG</td>

<td>
<div align=right>0x98</div>
</td>

<td>
<div align=right>0xef</div>
</td>
</tr>

<tr>
<td>&nbsp;BDT_PAGE1</td>

<td>
<div align=right>0x9c</div>
</td>

<td>
<div align=right>0xff</div>
</td>
</tr>

<tr>
<td>&nbsp;BDT_PAGE2</td>

<td>
<div align=right>0xB0</div>
</td>

<td>
<div align=right>0xff</div>
</td>
</tr>

<tr>
<td>&nbsp;BDT_PAGE3</td>

<td>
<div align=right>0xB4</div>
</td>

<td>
<div align=right>0xff</div>
</td>
</tr>

<tr>
<td>&nbsp;ENDPCTL0</td>

<td>
<div align=right>0xC0</div>
</td>

<td>
<div align=right>0x1f</div>
</td>
</tr>

<tr>
<td>&nbsp;ENDPCTL1</td>

<td>
<div align=right>0xC4</div>
</td>

<td>
<div align=right>0x1f</div>
</td>
</tr>

<tr>
<td>&nbsp;ENDPCTL2</td>

<td>
<div align=right>0xC8</div>
</td>

<td>
<div align=right>0x1f</div>
</td>
</tr>

<tr>
<td>&nbsp;ENDPCTL3</td>

<td>
<div align=right>0xCC</div>
</td>

<td>
<div align=right>0x1f</div>
</td>
</tr>
</table>

<p>(2) USB Simple Device Test
<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * Arc Test bench
<p><img SRC="usb_arc_tb.gif" height=240 width=500>
<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * Device Test :9722
<br>&nbsp;
<center><table BORDER COLS=2 WIDTH="90%" NOSAVE >
<tr>
<td>Test Program Side</td>

<td>Host control side</td>
</tr>

<tr>
<td>USB device setup
<br>&nbsp;<font size=-1> * setup BDT(buffer descriptor register)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp; </font><font size=-2>1stMSByte&nbsp;&nbsp;&nbsp;&nbsp;
into register BDT_PAGE_01(0x9C)</font>
<br><font size=-2>&nbsp;&nbsp;&nbsp;&nbsp; 2nd MSBytes&nbsp; into register
BDT_PAGE_02(0xB0)</font>
<br><font size=-2>&nbsp;&nbsp;&nbsp;&nbsp; 3rd MSBytes&nbsp; into register
BDT_PAGE_03(0xB4)</font>
<br><font size=-2>&nbsp; </font><font size=-1>* Write 0x00 into the following
8 registers:</font>
<br><font size=-2>&nbsp;&nbsp;&nbsp;&nbsp; "OTG_ICTRL"&nbsp;&nbsp;&nbsp;&nbsp;
0x14&nbsp;</font>
<br><font size=-2>&nbsp;&nbsp;&nbsp;&nbsp; "OTG_CTRL"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
0x1c&nbsp;</font>
<br><font size=-2>&nbsp;&nbsp;&nbsp;&nbsp; "CONTROL"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
0x94&nbsp;</font>
<br><font size=-2>&nbsp;&nbsp;&nbsp;&nbsp; "INT_ENABLE"&nbsp;&nbsp;&nbsp;
0x84&nbsp;</font>
<br><font size=-2>&nbsp;&nbsp;&nbsp;&nbsp; "ERR_ENABLE"&nbsp;&nbsp;&nbsp;
0x8C&nbsp;</font>
<br><font size=-2>&nbsp;&nbsp;&nbsp;&nbsp; "ADDRESSREG"&nbsp;&nbsp;&nbsp;
0x98&nbsp;</font>
<br><font size=-2>&nbsp;&nbsp;&nbsp;&nbsp; "FRAMENUMLOW"&nbsp;&nbsp; 0xA0&nbsp;</font>
<br><font size=-2>&nbsp;&nbsp;&nbsp;&nbsp; "FRAMENUMHI"&nbsp;&nbsp;&nbsp;
0xA4&nbsp;</font>
<br><font size=-1>&nbsp; * Write 0x00 to ENDPNT* to disable all ebdpoint</font>
<br><font size=-1>&nbsp; * Write 0x0D to EndPNT(0-3) to enable at most
4 endpoint</font>
<br><font size=-1>&nbsp;&nbsp; * write 0xFF to "INT_STATUS" (0x80) to&nbsp;
clear all irq</font>
<br><font size=-1>&nbsp; * Write 0x01 to "INT_ENABLE" (0x84) to&nbsp;&nbsp;
enable USB rst interrupt</font>
<br><font size=-1>&nbsp;&nbsp; * Write 0x02 to "CONTROL" (0x94) to reset
all BDT ODD ping/pong bits</font>
<br><font size=-1>&nbsp;&nbsp; * Write 0x01 to "CONTROL" (0x94) to enable&nbsp;
VUSB&nbsp;</font>
<br><font size=-1>&nbsp;&nbsp; * Write 0x80 to&nbsp;&nbsp; "OTG_CTRL" (0x1c)
to enable a pull up resistor on D- Data line</font></td>

<td>&nbsp;</td>
</tr>

<tr>
<td></td>

<td>:9796&nbsp; call usb_reset to reset usb</td>
</tr>

<tr>
<td>Interrupt(:142 prog=1)
<br>&nbsp;&nbsp; <font size=-1>* check if it caused by reset</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * Write 0x0D to ENDPNT0(0xC0) to enable
tx/rx/handshaking</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * Write 0xB9 to INT_ENABLE(0x84)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * Write 0x01 to INT_STATUS(0x80) to
clear int bit.</font></td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>Setup Transaction Test</font>
<br><font size=-1>(A) :9290 called tocken_packet task to send out SETUP
token at endpoint 0</font>
<br><font size=-1>(B) :9317 send 1 bytes data packet with DATA0_PID</font>
<br><font size=-1>(C) :9326 called handshake_in_packet task to wait for
USB ACK</font>
<br><font size=-1>(D) repeat (A)--(C) till handshake is done.</font></td>
</tr>

<tr>
<td>Interrupt(prog=2) &lt;indicator setup token done>
<br><font size=-1>* check PID=0x0d(setup token)</font>
<br><font size=-1>* Create send out packet</font>
<br><font size=-2>&nbsp;&nbsp;&nbsp; pid=0&nbsp;&nbsp; with the same paket
length</font>
<br><font size=-1>*set 0x01 to "CONTROL"(0x94)</font>
<br><font size=-1>*clear interrput bit(08==>INT_STATUS)</font></td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>IN Token&nbsp; Transaction</font>
<br><font size=-1>(E) :9372 send out IN_PID tocken</font>
<br><font size=-1>(F) :9374 called data_in_packet Wait for device to respond
data (only data type get checked)</font>
<br><font size=-1>(G) :9425 send USB handshake packet</font></td>
</tr>

<tr>
<td>Interrupt(Prog=3) (Token_done)
<br><font size=-1>* check if it caused by tocken done(and tx)</font>
<br><font size=-1>* setup next recv packet with max length=8</font>
<br><font size=-1>* clear interrput bit(08==>INT_STATUS)</font></td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>DO (A)--(D) excpet different data in data packet and
packet size=2</font></td>
</tr>

<tr>
<td>Interrupt(prog=4)&nbsp;
<br>Same as (prog=2)</td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>DO (E) (F)</font>
<br><font size=-1>&nbsp;:9393 send out imcomplete ACK</font>
<br><font size=-1>&nbsp;DO (E) (F)</font>
<br><font size=-1>&nbsp;DO (G)</font></td>
</tr>

<tr>
<td>Interrupt(prog=5)&nbsp;
<br>Same as (prog=3)</td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>DO (A) --(D) excpet different data in data packet and
packet size=3</font></td>
</tr>

<tr>
<td>Interrupt(prog=6)&nbsp;
<br>Same as (prog=2)</td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>DO (E) (F)</font>
<br><font size=-1>&nbsp;:9393 send out BAD ACK</font>
<br><font size=-1>&nbsp;DO (E) (F)</font>
<br><font size=-1>&nbsp;DO G</font></td>
</tr>

<tr>
<td>Interrupt(prog=7)&nbsp;
<br>Same as (prog=3)</td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>DO (A) --(D) excpet different data in data packet and
packet size=8</font></td>
</tr>

<tr>
<td>Interrupt(prog=8)&nbsp;
<br>Same as (prog=2)</td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>DO (E)-(G)</font></td>
</tr>

<tr>
<td>Interrupt(prog=9)&nbsp;
<br>Same as (prog=2)</td>

<td></td>
</tr>

<tr>
<td></td>

<td>OUT Transaction:
<br>:<font size=-1>9442 send out OUT_PID token</font>
<br><font size=-1>:9449 send out zero length packets at endpoint 0</font>
<br><font size=-1>:9456 wait for USB ACK</font></td>
</tr>

<tr>
<td>Interrupt (prog=10) &lt;token_dne>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * check if caused by token done and
rx packet.</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * write 0x00 to INT_ENABLE(0x84)&nbsp;</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * clear interrupt bit</font>
<br><font size=-2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (0x08==>INT_STATUS
&lt;0x80>)</font></td>

<td></td>
</tr>
</table></center>

<p><font size=-1>Open isuues:</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(1)&nbsp; Only end point 0 get tests</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(2)&nbsp; More tests on out transaction?</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
(3)&nbsp; Do we need to test low speed</font>
<p>(3)&nbsp; Line State test mode :9489
<br>&nbsp;
<center><table BORDER COLS=2 WIDTH="90%" NOSAVE >
<tr>
<td>Test Program Side</td>

<td>vusb_host_ctl.v&nbsp;</td>
</tr>

<tr>
<td>Turn on Host mode
<br><font size=-2>(MainEntry.cpp 1031-1065)</font>
<br><font size=-2>&nbsp;&nbsp;&nbsp; </font><font size=-1>* Read USB_INFO(0x0C)
to see if USB_HOST is supported</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * Write 0x08 to CONTROL(0x94) to enable
host mode</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; *&nbsp; Write 0x20 to OTG_INT_EN(0x14)
to enable the interrupt on line state change</font></td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>set to k-state :9505</font>
<br><font size=-1>delay 10000 ns</font>
<br><font size=-1>reset :9507&nbsp;</font>
<br><font size=-1>set to j-state</font></td>
</tr>

<tr>
<td>Interrupt (prog=11)
<br>&nbsp;&nbsp; <font size=-1>* check OTG_ISTAT(0x10) if it cause by line
state changed</font>
<br><font size=-1>&nbsp;&nbsp; * READ CONTROL reg(0x94) check if the second
MSB(&amp;0x40 is in SE0 state ) is set.</font>
<br><font size=-1>&nbsp;&nbsp; * READ OTG_STAT reg(0x18) and check "line
state stable bit"(mask 0x20) is set</font>
<br><font size=-1>&nbsp;&nbsp; * Clear interrupt bit in both INT_STATUS
and OTG_ISTAT(0x10)</font></td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>Reset USB :9516</font>
<br><font size=-1>set to j-state</font></td>
</tr>

<tr>
<td>Interrupt(prog=12)
<br>&nbsp;&nbsp;&nbsp; * <font size=-1>READ OTAG_ISTAT(0x10), check if
it caused by line state changed(mask 0x20)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; *&nbsp; READ CONTROL reg(0x94)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; check if the 1st
MSB(&amp;0x80 is in J state ) is set.</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * READ OTG_STAT reg(0x18) and check
"line state stable bit"(mask 0x20)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * Write 0x20 to INT_ENB(0x84) reg,
to enable resume interrupts</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * clear int bits in both INT_STATUS
and OTG_ISTAT</font></td>

<td></td>
</tr>

<tr>
<td></td>

<td>set to k-state :9531</td>
</tr>

<tr>
<td>Interrupt (Prog 13)
<br><font size=-1>&nbsp;&nbsp;&nbsp; * Read INT_STATUS to check if it is
resume interrupt(mask 0x20)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * READ CONTROL reg(0x94)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; check J/SE0(0x80
0x40) state is not set</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * READ OTG_STAT reg(0x18) and check&nbsp;
"line state stable bit" not set</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * write 0x00 to INT_ENB(0x84) reg,
to turn off resume interrupt</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * write 0x00 to OTG_CTRL(0x1C)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * clear intrrupt bits(both)</font></td>

<td></td>
</tr>
</table></center>

<p>(4)&nbsp; OTG Test (:9588)
<br>&nbsp;
<center><table BORDER COLS=2 WIDTH="90%" NOSAVE >
<tr>
<td>Test Program Side</td>

<td>Verilog side</td>
</tr>

<tr>
<td><font size=-1>&nbsp; *&nbsp; Write 0x80 to OTG_ICTRL(0x14) to turn
on ID interrupt</font>
<br><font size=-1>&nbsp; *&nbsp; Write 0x08 to OTG_CTRL(0x1c) to turn on
vbus power.</font></td>

<td><font size=-1>Set otg_test timeout 20,000,000ns</font></td>
</tr>

<tr>
<td></td>

<td><font size=-1>In vusb_otg_lpbck.v,</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; :156 usb_id(id pin from mini connect)
will be asserted,</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; :otg_stable_id_r will be set to 1
after 1st 1ms (vusb_up_int_bvci.v:3833)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; :hc_otg_stable_id will be set to 1</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; interrupt is asserted at vusb_up_int_bvci.v:1861</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; (more than 1ms, host controller enable
and id pin stabled)</font></td>
</tr>

<tr>
<td>Interrupt (Prog 14 :425)
<br><font size=-1>&nbsp; * Check if it trigger by id pin</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; write 0 to OTG_CTRL (0x1c) to turn
off VBUS and data line termintation resistors.</font>
<br><font size=-1>&nbsp; * READ OTG_STAT(0x18) check if ID(mask 0x80) is
turned off</font>
<br><font size=-1>&nbsp;&nbsp; * clear interrupt bits(both)</font></td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>After 2ms, interrupt should be triggered again</font></td>
</tr>

<tr>
<td>Interrupt : (Prog 15 :457)
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp; * check if it trigger by id
pin</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp; * write 0x02 to OTG_CTRL(0x1c)
to charge vbus signal through a resistor</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp; * write 0x08 to OTG_ICTRL(0x14)
to enable session enable interrupt and also turn off id pin interrupt.</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * Read OTG_STAT(0x18) check if ID(mask
0x80) is turn off.</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * clear interrupt bits (Both)</font></td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>In vusb_otg_lpbck.v:158 , usb_session_vld get turn on.</font>
<br><font size=-1>&nbsp;After 2ms, vusb_up_int_bvci.v:1899, usb_sess_vld_int_r
get asserted.</font></td>
</tr>

<tr>
<td>Interrupt(Prog 16 :500)&nbsp;
<br>otg session valid interrupt
<br>&nbsp;&nbsp;&nbsp; <font size=-1>* check if trigger by otg session
valid interrupt</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * write 0 to OTG_CTRL(0x1c)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * Read from OTG_STAT(0x18) check if
sess_valid get cleared(mask 0x08)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; clear interrupt bits.(both)</font></td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>After 2ms, interrupt should be triggered again</font></td>
</tr>

<tr>
<td>Interrupt(Prog 17: 532)
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp; * check if trigger by otg session
valid interrupt</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * write 0x01 to OTG_CTRL(0x1c) to
discharge vbus via resistor</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * write 0x01 to OTG_ICTRL(0x14) to
turn on A_VBUS_VLD_EN interrupt</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * Read from OTG_STAT(0x18) check if
sess_valid get cleared(mask 0x08)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * clear interrupt bit. (both)</font></td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>In vusb_otg_lpbck.v:160 usb_a_vbus_vld will be asserted</font>
<br><font size=-1>After 2ms, otg_a_vbus_vld should get be triggered</font></td>
</tr>

<tr>
<td>Interrupt (Prog 18:574)
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp; * check if trigger by usb_a_bus_vld
interrupt</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; *&nbsp;</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * write 0 to OTG_CTRL(0x1c)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * READ OTG_STAT(0x18) check if usb_a_bus_vld
get clear(mask 0x01)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * clear interrupt bit(both)</font></td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>After another 2ms, interrupt again</font></td>
</tr>

<tr>
<td>Interrupt (Prog 19:607)
<br><font size=-1>&nbsp;&nbsp;&nbsp; * check if trigger by usb_a_bus_vld
interrupt</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * write 0x04 to OTG_ICTRL(0x14) to
turn on B_Session_end_en interrupt</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * READ OTG_STAT(0x18) check if usb_a_bus_vld
get clear(mask 0x01)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * clear interrupt bits(both)</font></td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>After 2ms (vusb_up_int_bvci.v :1809), usb_b_sess_end_int
should be triggered</font></td>
</tr>

<tr>
<td>Interrupt :649 (progress 20)
<br><font size=-1>&nbsp;&nbsp;&nbsp; * check if it triggered by usb_b_sess_end_int(mask
0x04)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * write 0 to OTG_CTRL(0x1c)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * READ OTG_STAT(0x18) check if usb_b_sess_end_int&nbsp;
get clear(mask 0x04)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * clear interrupt bits (both)</font></td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>After another 2ms, interrupt again</font></td>
</tr>

<tr>
<td>Interrupt : (Prog 21 :682)
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp; * check if it triggered by usb_b_sess_end_int(mask
0x04)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp; * READ OTG_STAT(0x18) check
if usb_b_sess_end_int&nbsp; get clear(mask 0x04)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * write 0x00 to OTG_ICTRL(0x14) to
turn off all interrupt</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * clear interrupt bits(both)</font></td>

<td></td>
</tr>
</table></center>

<p>(5) Simple Host echo test (:9600)
<br>&nbsp;
<br>&nbsp;
<center><table BORDER COLS=2 WIDTH="90%" NOSAVE >
<tr>
<td>
<center>Test program side</center>
</td>

<td>
<center>Verilog Side
<br><font size=-2>(vusb_host_ctl.v is used as device)</font></center>
</td>
</tr>

<tr>
<td>Host setup
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; *&nbsp; write 0x00 to
CONTROL(0x94) to disbale vusb core.</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; *&nbsp; Call HostUsbInit()
in usb_init.cpp:199 to set up usb 1.1 Host.</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * write 0xff to ERR_STAT(0x88)
to clear the error reg.</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * write 0x0E to INT_STAT(0x80)
to clear TOK_DNE, SOF_TOK error int</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * write 0x0E to INT_ENB(0x84)&nbsp;
to setup TOK_DNE, SOF_TOK error int</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * write 0x30 to OTG_CTRL(0x1c)
to turn off/down resistors</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * write 0x1b to CONTROL(0x94)
to set host mode and reset</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * wait 100 cycles</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * write 0x09 to CONTROL(0x94)
to enable host mode(turn off reset)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (after reset it
should sent out SOF tocken )</font></td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>* Set 4ms timeout before vusb switch to device mode.</font>
<br><font size=-1>* Wait for SOF with (SOF_PID, #1, at endpnt 0)</font></td>
</tr>

<tr>
<td>Interrupt(Prog=22)
<br><font size=-1>&nbsp;&nbsp;&nbsp; * check if caused by&nbsp; SOF_TOK(0x04)</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * write 0x10(out token) to TOKEN(0xA8)
to start OUT Token transaction</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * clear interrupt bit</font></td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>* Then wait for out tocken(OUT_PID, #0, endpnt=0)</font>
<br><font size=-1>* Wait for DATA from host (DATA0_PID, rev_length, 0)&nbsp;</font>
<br><font size=-1>* When it done, it will trigger Token done interrupt</font></td>
</tr>

<tr>
<td>Interrupt(Prog=23)
<br><font size=-1>&nbsp;&nbsp;&nbsp; * check if caused by TOKEN_DNE and
tx&nbsp;</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * write 0x90(in token) to TOKEN(0xA8)
to start IN Token transaction</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * clear interrupt bit</font></td>

<td></td>
</tr>

<tr>
<td></td>

<td><font size=-1>* Wait for IN tocken:9675 (IN_PID, 0, 0)</font>
<br><font size=-1>* Copy the rx data to tx buffer.</font>
<br><font size=-1>* Send out packet with PID=DATA0_PID, endpoint=0</font>
<br><font size=-1>* When Rx is doen, TOK_DONE interrupt will be trigered.</font></td>
</tr>

<tr>
<td>Interrupt(Prog=24)
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * check if it caused by
TOK_DONE and rx packet</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * check data in rcv packet
is the same as sendout.&nbsp;</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * write 0x00 to CONTROL(0x94)
to disable host mode</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp;&nbsp; * write 0x00 to INT_ENB to disable
all interrupts</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * clear interrupt bit</font>
<br><font size=-1>&nbsp;&nbsp;&nbsp; * Finish tests</font></td>

<td></td>
</tr>
</table></center>

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