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<center>
<h1>
MI Verification</h1></center>
<a href="http://therouter/bb/rf/doc/hw/mi-spec.html">MI Specification</a>
<br>&nbsp;
<h3>
TODO</h3>
MI_VTIMER_REG
<br>MI_AVCTRL_REG
<br>Reset values of registers
<br>Virage store controller, Charge pump and NV array
<h3>
Register Tests</h3>
<i>IOSIM Only (?)</i>
<p><b>Non-secure Mode Testing</b>
<p>MI_MODE: Only bit 11 (CLR_DPINTR) has a function in BCP. For all other
bits check that writes are ignored and reads return 0.
<p>MI_VERSION: Check all writes are ignored. Read should return a known
result: 0x0202b0b0.
<p>MI_INTR: Check that writes are ignored. Reads are checked through interrupt
tests (see later).
<p>MI_MASK: This register has unique (ehh!) behavior. Writes set up the
interrupt mask bits. Reads return the interrupt mask bits. These are probably
tested in other tests, but we should independently set and clear all mask
bits and check the results through read. Check that bits 31:12 are ignored
on write and bits 31:6 return 0 on read.
<p>MI_ENTR: Check that writes are ignored. Reads are checked through interrupt
tests.
<p>MI_EMASK: This has the same behavior as MI_MASK, but it defines additional
BCP only interrupts.
<p>MI_CTRL: Check bits 31:19 and bits 7:0 ignore writes and return 0 on
reads. Bits 18:13 should be tested through the general register test for
write/read, since they have no side effects. Side effects of bits 12:8
are tested later.
<p>MI_SEC_MODE: Check that writes are ignored. Seems we must write, then
read, which will cause an entry into secure mode. Since the read still
returns we can check that the write was ignored. Reads have the side effect
of arming the logic to enter secure mode, and are tested later.
<p>MI_SEC_TIMER: Check that writes are ignored and reads return 0.
<p>MI_SEC_FLASH: Check that writes are ignored and reads return 0.
<p>MI_ERR_ADDR: Check that writes are ignored. Behavior on read is tested
below under write error testing
<p>MI_ERR_DATA: Behavior is tested below under write error testing
<p><b>Secure Mode Testing</b>
<p>Access to MI_MODE, MI_VERSION, MI_INTR, MI_MASK, MI_CTRL, MI_ERR_ADDR,
MI_ERR_DATA should be the same as above, so re-run identical tests.
<p>MI_SEC_MODE: This register appears differently in secure mode. Check
bits 31:7 writes are ignored and reads return 0. Bit 6 EN_IRAM and bit
1 RESET are tested in the SRAM access tests above. Other bits have side
effects are tested in secure mode entry/exit tests below.
<p>MI_SEC_TIMER: Check writes to 31:24 are ignored, set 23:16 to zero,
run register test on 15:0. Other patterns have side effects, so are tested
below under secure timer.
<p>MI_SEC_FLASH: XXX Unknown as yet
<br>&nbsp;
<h3>
SRAM/ROM/Virage RAM Testing</h3>
<i>IOSIM Only (?)</i>
<p>MI has several SRAM blocks. The requirement is to test that the address
and data lines are wired correctly and that all possible access types (byte,
half-word, work, block) work correctly. Since the SRAMs have different
access functionality dependent on the mode (secure mode or not) and on
the state of the EN_IRAM bit in the MI_SEC_MODE register. Access functionality
needs to be tested as well. For the SRAMs we have the following properties
<p><b>ISRAM</b>, 32kByte R/W: byte, half-word, word, block accesses. Accessible
in secure mode and in non-secure mode if EN_ISRAM bit is set
<p><b>BSRAM</b>, 64kByte R/W: byte, half-word, word and block accesses.
Accessible in secure mode only. Access is at address 0x1fc20000 if RESET
in MI_SEC_MODE is set (which is the pin reset condition). If RESET is not
set then BSRAM is accessible at 0x1fc00000.
<p><b>BROM</b>, 16kByte RO (may change to 8kByte): word and block accesses.
Accessible in secure mode only. Access is at address 0x1fc00000 if RESET
in MI_SEC_MODE is set. If RESET is not set BROM is accessible at 0x1fc20000.
<p><b>Virage0</b>, 512 bits R/W: word and block accesses. Accessible in
secure mode only. Access is at address 0x1fc80000.
<p><b>Virage1</b>, 512 bits R/W: word and block accesses. Accessible in
secure mode only. Access is at address 0x1fc90000.
<p><b>Virage2</b>, 2048 bits R/W: word and block accesses. Accessible in
secure mode only. Access is at address 0x1fca0000.
<p><b>Address/Data R/W testing</b>
<p>To test appropriate address wiring, run the following address patterns,
doing read/write for SRAMs:
<br>&nbsp;
<blockquote>byte: 0, b1, b11, b111, etc
<br>half-word: 0, b10, b110, b1110, etc
<br>word: 0, b100, b1100, b11100, etc
<br>8 byte block: 0, b1000, b11000, b111000, etc
<br>16 byte block: 0, b10000, b110000, b1110000, etc
<br>32 byte block: 0, b100000, b1100000, b11100000, etc</blockquote>

<p><br>To test data line wiring use the standard register test (see Haishan's
IOSIM document), that as a minimum usese a walking 1's pattern across all
data lines in a 32 bit word, with the address fixed at the first location
in the SRAM block.
<p>For BROM, read only and match against known contents at the given locations.
<p><b>Access testing</b>
<p>To test access in secure mode and non-secure mode do at least the following:
<p>1. In secure mode, run all sram testing ensure everything passes.
<br>2. In non-secure mode, with EN_ISRAM bit turned off, do word write/read
first location of each SRAM and make sure all fail.
<br>3. In non-secure mode, with EN_ISRAM bit turned on, do word write/read
first location of each SRAM and make sure only ISRAM passes. Run complete
SRAM test on ISRAM from non-secure mode.
<br>4. For BSRAM check access at address 0x1fc20000 when RESET is set and
0x1fc00000 when RESET is not set.
<br>5. Check read only access to BROM at address 0x1fc00000 when RESET
is set and 0x1fc20000 when RESET is not set.
<h3>
Functional Tests</h3>

<h3>
<i>PIF RAM Access</i></h3>
The MI provides mechanisms to trap accesses to PIF RAMwhich on N64 was
located at 0x1fc0_07c0-7ff. On BB this space is occupied by the BRAM/BROM.
The address trapping is provided to help debug applications/games that
write to this address space. There are two mechanisms to trap writes and
one mechanism to trap reads. The mechanisms are defined by bits in the
MI_CTRL register.
<p><b>Writes</b>
<p>There are 2 mechanisms to trap writes to PIF RAM:
<ol>
<li>
Secure Kernel Trap - set SKI_PIF bit in MI_CTRL</li>

<li>
Write Error interrupt - set WEI_PIF bit in MI_CTRL</li>
</ol>
In both cases information on the cause of the error is recorded in
<ul>
<li>
MI_ERR_ADDR</li>

<li>
MI_ERR_DATA</li>

<li>
MI_ERR_INFO registers. These capture the address of first write error,
the data of the first single write error (does not capture data for block
writes)</li>
</ul>
Since the PIF RAM size is small (64 Bytes) all possible combinations of
byte, half-word, word, and block (8, 16, 32) writes can be tested for all
possible locations.
<p>For each case check:
<ol>
<li>
The secure kernel trap or interrupt is generated correctly</li>

<li>
The contents of the MI_ERR_ADDR, MI_ERR_DATA and MI_ERR_INFO registers
are correct.</li>

<li>
For the secure kernel trap, check that the STRAP bit is set in MI_SEC_MODE</li>

<li>
The interrupt is cleared (on reading MI_ERR_INFO) or secure mode can be
exited and NMI goes away.</li>
</ol>
XXX Does it make any sense to test with both bits set?
<p><b>Reads</b>
<p>Setting the BER_PIF bit in the MI_CTRL register will result in BUS errors
being returned to the CPU on PIF RAM accesses. This is best tested by running
code on the CPU, since the IOSIM socket does not return an SYSAD information.
<br>&nbsp;
<h3>
<i>Illegal Block Request</i></h3>
<i>CPU and IOSIM</i>.
<p>MI has mechanisms to trap on block writes to non-memory spaces and generate
Bus errors on block reads. The actions taken are controlled by bits set
in the MI_CTRL register. Definition of a non-memory space is anything which
is not in the following areas:
<ol>
<li>
0x1fc00000 to 0x1fcfffff</li>

<li>
0x0 to 0x3000000</li>

<li>
0x80000000 to 0xffffffff</li>
</ol>
<b>Writes</b>
<p>The two possible actions on illegal block writes are:
<ol>
<li>
Secure Kernel Trap - Set bit SKI_BNM</li>

<li>
Write Error Interrupt - Set bit WEI_BNM</li>
</ol>
For each of these 2 cases we check:
<ol>
<li>
The secure kernel trap or interrupt is generated correctly</li>

<li>
The contents of the MI_ERR_ADDR, MI_ERR_DATA and MI_ERR_INFO registers
are correct.</li>

<li>
For the secure kernel trap, check that the STRAP bit is set in MI_SEC_MODE</li>

<li>
The interrupt is cleared (on reading MI_ERR_INFO) or secure mode can be
exited and NMI goes away.</li>
</ol>
Since the size of non-memory regions are large and it is not possible to
cover all addresses exhaustively, so we can use randomly generated addresses,
with a different random seed each time. The test cases should cover all
combinations for block write (8, 16, 32 bytes).
<p><b>Reads</b>
<p>Since we cannot record Bus errors through IOSIM, Block reads must be
tested using code on the CPU.
<h3>
<i>Interrupt Control</i></h3>
<i>CPU Only.</i>
<p>XXX We should cover 1 case from each of INT0 - INT4. Focus on the new
units. Since all interrupts will be tested in the individual unit tests
here we should just make sure the interrupt lines are wired up correctly
to the CPU.
<p>Test enabling, masking, polling status in MI_INTR, MI_MASK.&nbsp; Need
separate test for each device (VI, PI, SP, SI, AI, DP, etc) to raise an
interrupt.&nbsp; Test should be extended to include new interrupts when
defined.&nbsp; Test should also verify clearing the DP interrupt using
the MI_MODE register.
<h3>
<i>Cold Reset/DIV_MODE</i></h3>
<i>CPU Only.</i>
<p>Test that DIV_MODE in MI_CTRL is set properly on cold reset, appropriate
signals are set to mips core.&nbsp; Verify that all MI registers on restored
to initial state.
<h3>
<i>Warm Reset</i></h3>
<i>CPU Only.</i>
<p>Like the cold reset test, but don't test DIV_MODE
<h3>
<i>Secure Mode Entry/Exit</i></h3>
<i>CPU Only (Other tests cover this in IOSIM)</i>
<p>Verify secure kernel entry from non-secure mode for each cause: app
triggered, timer triggered, emulation trap, fatal error.&nbsp; The different
cases are:
<ol>
<li>
Application triggered entry/exit. This is covered in the many IOSIM tests
already.</li>

<li>
Emulation trap triggered. This is covered in the IOSIM PIF RAM access tests
and the Illegal block request tests.</li>

<li>
Secure Timer. This is covered in the IOSIM Secure Timer tests.</li>

<li>
Fatal. Fatal is caused by errors from the PI. A secure kernel trap can
be generated by setting the SK bit in the PI_ERROR register.</li>
</ol>
In each of the cases above we must make sure that on entry the MI_SEC_MODE
register is set correctly, and that on exit NMI is cleared.
<h3>
<i>Secure Timer</i></h3>
<i>IOSIM Only (except for a few values to check SK trap, see above?)</i>
<p>The Secure Timer uses a pre-scaler to divide the system clock that then
drives a count down register that is initialized with a start value. The
pre-scaler and the timer are both 16 bits. The behavior of the pre-scaler
and the start value can be verified by using a walking 1 through each of
them independently, with the other set to a fixed value. The time between
setting the register and generating the trap should be checked.
<p>The equation defining the total time is: system_clk_period*(pre-scaler+1)*start_value
(XXX this does not seem to be correct).
<p>The current value of the count is given in bits 31:16 of the MI_SEC_TIMER
register on read. It should be verified that these count down correctly.
<p>The timer can be stopped at anytime by writing 0 to the pre-scaler.
This should be verified for at least one case.
<h3>
<i>Virage0/Virage1 Recall/Store</i></h3>
Verify that the 16x32 SRAM can be read and written for both devices.&nbsp;
Verify that recall with known content works correctly.&nbsp; Verify that
store works correctly by performing a recall, rewriting the SRAM, performing
a store, clearing the SRAM and performing another recall.
<h3>
<i>Virage2 Recall/Store</i></h3>
Verify that the 64x32 SRAM can be read and written.&nbsp; Verify that recall
with&nbsp; known content works correctly.&nbsp; Verify that store works
correctly by pushing a write through the controller and recalling it.
<br>&nbsp;
<h1>
Test List</h1>
<b>Reset Register Test</b>
<p>Fill registers with RANDOMs (where it makes sense), do pin reset, check
that all registers come up with correct values.
<p><b>Register Test</b>
<p>Check register bits in Secure and Non-secure mode.
<p>Use standard register_test from bcp_util.c to check r/w and r/o bits.
<p>For mask registers (MI_INTR_MASK, MI_INTR_EMASK) set and clear each
bit.
<p>For Secure mode register, check that writing 1's does not change the
state of bits 2-7.
<p><b>PIF RAM Access test</b>
<p>Check Secure Kernel Trap and Interrupt on PIF RAM access. Write all
locations using byte, half-word, triple byte, word, double word, quad word
and 32 bytes.
<p>Check multiple writes. Make sure first write is captured.
<p>Check Error registers for correct values
<p><b>Block Write Error test</b>
<p>Check SK trap and Interrupt on Block writes to non-memory spaces.
<p>Uses randoms, 100 runs per night. Check all block sizes (8, 16, 32).
<p>Check correct values in Error registers.
<p><b>SRAM Access tests</b>
<p>From Secure Mode check all SRAMS (including virage SRAMS) by walking
ones through address bits and data bits.
<p>Check RESET bit for relocation of Boot ROM and Internal SRAM.
<p>Check that setting IRAM_EN bit, enables access to SRAM from non-secure
mode. Resetting bit disables access.
<p>Check that all other SRAMs and Boot ROM are not accessible from non-secure
mode.
<p><b>Secure Timer tests</b>
<p>Check pre-scaler by walking ones through all bits. Check timer by walking
ones through all bits.
<p>In all cases check timer trap is generated correctly.
<p>Check that the count down is really counting down.
<br>Check that writing zero to scaler stops the timer.
<p><b>BROM Read test</b>
<p>Check that the values read from BROM are the same as the ones programmed.
<p><b>DP/SP/VI Interrupt Test</b>
<p>Check DP Interrupt gets generated and can be cleared by bit in MI_MODE
register. Check that mask works.
<p>Check SP Interrupt generation, clearing and masking.
<p>Check VI Interrupt generation, clearing and masking.
<p><b>NV Recall Test</b>
<p>Do a recall and check that correct signals bits are asserted at correct
times.
<p><b>NV Store Recall Test</b>
<p>Do a store and recall by directly programming Charge Pump and NV array.
<p><b>NV Compare Test</b>
<p>Do a standard compare, check that correct signals are asserted at correct
times, check for MATCH.
<p><b>NMS Store Test</b>
<p>Do a standard store using NMS. Check that values are correctlly stored.
using NMS recall operation.
<br>Three versions:
<ol>
<li>
Default parameters</li>

<li>
Typical fixed set of parameters</li>

<li>
Random Test with random selection for vpp_sel, vpp_max and increment.&nbsp;
Set number of dumb pulses to maximum. Program in nms register interface
and check vpp levels in sequence as they appear in CP_VPPSEL bits.</li>
</ol>

<p><br><b>NMS Compare Test</b>
<p>Do an NMS recall operation to get values into the SRAM.
<p>Use the store controller to do a compare. Check that signal timing is
correct.
<p><b>NMS Recall Auto Margin Test</b>
<p>Do Recall auto margin, check for correct timing of signals.
<br>Use this test to check nms_crm* registers. Program random set of BIAS,
TECC, MRCL settings in NMS_CRM* registers and check the outputs in the
nv_mrcl, nv_tecc and nv_bias bits in sequence and verify with respect to
inputs.
<p><b>NMS Keep mode Test</b>
<p>Put NMS in keep mode, check that SRAM array can be read. Put array back
in idle, check that array can be read.
<p><b>MI_SEC_VTIME register</b>
<br>Vary the sysclk from 62.5 to 100Mhz and check that tests pass with
various programmings of VTIME register.
<br>&nbsp;
<br>&nbsp;
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