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	Project BB - SI DV Plan
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	Project BB - SI DV Plan
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	<b>Broad<i>On</i> confidential</b>
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<p>
<b><u> SI Related DV Tasks </u></b>
<p>
<li> add controller backdoor to IPC interface,
	one interface for both local and JoyChannel controllers;
<li> implement new SI functional tests;
<li> implement SI random tests for system stress;

<p>
<b><u> The JoyChannel Controller Model (jctrl.v) </u></b>
<p>
	The top level simulation model instantiates three behavioral
	JoyChannel controllers, <i>vsim.jctrl1</i>, <i>vsim.jctrl2</i>
	and <i>vsim.jctrl3</i>. The behavioral model allows control over
	several modes and button events. The list below descibes all DV
	accessible registers and their default settings. Refer to the
	<i>N64 JoyChannel Protocol Specification</i> for details.
<dl>
<dt> <code>vsim.jctrlX.jctrl_mon</code>, set by +jctrl_mon
<dd> local controller monitor;
<br>
	Setting jctrl_mon to 1 enables logging of JoyChannel controller
	events into the simulation log.
<p>
<dt> <code>vsim.jctrlX.enable</code>, default 0
<dd> flag to disable (0) or enable (1) the controller;
<br>
	This should be used to test the <i>no response</i> flag in the
	SI status of the channel.
<p>
<dt> <code>vsim.jctrlX.div</code> [3:0], default 9 to divide by 10
<dd> controller internal speed;
<br>
	This divider controls the speed of the channel. A 10MHz clock is
	divided by (div + 1) to create the clock for the serial protocol.
	The divider should be used to test minumum and maximum channel
	speeds. For example, 10MHz / (9 + 1) = 1us per pulse. Each bit
	requires four pulses, ie. 1us * 4 = 4us, ie. 250kbits/s.
<p>
<dt> <code>vsim.jctrlX.type_l</code>, default 0x02
<dt> <code>vsim.jctrlX.type_h</code>, default 0x00
<dt> <code>vsim.jctrlX.status</code>, default 0x00
<dd> type low, type high and status;
<p>
<dt> <code>vsim.jctrlX.button</code>, default 0x0000
<dd> buttons pressed, one bit per button
<p>
<dt> <code>vsim.jctrlX.x</code>, default 0
<dt> <code>vsim.jctrlX.y</code>, default 0
<dd> x/y position of joystick;
<p>
<dt> <code>vsim.jctrlX.rsp_random</code>, default 0
<dd> response randomization;
<br>
	Tells the model to randomize bit stream timing and delay behavior
	within legal JoyChannel limits. This should be set in system DV,
	as it changes SI and controller event timing. This option can be used
	in master mode.
<p>
<dt> <code>vsim.jctrlX.rsp_echo</code>, default 0
<dd> response echo;
<br>
	Tells the model to respond with the byte received in the command.
	Specifically, cmd[1:0] encodes the number of tx/rx bytes, 0 means one
	byte, 3 means 4 bytes. This should be used to test JoyChannel commands
	other than the suported RESET, QUERY and STATUS. This option cannot
	be used in master mode.
<p>
<dt> <code>vsim.jctrlX.collide</code>, [3:0], default 0
<dd> force JoyChannel collision;
<br>
	When bit 3 is 1, the controller forces a JoyChannel collision
	during bit [2:0] of the command phase. This should be used to
	test the <i>collision error</i> bit in the SI for the channel.
<p>
<dt> <code>vsim.jctrlX.framerr</code>, [5:0], default 0
<dd> force JoyChannel frame error;
<br>
	When bit 5 is 1, the controller forces a JoyChannel frame error
	during bit [4:0] of the response phase. This should be used to
	test the <i>frame error</i> bit in the SI for the channel.
<p>
<dt> <code>vsim.jctrlX.glitch_detect</code>, default 1
<dd> enable/disable glitch detection;
<br>
	This bit durns on (1) or off (0) glitch detection.
	It should be set to 0 for JoyChannel error testing.
<p>
<dt> <code>vsim.jctrlX.reset</code>, default 0
<dd> force JoyChannel reset;
<br>
	Set this bit to 1 to force a JoyChannel reset (0 on wire).
	This overwrites all other activity but does not stop it.
	DV environment is responsible for timing. The model does not
	need to be enables for the reset to work.
<p>
<dt> <code>vsim.jctrlX.master</code>, default 0 (slave)
<dd> puts controller into master mode for si slave testing;
<br>
	When this bit is set the mode switches from slave mode to master mode.
<p>
<dt> <code>vsim.jctrlX.tx_size</code>
<dd> transmit size in byte in master mode;
<p>
<dt> <code>vsim.jctrlX.tx_data[0:35]</code>
<dd> transmit data in master mode, 0=cmd 1..35=data;
<p>
<dt> <code>vsim.jctrlX.tx_on</code>
<dd> master transmission start;
<br>
	Set this bit to 1 to start command transmission in master mode.
	This bit is cleared when transmission is finished. A 64us JoyChannel
	protocol delay between transmissions must be observed by the dv
	environment.
<p>
<dt> <code>vsim.jctrlX.rx_size</code>
<dd> number of bytes in received response;
<p>
<dt> <code>vsim.jctrlX.rx_last</code>
<dd> number of response bytes in addition to cmd byte;
<br>
	This variable has to be set to the number of data bytes.
<p>
<dt> <code>vsim.jctrlX.rx_data[0:35]</code>
<dd> response data from master, 0=cmd, 1..35=data;
</dl>

<p>
<b><u> The Local Controller Model (lctrl.v) </u></b>
<p>
	The top level simulation model instantiates one behavioral model
	for the local controller, <i>vsim.lctrl</i>. The model allows
	control over several modes, button events and x/y motion events.
	The list below descibes all DV accessible registers and their
	default settings. Refer to the <i>N64 JoyChannel Protocol
	Specification</i> for details.
<p>
	The local controller is always enabled. The SI needs four JoyChannel
	clocks for de-glitching of the x/y inputs. The fastest simulation of
	x/y stick motion thus requires (tXfer + tHigh + tXfer + tLow)ns for
	one count of x/y position change.
<dl>
<dt> <code>vsim.lctrl.lctrl_mon</code>, set by +lctrl_mon
<dd> local controller monitor;
<br>
	Setting lctrl_mon to 1 enables logging of local controller
	events into the simulation log.
<p>
<dt> <code>vsim.lctrl.button</code>, default 0x0000
<dd> buttons pressed, one bit per button;
<p>
<dt> <code>vsim.lctrl.xmove</code>, default 0
<dd> x stick move control;
<br>
	negative values simulate stick move to the left, positive to the right;
<br>
	set to 0 when motion simulation is finished;
<br>
	can be set to values larger than the x counter limits
	to test that the counter does not overflow;
<p>
<dt> <code>vsim.lctrl.ymove</code>, default 0
<dd> y stick move control;
<br>
	negative values simulate stick move down, positive up;
<br>
	set to 0 when motion simulation is finished;
<br>
	can be set to values larger than the y counter limits
	to test that the counter does not overflow;
<p>
<dt> <code>vsim.lctrl.inmotion</code>, default 0
<dd> busy with motion;
<br>
	set as long as there is motion to simulate;
<br>
	xmove and ymove can be overwritten at any time;
<p>
<dt> <code>vsim.lctrl.jitter</code>, default 0
<dd> random jitter mask;
<br>
	mask applied to a 32-bit random;
<br>
	the result is a time in ns that is added to the pulse timing values
	to jitter the x/y motion pulses;
<p>
<dt> <code>vsim.lctrl.tLow</code>, default JCHAN_PERIOD * 4
<dd> inactive time between motion pulses;
<p>
<dt> <code>vsim.lctrl.tXfer</code>, default JCHAN_PERIOD * 4
<dd> lead/tail time between pulse signals;
<p>
<dt> <code>vsim.lctrl.tHigh</code>, default JCHAN_PERIOD * 4
<dd> active time of both pulse signals;
<p>
<dt> <code>vsim.lctrl.xglitch[1:0]</code>, default 0
<dd> x[1:0] glitch insertion;
<br>
	set to one to cause a glitch on the respective x pulse signal;
<br>
	clears itself after pulse has been sent out;
<p>
<dt> <code>vsim.lctrl.yglitch[1:0]</code>, default 0
<dd> y[1:0] glitch insertion;
<br>	set to one to cause a glitch on the respective y pulse signal;
<br>
	clears itself after pulse has been sent out;
</dl>

<p>
<b> JoyChannel Tests </b>
<p>
<dl>
<dt> J1. test SI_STATUS after reset;
<dd> all bits should be 0,
<dt> J2. test register bits;
<dd> test all read/write bits of all defined registers; SI_DRAM_ADDR,
	SI_CONFIG, SI_CTRL; <br>
	test SI_DRAM_ADDR address rounding, returns 0 for bits [2:0].
<dt> J3. test SI write DMA;
<dd> setup SI protocol buffers in memory; <br>
	issue SI write DMA by writing SI_DMA_WRITE; <br>
	check that dma is busy, DMA_BUSY=1; <br>
	wait for dma completion or time out, DMA_BUSY=0; <br>
	check that DMA_ERR is correct; <br>
	check that interrupt flag is set, INT=1; <br>
	check that SI interrupt is seen in MI; <br>
	check data in SI buffers by reading them through PIO space; <br>
	check that SI_STATUS is cleared after writing to it; <br>
<dt> J4. test SI read DMA;
<dd> a previous SI write DMA has moved protocol data to the SI; <br>
	choose a memory different from the write DMA; <br>
	issue SI read DMA by writing SI_DMA_READ; <br>
	check that dma is busy, DMA_BUSY=1; <br>
	the read dma triggers the communication to the the controllers; <br>
	wait for dma completion or time out, DMA_BUSY=0; <br>
	check that DMA_ERR is correct; <br>
	check that interrupt flag is set, INT=1; <br>
	check that SI interrupt is seen in MI; <br>
	compare data in memory with SI buffers; <br>
	check that SI_STATUS is cleared after writing to it; <br>
	check that controller response is correct for the commands issued; <br>
<dt> J5. test DMA conflicts;
<dd> repeat test 4, but write SI_DRAM_ADDR, SI_DMA_WRITE or SI_DMA_READ
	while the dma is busy; <br>
	test 3 cannot be used, because write dma is done too quickly; <br>
	the original DMA should complete; <br>
	in addition, the DMA_ERR bit should be 1 to indicate conflict; <br>
<dt> J6. test controller bits;
<dd> repeat test 4 and/or 5; <br>
	set bits through controller backdoor; <br>
	check each type, status, button, x, and y bit in main memory;
<dt> J7. test controller errors;
<dd> set error modes in the JoyChannel controllers; <br>
	force frame errors, collisions and no responses; <br>
	check that the SI sets the appropriate error bits; <br>
<dt> J8. test all controller commands;
<dd> repeat tests J3 and J4 with all supported commands; <br>
	check that response from controller is correct;
<dt> J9. test SI channel resets;
<dd> start a SI read DMA similar to test J4; <br>
	write the SI_CTRL register with JCRST bit=1; <br>
	the SI stops communication, the controller will time out; <br>
	check that all controllers return no response; <br>
	release JCRST bit=0; <br>
	start another SI read DMA, which should complete normally;
<dt> J10. test single command errors
<dd> setup memory with byte 0 of controller 0 set to 0x00; <br>
	start si write dma, followed by si read dma; <br>
	check that 0xff is returned in the read dma data of all controllers; <br>
<dt> J11. random tests
<dd> repeat above tests with randoms for memory addresses, controller
	status and responses,
</dl>

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	Problems and comments to
<a href="mailto:berndt@broadon.com">
	berndt@broadon.com
</a>
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