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  <title>SI System Level DV Test Plan</title>
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<center><font size="+2">SI System Level DV Test Plan</font></center>

<p>Reference: <br>
     <a href="../hw/si-spec.html">SI Spec</a>
     <br>
     <a href="si-dv.html">SI DV Test Plan</a>
     <br>
         Verilog test file(vsim/tests/si_test.v) </p>

<p>To do list: <br>
         (1) <strike>Frank will make SI worked both in master and slave mode.</strike>
     &nbsp;Both Frank and Bill have provided master models for slave mode
testing.  &nbsp;I am using Bills model for basic operation and Franks model
for random  bit time, bit time violations(frame error), truncated commands,
collisions,  some resets, and reserved commands.<br>
         (2) Jctrl compatibility test <br>
         (3) Try to use serial protocol to monitor outgoing data. <br>
         (4) CPU level test. (Waiting until Frank integrating R4300 is done)
  <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * Write MIPS code to
driven    SI,  compile and link with existing libultra. <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; *&nbsp; Load final rom
 into   flash  <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; *&nbsp; Let MIPS run
it.   <br>
         (5) Done: &nbsp;<strike>Haishan write backdoor ipc task for jctrl.
 </strike><br>
         (6) Rumble pak support. (After Frank done with hardware)<br>
         (7) Done: <strike>Update Local Controller tests after Frank makes
 changes</strike><br>
         (8) Done: <strike>Iorand tests</strike></p>
     <a href="#SI_System_Level_DV_Test_Plan">SI System Level DV Test Plan</a>
     <br>
     <a href="#SI_System_Level_DV_Test_Descriptions">SI System Level DV Test
  Descriptions</a>

<p><br>
     </p>

<h3><a name="SI_System_Level_DV_Test_Plan"></a>
      SI System Level DV Test Plan</h3>

<p>1. SI Register test</p>

<p>&nbsp;&nbsp;&nbsp; *&nbsp; SI_STATUS register (0x4800018). <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (1)&nbsp; READ when test
  starts  and check that it is 0 after system start(/reset). <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (2)&nbsp; Write data
to  SI_STATUS  with the following pattern, and read back and check data (should
 be  ignored)  <br>
         &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    cycle through defined bits setting each to 1 while other defined bits
are    set to 0 and unused bits are set to x<br>
         &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    cycle through defined bits setting each to 0 while other defined bits
are    set to 1 and unused bits are set to x<br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     one bit(from bit 0 to 31) is 1, all others are 0 <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     one bit is 0, all others are 1<br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (3)&nbsp; &nbsp;use register_test
 routine to test that rw bits can be toggled to 1 and 0, &nbsp;that  ro bits
 can't be written, and try random write patterns.<br>
  <br>
  </p>

<p>&nbsp;&nbsp;&nbsp;&nbsp; *&nbsp; SI_DRAM_ADDR <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (1)&nbsp; Verify that bits
[2:0]  are ignored in DMAs (i.e verify 8-byte align is forced)<br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (2)&nbsp; Fill pattern as above
   (2 and 3) and make sure data reads as expected. <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (3)&nbsp; Test addr crossing
 page(2k)     boundary<br>
         &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    -- Actual write/read done in SI DMA test case: SiTestDmaSpecificAddrs
</p>

<p>&nbsp;&nbsp;&nbsp;&nbsp; * SI_DMA_WRITE, SI_DMA_READ, SI_RAM <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Will be tested
in  DMA  part   </p>

<p>&nbsp;&nbsp;&nbsp;&nbsp; * SI_CONFIG (0x480001C) <br>
         &nbsp;&nbsp;&nbsp;&nbsp; * SI_CTRL(0x0480000C) <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; As in (2 and 3) for&nbsp;
 SI_STATUS,    test all defined bits of SI_COFNIG and SI_CTRL.&nbsp;</p>

<p>       &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; For RW bit, test if
it was   correctly  set. <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R only bit, check if
it  can   be  changed. <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; When tests are done,
set  to  "reset"  status. <br>
         &nbsp; <br>
         &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    Test Case for all of "SI Register test":&nbsp;&nbsp;&nbsp; SiTestRegisters</p>

<p>2. PIO test <br>
         &nbsp;&nbsp;&nbsp; R/W to SI_RAM (from 0x1fc007c0 to 0x1fc007ff),
 and verify that write is ignored and reads return 0.</p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test case for
    &nbsp;"PIO test": &nbsp;&nbsp;&nbsp; done in SiTestRegisters <br>
     </p>

<p>3.&nbsp; SI DMA test </p>

<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; *&nbsp; 3.1 DMA Write test <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 3.1.1Set
   SI_DMA_ADDR   to the following kinds of addr: <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     (1)&nbsp; Perfect address&nbsp; (align 8)<br>
         &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    Test Case: &nbsp;SiTestValidCtrlCmds<br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     (2)&nbsp; Not align to 8 byte(test all cased from 1-7)<br>
         &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    Test Case: &nbsp;SiTestDmaSpecificAddrs<br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     (3)&nbsp; Cross 2k page boundry<br>
         &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    Test Case: &nbsp;SiTestDmaSpecificAddrs<br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     (4)&nbsp; x36 mode address<br>
         &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    Test Case: &nbsp;SiTestDmaSpecificAddrs<br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     (5)&nbsp; x64 mode address (lower 16 MBytes)<br>
         &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    Test Case: &nbsp;SiTestDmaSpecificAddrs <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     (6)&nbsp; Cross DDR bank(at least, check bank 0/1&nbsp;&nbsp; and&nbsp;
   2/3&nbsp; cross)<br>
         &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    Test Case: &nbsp;SiTestDmaSpecificAddrs <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     (7)&nbsp; Other boundaries: 16bytes, 32bytes, 64bytes, 128bytes, 256bytes
     , 512bytes, 1K, 4K, 8K, 16K, 32K, 64K, 128K, 256K, 512K, 1M, 2M, 4M<br>
         &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    Test Case: &nbsp;SiTestDmaSpecificAddrs<br>
        &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
    (8)&nbsp; Walk 1&#8217;s: Test SI DMA Writes (and Reads) with starting addresses
    defined by the bit sequence below (r stands for random). Do this for both
 x36 and x64 addresses.<br>
         &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    Test Case: &nbsp;<span class="SpellE">SiTestDmaWalkBits</span></p>

<p style="margin-left: 1.5in; "><span style="font-family: &quot;Courier New&quot;; ">
        00000000000000000000000000000000<br>
         00000000000000000000000000001000<br>
         0000000000000000000000000001r000<br>
         000000000000000000000000001rr000<br>
         00000000000000000000000001rrr000<br>
         0000000000000000000000001rrrr000<br>
     <span style="mso-spacerun:yes">&nbsp;</span><span style="mso-spacerun:yes">
        &nbsp;&nbsp; </span>:<br>
         0000000001rrrrrrrrrrrrrrrrrrr000<br>
         000000001rrrrrrrrrrrrrrrrrrrr000<br>
         00000001rrrrrrrrrrrrrrrrrrrrr000<br>
         00000010rrrrrrrrrrrrrrrrrrrrr000<o:p></o:p></span></p>

<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
    (9)&nbsp; Walk 0&#8217;s: Test SI DMA Writes (and Reads) with starting addresses
    defined by the bit sequence below (r stands for random). &nbsp;Do this
 for both x36 and x64 addresses.<br>
         &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    Test Case: &nbsp;<span class="SpellE">SiTestDmaWalkBits</span></p>

<p style="margin-left: 1.5in; "><span style="font-family: &quot;Courier New&quot;; ">
        00000010111111111111111111100000<br>
         000000101111111111111111110rr000<br>
         00000010111111111111111110rrr000<br>
         0000001011111111111111110rrrr000<br>
         000000101111111111111110rrrrr000<br>
         00000010111111111111110rrrrrr000<br>
     <span style="mso-spacerun:yes">&nbsp;</span><span style="mso-spacerun:yes">
        &nbsp;&nbsp; </span>:<br>
         0000001010rrrrrrrrrrrrrrrrrrr000<br>
         000000100rrrrrrrrrrrrrrrrrrrr000<br>
         00000010rrrrrrrrrrrrrrrrrrrrr000<br>
         0000000rrrrrrrrrrrrrrrrrrrrrr000<br>
     <o:p></o:p></span></p>

<p><br>
        &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 3.1.2 Fill
a   pattern   into memory via memory backdoor access. <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Then,
 write    any value(including x,z values) to SI_DMA_WRITE address, read data
 from&nbsp;    SI_STATUS, then check the following items <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     (1)&nbsp; DMA_BUSY is set or not (value might be depend on each cases,
  double  check DMA can be started) <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     (2)&nbsp; If DMA_BUSY is set, poll until done with a timeout. <br>
      &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     Check that finishes within reasonable time. <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     (3)&nbsp; Check if DMA_ERR is 0 <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     (4)&nbsp; Check if INT is set and also check on reply code to see if
int    is set. <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     Write any value to clear SI_STATUS, then read back to see if all bits
 are   expected(e.g, INT is clear?, etc)</p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case: &nbsp;SiTestValidCtrlCmds,
    &nbsp;SiTestDmaSpecificAddrs, &nbsp;<span class="SpellE">SiTestDmaWalkBits</span>
        , &nbsp;SiRandomTests, SiTestDmaXs, and most other test cases<br>
     </p>

<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; *&nbsp; 3.2 DMA Read Test <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Test
 all   the  different address cases(refer to DMA write) with: <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
 (1)   All  joychannels with valid supported command (0/1/255)<br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     * Set data to SI controller by SI controller backdoor(at least walk
through      all buttons). <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     * Write any data to SI_DMA_WRITE(to see if DMA&nbsp;can be started)
<br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     * Test DMA_BUSY is set or not <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     * If DMA_BUSY is set(read from&nbsp; SI_STATUS), then polling until
is   done   <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     * check is DMA_ERR is 0 <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     * check INT bit (remember to check from reply code also) <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     *&nbsp; compare data in memory with SI buffer. <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     *&nbsp; check if response is correct for each channel. <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     reply and also compare with data you pre-set via si controller backdoor.&nbsp;</p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case:&nbsp;&nbsp;&nbsp;
    SiTestValidCtrlCmds<span class="GramE">, &nbsp;SiTestDmaSpecificAddrs</span>
        , &nbsp;<span class="SpellE">SiTestDmaWalkBits</span><br>
     </p>

<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (2) Pick
up a few typical case in (1) , when DMA_BUSY is set, do <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     Write to any of DMA register(DMA_DRAM_ADDR, SI_DMA_WRITE, SI_DMA_READ,
  <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     Then read SI_STATUS, check if DMA_ERR bit is set of not.</p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case:&nbsp;&nbsp;&nbsp;
    SiTestDmaBusyError<br>
     <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (3)
Test   invalid  command for each joychannel and local ctrlr and combinations.</p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case:&nbsp;&nbsp;&nbsp;
    SiTestInvalidCtrlrCmds,&nbsp; SiTestCtrlrErrViaBD<br>
     </p>

<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (4)&nbsp;
     Set error mode, then create error cases(illegal rx/snd size, frame errors,
     collisions, reset and timeout), then check to see if the second byte
of   reply is correctly set.</p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case:&nbsp;&nbsp;&nbsp;
    SiTestInvalidCtrlrCmds,&nbsp; SiTestCtrlrErrViaBD</p>

<p>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;(5) Test unsupported pass through
   commands (i.e. 4 - 254)<br>
     </p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case:&nbsp;&nbsp;&nbsp;
    SiTestValidCtrlCmds<span class="GramE">, &nbsp;</span>SiTestInvalidCtrlrCmds,&nbsp;
   SiTestCtrlrErrViaBD</p>

<p>4. SI channel reset test <br>
         &nbsp;&nbsp;&nbsp;&nbsp; Start a DMA read with button/stick query
 for all controllers. &nbsp;Set the JCRST bit in SI_CTRL to start a joy channel
 reset. &nbsp;Reset the JCRST bit after 805 us. &nbsp;Check the result of
the DMA read and verify that all controllers &nbsp;have the controller reset
error bit set. &nbsp;Do another DMA read with button/stick query and verify
that it completes normally.<br>
   </p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case:&nbsp;&nbsp;&nbsp;
    SiTestJChannelReset<br>
     </p>

<p>5. Local controller Tests <br>
         &nbsp;&nbsp;&nbsp;&nbsp; Set data(e.g, button press, etc) via local
  controller   backdoor. (walk through all buttons &amp;&amp; random patterns)
 <br>
         &nbsp;&nbsp;&nbsp;&nbsp; Check results with what was set through
the   backdoor. </p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case:&nbsp;&nbsp;&nbsp;
   &nbsp;Cycles through all buttons in SiTestDmaSpecificAddrs. &nbsp; Most
 other  tests also test local controller buttons and x,y.</p>

<p>&nbsp;&nbsp;&nbsp;&nbsp; Local controller single command dectection test.
     <br>
         &nbsp;&nbsp;&nbsp;&nbsp; With SI_CONFIG bit 23 set to 0, issue a
command  with block byte (byte 0) set to 0. &nbsp;Verify that the command
works normally.<br>
   &nbsp; &nbsp; &nbsp;With SI_CONFIG bit 23 set to 1, issue a command&nbsp;
 with byte 0&nbsp; set to  0, check that all returned bits are 1s.</p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case:&nbsp;&nbsp;&nbsp;&nbsp;
    SiTestSingleCmdDetection<br>
     </p>

<p>&nbsp;&nbsp;&nbsp; SI_CONFIG [21:16]&nbsp; button rate control. <br>
         &nbsp;&nbsp;&nbsp; Set it to different rates, then measure the how
 long  in sim time it takes to see the data via DMA. Check if is in reasonable
    range</p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case:&nbsp;&nbsp;&nbsp;
   SiTestLCtrlButRate <br>
     </p>

<p><span style="mso-spacerun:yes">&nbsp;&nbsp;&nbsp; </span>JSRST (L, R,
START pressed at same time reset stick reference)<br>
     <span style="mso-spacerun:yes">&nbsp;&nbsp;&nbsp; </span>Test that if
 the    L, R, and START buttons are pressed <span class="GramE">simultaneously<span style="mso-spacerun:yes"></span>
      on</span> the Local controller, the stick reference is reset.</p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case:&nbsp;&nbsp;&nbsp;&nbsp;
   SiTestLCtrlJSRST<span class="GramE"></span></p>

<p>&nbsp;&nbsp;&nbsp; Test local controller button sample deglitching.<br>
      &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Set buttons to 0<br>
      &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Set button rate to 1 unless specified
   otherwise<br>
      &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Use default jc_div = 31, tXfer
 =  tHigh  = tLow = 2000,<br>
      &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
jitter    = 0<br>
     &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Set buttons on via bd for 1.25
sample   period, verify no<br>
      &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; change in button state<br>
      &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Set buttons off via bd, verify
 no  change in button state<br>
      &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Verify buttons don't show up
in  dma  button query within<br>
      &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; the max time they would have
shown    up if we didn't turn them off.<br>
      &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Set buttons on for 2.25 sample
 period,   verify they don't show as on<br>
      &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; set buttons off, verify they
don't    show as on<br>
      &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Verify buttons don't show up
in  dma  button query within<br>
      &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; the max time they would have
shown    up if we didn't turn them off.<br>
     </p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case:&nbsp;&nbsp;&nbsp;
   SiTestLCtrlButDeglitch<br>
     </p>

<p>&nbsp; &nbsp; Test local controller X,Y movement<br>
      &nbsp; &nbsp; &nbsp;For (+x, -y), (+x, +y), (-x, -y), and (-x, +y)&nbsp;
   counts:<br>
      &nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Cmd x,y to move part way
 to  limit via bd and see that<br>
      &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; lctrl DMA button/xy query indicates
  that  they get there.<br>
      &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; Do an lctrl button test without
changing    x,y input and<br>
      &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; verify that x,y in lctrl DMA button/xy
   query doesn't change<br>
      &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; Cmd x and y beyond x,y limits and
 see   that the querried<br>
      &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; value pegs at the limits.&nbsp;
Verify    that subsequent movement<br>
      &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; behaves normally.<br>
     <br>
      &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;Use jitter during the tests</p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   SiTestLCtrlJsxy<br>
     <span class="GramE"></span></p>

<p>&nbsp;&nbsp;&nbsp; Test local controller X,Y sample deglitching.<br>
     &nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Use backdoor parameters:<br>
     &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; xglitch[0],&nbsp; xglitch[1]
  , yglitch[0], and yglitch[1]<br>
     &nbsp; &nbsp; &nbsp; &nbsp;&nbsp; to create glitches on the respective
 x  and y pulse signals.<br>
     &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;Verify that the X and Y do not change.&nbsp;
  <br>
     </p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case:&nbsp;&nbsp;&nbsp;
   SiTestLCtrlJsxyDeglitch<br>
      &nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; <br>
     </p>

<p>6. Test Slave mode <br>
         &nbsp;&nbsp;&nbsp; Using Bill's master model, in slave mode setup
 jctrl  1 to receive cmds from the master. &nbsp;Request the master model
to send  each of the valid cmds (0,1,255), &nbsp;get the response from the
local controller,  prepare and transmit the response to the master, retrieve
and verify the data received by the master. &nbsp;Test getting the lctrl
response in a separate  DMA after receiving the cmd from the master. &nbsp;Test
getting the lctrl  response for button/joystick x,y in the same DMA in which
the master cmd is received.</p>

<p>&nbsp;&nbsp;&nbsp; While doing slave mode transactions verify expected
  behavior of all assoiated register bits and interrupts. This includes at
 least, SI_CONFIG JC_SLAVE, &nbsp;SI_CTRL XMIT, BUSY, REQ, SI_STATUS bits
assoiated with DMA's used during slave mode transactions, and interrupt indications.</p>

<p>&nbsp; &nbsp; Test Joy Channel resets commanded by master while in slave
  mode. <br>
    </p>

<ol>
      <li>with rcv active (before cmd rqstd) start a reset, after reset should
  have completed, check, should get reset error bit set (plus maybe no response)</li>
      <li>with rcv active (before cmd rqstd) start a reset, after it should
 have completed, rqst cmd and check, should get reset error bit set (plus
maybe no response</li>
      <li>with rcv active (before cmd rqstd) start a reset, during reset,
check,  should get reset error bit set (plus maybe no response)</li>
      <li>before start cmd receive start a reset, start rcv during reset,
check,  should get reset error bit set</li>
      <li>reset during reception of a cmd from the master, (use Franks backdoor
  reset for this one)</li>

</ol>
   &nbsp; &nbsp;Using Frank's master model:
<ol>
     <li>Use the backdoor rsp_random setting to test randomly stretched bit
 pulses within the spec limits.</li>
     <li>Use the backdoor to generate bit timing violations to test the frame
 error detection. Verify that the frame error bit gets set.</li>
     <li>Use the backdoor to disable the master model during a command transmition
 to the slave to test truncated commands. &nbsp;Verify that truncated commands
 cause a no response error and&nbsp; that a good command can be received after
 64us.</li>
     <li>Use the backdoor to force a collision during trasnmission of the
slave  response to the master. &nbsp;Verify that the collision error is indicated
 in the error bits.</li>
     <li>Verify that the SI can receive random commands in the range 4 to
254  with the number of bytes received indicated by bits [2:0] of the cmd.<br>
     </li>

</ol>

<p></p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case:&nbsp;&nbsp;&nbsp;&nbsp;
  SiTestSlave<br>
     </p>

<p>7 Random tests <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Run tests with random controller
cmds,   random expected responses via backdoor, random failures, random addresses
  for write and read DMA buffers. </p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case:&nbsp;&nbsp;&nbsp;&nbsp;
    SiTestRandom<br>
     </p>

<p>8. Iorand test. <br>
         &nbsp;&nbsp; &nbsp;Pick up a few typical cases, and fit it into
iorand  test frame.   <br>
     </p>

<p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case:&nbsp;&nbsp;&nbsp;&nbsp;
  SiTestRandEnv runs the following tests in the Iorand environment:</p>

<blockquote>
  <blockquote>SiTestRandom(1, ForceFail_None, 0, 0);<br>
    SiTestRandom(1, ForceFail_None, StartWithXs, 0);<br>
    SiTestValidCtrlCmds(1, 0, 0, 0);<br>
    SiTestInvalidCtrlrCmds(1, 0, 0, 0);<br>
    SiTestCtrlrErrViaBD(1, CtrlQueryStatus, 0, 0);<br>
    SiTestDmaBusyError(1, SI_DMA_WR_REG, PIF_RAM_START, 0);<br>
    SiTestSingleCmdDetection(1, 1, 0, 0);<br>
    SiTestJChannelReset(1, 0, 0, 0);<br>
    SiTestDmaStress(num_iterations);<br>
        <br>
        </blockquote>
        </blockquote>

    <p>9. Test SI interrupt mask/unmask<br>
      &nbsp;&nbsp;&nbsp; Test that when the SI interrupt mask bit is set
in  the  MI_INTR_MASK_REG, the interrupt shows up in the lsb of int_l.<br>
      &nbsp;&nbsp;&nbsp; Test that when the SI interrupt mask bit is not
set   in  the MI_INTR_MASK_REG, the interrupt does not show up in the lsb
of int_l.</p>

    <p>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; Test Case:&nbsp;&nbsp;&nbsp;&nbsp;
   All DMA tests check for the existance of the interrupt after each DMA.<br>
      &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
   &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
   &nbsp;A SiTestRandom() test is run with the SI int mask bit not set to
test   that case.<br>
     <br>
     </p>

    <p>&nbsp; </p>

    <p><br>
     </p>

    <h3><br>
     </h3>

    <h3><a name="SI_System_Level_DV_Test_Descriptions"></a>
      SI System Level DV Test Descriptions</h3>

    <h3>Overview</h3>
   The nightly SI regressions are run by invoking the function SiRunTests()
 which then invokes the set of tests &nbsp;to be performed. &nbsp; &nbsp;Either
 iosim with the input file "bcp_si.tst" or the executable "si_test" can be
 used to invoke SiRunTests().<br>
     <br>
      To get debug outputs, use -d 0x0141 on the isoim or si_test cmd line.<br>
       <br>
         SiRunTests ( testmask, levels, reserved, seed)<br>
     <br>
      &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; if seed not 0, use seed to initialize
   with srandom<br>
     <br>
      &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; run a test if testmask == 0 or
 bit(test_num)   is set in testmask<br>
      &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; and levels == 0 or test_lvl &lt;
  levels.  For example:<br>
      &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; levels
==  0<br>
      &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   run lvl 0, 1, 2, 3, ...<br>
      &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; levels
==  1<br>
      &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   run lvl 0<br>
      &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; levels
==  2<br>
      &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   run lvl 0, 1<br>
      &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; levels
==  3<br>
      &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   run lvl 0, 1, 2
    <blockquote>levels is also passed to most test routines so it can limit
  the  amount of test cases based on level. &nbsp;Most test routines ignore
  the levels arg, but it is used by some tests.<br>
       </blockquote>
       <br>
       <tt>&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; test_num&nbsp; test_lvl<br>
      &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp;&nbsp;
 /<br>
         </tt><tt>   &nbsp;&nbsp;&nbsp; TEST( 29, 0, SiTestRegisters &nbsp;
 &nbsp; &nbsp; &nbsp; </tt><tt>&nbsp;( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
         </tt><tt>   &nbsp;&nbsp;&nbsp; TEST(&nbsp; 0, 0, SiTestValidCtrlCmds&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );</tt><br>
         <tt>   &nbsp;&nbsp;&nbsp; TEST(&nbsp; 1, 0, SiTestInvalidCtrlrCmds&nbsp;&nbsp;
  ( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST(&nbsp; 2, 2, SiTestCtrlrErrViaBD&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, CtrlQueryStatus,&nbsp; 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST(&nbsp; 3, 1, SiTestCtrlrErrViaBD&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, CtrlReset,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST(&nbsp; 4, 0, SiTestCtrlrErrViaBD&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, CtrlQueryButtons, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST(&nbsp; 5, 1, SiTestCtrlrErrViaBD&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, CtrlJcUnsupCmd,&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST(&nbsp; 6, 1, SiTestCtrlrErrViaBD&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, CtrlNoXmitRand,&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST(&nbsp; 7, 2, SiTestDmaBusyError&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, SI_DMA_WR_REG,&nbsp;&nbsp;&nbsp; SI_RAM,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0) );<br>
      &nbsp;&nbsp;&nbsp; TEST(&nbsp; 8, 1, SiTestDmaBusyError&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, SI_DMA_RD_REG,&nbsp;&nbsp;&nbsp; SI_RAM,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0) );<br>
      &nbsp;&nbsp;&nbsp; TEST(&nbsp; 9, 0, SiTestDmaBusyError&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, SI_DRAM_ADDR_REG, 0x40,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0) );<br>
      &nbsp;&nbsp;&nbsp; TEST( 10, 1, SiTestSingleCmdDetection ( levels,
0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST( 11, 0, SiTestSingleCmdDetection ( levels,
1,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST( 12, 0, SiTestJChannelReset&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST( 13, 0, SiTestDmaSpecificAddrs&nbsp;&nbsp;
(  levels,   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST( 14, 0, SiTestDmaSpecificAddrs&nbsp;&nbsp;
(  levels,   1,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST( 15, 0, SiTestDmaWalkBits&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST( 16, 3, SiTestDmaWalkBits&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, 1,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST( 17, 1, SiTestDmaWalkBits&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   1,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST( 18, 1, SiTestDmaWalkBits&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, 1,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   1,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST( 19, 1, SiTestRandom&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   (&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 5, ForceFail_None,&nbsp;&nbsp; StartWithXs,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST( 20, 2, SiTestRandom&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   (&nbsp;&nbsp;&nbsp;&nbsp; 10, ForceFail_None,&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST( 21, 3, SiTestRandom&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   (&nbsp;&nbsp;&nbsp;&nbsp; 10, ForceFail_Random, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST( 22, 2, SiTestRandom&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   (&nbsp;&nbsp;&nbsp;&nbsp; 10, ForceFail_None,&nbsp;&nbsp; JChannel_Resp_Rand,
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST( 23, 2, SiTestLCtrlJSRST&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST( 24, 1, SiTestLCtrlButRate&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST( 25, 1, SiTestLCtrlJsxy&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, LCTRL_SOMEJITTER, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
      &nbsp;&nbsp;&nbsp; TEST( 26, 2, SiTestRandom&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   (&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1, ForceFail_ClearSiIntMask, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
       </tt><tt>&nbsp;&nbsp;&nbsp; TEST( 27, 2, SiTestLCtrlButDeglitch&nbsp;&nbsp;
   ( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
       </tt><tt>&nbsp;&nbsp;&nbsp; TEST( 28, 2,&nbsp;SiTestLCtrlJsxyDeglitch</tt><tt>
      &nbsp;( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );</tt><br>
         <tt>&nbsp;&nbsp;&nbsp; TEST( 30, 2,&nbsp;SiTestBugFixes &nbsp; &nbsp;
 &nbsp; &nbsp;&nbsp;</tt><tt>   &nbsp;( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );</tt><br>
         <tt>&nbsp;&nbsp;&nbsp; TEST( 31, 2,&nbsp;SiTestSlave &nbsp; &nbsp;
 &nbsp; &nbsp; &nbsp; &nbsp;</tt><tt>   &nbsp;( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );</tt><br>
         <br>
   &nbsp;<br>
     &nbsp;<br>
     Tests other than the register tests use a common set of lower level
routines   for:<br>

      <ul>
         <li>Initializing test data structures and default parameter values</li>
         <li>Setting up simulation backdoor parameters per the intent of
the   test</li>
         <li>Setting up failure cases if the test specifies<br>
         </li>
         <li>Setting up DMA buffers</li>
         <li>DMA write (with timeout) to provide controller commands to SI</li>
         <li>DMA read (with timeout) to get results of controller commands</li>
         <li>Check DMA results with expected values</li>

      </ul>
      Tests fill in an SiDmaTestParam data structure that specifies everything
   about a DMA write, DMA read, &nbsp;backdoor setup, forced failures, and
 all  expected results of the DMA read (including expected failures). &nbsp;
 That  data structure is then passed to lower level routines to perform the
 test.  &nbsp; Sometimes aspects of the test need to be checked specifically
 by the  high level test routine, but frequently, no additional checks are
 required  other than what is done by the low level routines.<br>
       <br>
      Since all the tests use common low level routines, every test automatically
   checks most aspects of the DMA's and other common aspects of tests. &nbsp;For
   Example:<br>

      <ul>
         <li>Before every DMA start:</li>

        <ul>
           <li>DMA_ERR bit is checked</li>
           <li>DMA_BUSY bit is checked</li>
           <li>SI interrupt in MI_INTR_REG is checked</li>
           <li>interrupt in lsb of int_l is checked</li>

        </ul>
         <li>After every DMA start:</li>

        <ul>
           <li>DMA_ERR bit is checked</li>
           <li>DMA_BUSY bit is checked</li>

        </ul>
         <li>On every DMA completion:</li>

        <ul>
           <li>&nbsp;there is a timeout on DMA_BUSY</li>
           <li>DMA_ERR bit is checked</li>
           <li>SI status reg interrupt pending bit is checked</li>
           <li>SI interrupt in MI_INTR_REG is checked</li>
           <li>interrupt in lsb of int_l is checked</li>
           <li>status is cleared</li>

        </ul>
         <li>When appropriate, after DMA read completion</li>

        <ul>
           <li>guard bands arround DMA buffer are checked</li>
           <li>data in DMA buffer is compared to expected values</li>

        </ul>

      </ul>
      The checks take expected failures into consideration when testing error
  cases.<br>
       <br>
      Most tests supply random values for parameters that are not specifically
   being tested. &nbsp;For example, if we are specifically testing local
controller    X,Y movement, the joy channel controllers are issued random
commands with    random expected values setup via backdoor writes. &nbsp;The
results of those   commands are automatically checked. &nbsp;While we are
doing most tests,  local controller button and X,Y movement are tested with
random expected  values setup via backdoor. &nbsp;X,Y movement tests can
span multiple unrelated  test cases. &nbsp;The results are automatically
checked.<br>
       <br>
     When checking local controller X,Y movement during any test, verifies
 that  the expected X,Y is reached within the expected max time and that
the  position  doesn't change after reaching the expected position until
the next  backdoor  X,Y move commands are issued. &nbsp;During movement,
each X,Y sample  is checked  to see that it is moving closer to the target
values. &nbsp; Once an X,Y movement is started during a test, no new X,Y
movement backdoor cmds will be issued until the previous movement has been
completely verified or a reset has been performed. &nbsp;When resets are
commanded, it is verified  that X,Y goes to and stays at 0.<br>
       <br>
     When checking local controller buttons, it is verified that the expected
  button values show up within the computed max time for 3 button samples.<br>
       <br>
     Random DMA buffer addresses are used except when testing specific DMA
buffer  locations.     <br>
     Memory size is determinined dynamically and random addresses are taken
 from  the memory available.  <br>
       <br>
      There are several global parameters that have a default value that
can   be  temporarily modified during specific tests or for debugging<br>
       <br>

      <blockquote>use_rsp_echo[4]&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
   &nbsp; default: &nbsp;&nbsp;&nbsp; { 0, 1, 1, 1 }<br>
     Set array element 1 - 3 to 0 to disable use of response echo for corresponding
   jc ctrlr.<br>
         <br>
       use_rsp_rand[4]&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
&nbsp;    &nbsp;default:&nbsp;&nbsp; &nbsp;[ 0, 0, 0, 0 ] <br>
       Set array element 1 - 3 to non-zero to enable response randomization
 for   the corresponding jc ctrlr. &nbsp;This is normally only turned on for
 specific   tests, as it increases the time required to perform the tests.<br>
         <br>
      no_random_jsrst&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
  &nbsp;default:&nbsp;&nbsp;&nbsp; 0<br>
      Set to non-zero to prevent Joystick reset button combinations (JSRST
 -  Start,  L, and R) when using random button values in tests. &nbsp; &nbsp;Even
  if no_random_jsrst is zero, a JSRST button combination will not be produced
  by the random buttton generator if it has done so within the last 20 calls.<br>
         <br>
      random_seed&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
&nbsp;&nbsp;&nbsp;   &nbsp; &nbsp; default:&nbsp;&nbsp;&nbsp; 0x0badface<br>
      This is the random seed that is used unless it is overridden by passing
  a non-zero seed parameter to SiRunTests or a specific test.<br>
         <br>
      si_use_io_read_io_write&nbsp;&nbsp; default:&nbsp;&nbsp;&nbsp; 0<br>
      Set to non-zero to force use of IO_READ/IO_WRITE rather than backdoor
 writes  or extended read/writes.<br>
         <br>
      stop_tests_on_err&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp; &nbsp; &nbsp;
 &nbsp;default:&nbsp;&nbsp;&nbsp;  0<br>
       Set to non-zero to terminate entire test run at end of a test that
fails.<br>
         <br>
       stop_test_on_err&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; &nbsp;
&nbsp;   &nbsp; &nbsp;default:&nbsp;&nbsp;&nbsp; 0<br>
       Set to non-zero to terminate the current test on detection of a failure.<br>
         <br>
         <br>
         </blockquote>

        <h3>Description of each test</h3>
         <br>
         <tt><br>
         <b>TEST(&nbsp; 29, 0, SiTestRegisters&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );</b></tt>
        <blockquote>Do a pin reset and then check SI_STATUS, SI_CONFIG, and
 SI_CTRL for correct reset initialization.<br>
           <br>
  For SI_STATUS, SI_CONFIG, SI_CTRL, and SI_DRAM_ADDR<br>

          <ul>
              <li>Write data with the following pattern, and read back and
 check data for correct values  </li>

          </ul>
         &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    cycle through defined bits setting each to 1 while other defined bits
are    set to 0 and unused bits are set to x<br>
         &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;
    cycle through defined bits setting each to 0 while other defined bits
are    set to 1 and unused bits are set to x<br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     one bit(from bit 0 to 31) is 1, all others are 0 <br>
         &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
     one bit is 0, all others are 1<br>

          <ul>
              <li>use register_test routine to test that rw bits can be toggled
 to 1 and 0, &nbsp;that  ro bits can't be written, and try random write patterns.</li>

          </ul>
   R/W to SI_RAM (from 0x1fc007c0 to 0x1fc007ff), and verify that write is
 ignored and reads return 0.<br>
          </blockquote>
           <tt>&nbsp;<b><br>
         <b>TEST(&nbsp; 0, 0, SiTestValidCtrlCmds&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );</b></b></tt><b>                       </b>

          <blockquote>Test non-error cases for Local and JCtrl cmds.&nbsp;
 This  tests most aspects of SI ctrlr cmd/response that are expected to complete
   without errors.<br>
           <br>
      Tests all supported cmd types (button, type/status, reset) and random
 unsupported  (i.e. pass through) commands. &nbsp;Tests same cmd types to
all controllers  and different mixes of commands to controlleers. &nbsp;Tests
 all cmd types  with tx size 0 (no xmit).<br>
           <br>
      Uses random DMA buffer addressses and random values for expected values
  setup via backdoor.<br>
           </blockquote>
           <b><tt>&nbsp;<b><br>
      TEST(&nbsp; 1, 0, SiTestInvalidCtrlrCmds&nbsp;&nbsp; ( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
           </b></tt>                             </b>

            <blockquote>Test ctrlr cmds with errors in the cmd fields.<br>
             <br>
      Tests all supported cmd types (button, type/status, reset) and random
 unsupported  (i.e. pass through) commands. &nbsp;Tests all cmd types with
 tx size 0 (no  xmit).<br>
             <br>
      tx_size too big for any cmd (i.e. &gt; 5)<br>
      invalid tx_size for the cmd<br>
      rx_size too big for any cmd (i.e. &gt; 4)<br>
      rx_size 0<br>
      invalid rx_size for the cmd<br>
               <b>    &nbsp;<br>
             </b></blockquote>
   <b>          <tt><b> TEST(&nbsp; 2, 2, SiTestCtrlrErrViaBD&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
  ( levels, CtrlQueryStatus,&nbsp; 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );</b></tt>                                   </b>

              <blockquote>Force errors via joy channel backdoor for controller
  type/status query on all combinations of jc 1, jc 2, and jc 3. &nbsp;A
query   with no errors is done on the local controller.<br>
               <br>
      Test no response from disabled ctrlr<br>
      Test collision err set via backdoor<br>
      Test frame err set via backdoor<br>
               </blockquote>
               <b><br>
               <tt><b>TEST(&nbsp; 3, 1, SiTestCtrlrErrViaBD&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, CtrlReset,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
               </b></tt>                                         </b>

                <blockquote>Force errors via joy channel backdoor for controller
  reset cmd on all combinations of jc 1, jc 2, and jc 3. &nbsp;A cmd with
no  errors is done on the local controller.<br>
                 <br>
       Test no response from disabled ctrlr<br>
       Test collision err set via backdoor<br>
       Test frame err set via backdoor<br>
                 </blockquote>
                 <b><br>
                 <tt><b>TEST(&nbsp; 4, 0, SiTestCtrlrErrViaBD&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, CtrlQueryButtons, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
                 </b></tt>
                  </b>
                  <blockquote>Force errors via joy channel backdoor for controller
  button/xy query on all combinations of jc 1, jc 2, and jc 3. &nbsp;A query
  with no errors is done on the local controller.<br>
                   <br>
       Test no response from disabled ctrlr<br>
       Test collision err set via backdoor<br>
       Test frame err set via backdoor<br>
                   </blockquote>
                   <b><br>
                   <tt><b>TEST(&nbsp; 5, 1, SiTestCtrlrErrViaBD&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, CtrlJcUnsupCmd,&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
                   </b></tt>
        </b>
                    <blockquote>Force errors via joy channel backdoor for
random   unsupported (pass through) controller queries on all combinations
 of jc 1,  jc 2, and jc 3. &nbsp;A query with no errors is done on the local
 controller.<br>
                     <br>
       Test no response from disabled ctrlr<br>
       Test collision err set via backdoor<br>
       Test frame err set via backdoor<br>
                     </blockquote>
                     <b><br>
                     <tt><b>TEST(&nbsp; 6, 1, SiTestCtrlrErrViaBD&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, CtrlNoXmitRand,&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
                     </b></tt>
                </b>
                      <blockquote>Force errors via joy channel backdoor for
 random  controller cmds with tx_size set to 0 query on all combinations
of  jc 1, jc 2, and jc 3. &nbsp;A query with no errors is done on the local
controller.<br>
                       <br>
      Since there should be no cmd transmitted to joy channel controllers
when   tx_size is 0, these tests are expected to behave the same as 'no xmit'
 cmds   without any joy channel controller forced fails.<br>
                       <br>
       Test no response from disabled ctrlr<br>
       Test collision err set via backdoor<br>
       Test frame err set via backdoor<br>
                       </blockquote>
                       <b><br>
                       <tt><b>TEST(&nbsp; 7, 2, SiTestDmaBusyError&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, SI_DMA_WR_REG,&nbsp;&nbsp;&nbsp; </b></tt><tt><b>data_to_write,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
  0) );<br>
                       </b></tt>
                        </b>

                        <blockquote>Test ability to create and clear DMA
busy  errors.<br>
      Write to SI DMA WRITE register while DMA is busy to cause error.<br>
      Uses button queries with random expected values for buttons and x,y.<br>
     The default value written to the register is PIF_RAM_START.<br>
                           <b>    &nbsp;<br>
                         </b></blockquote>
   <b>                      <tt><b>TEST(&nbsp; 8, 1, SiTestDmaBusyError&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, SI_DMA_RD_REG,&nbsp;&nbsp;&nbsp; data_to_write</b></tt><tt><b>
    ,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0) );<br>
                         </b></tt>
                                </b>

                          <blockquote>Test ability to create and clear DMA
busy  errors.<br>
       Write to SI DMA READ register while DMA is busy to cause error.<br>
       Uses button queries with random expected values for buttons and x,y.<br>
     The default value written to the register is PIF_RAM_START.<br>
                             <b>    &nbsp;<br>
                           </b></blockquote>
   <b>                        <tt><b>TEST(&nbsp; 9, 0, SiTestDmaBusyError&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, SI_DRAM_ADDR_REG, data_to_write,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0) );<br>
                           </b></tt>
                                        </b>

                            <blockquote>Test ability to create and clear
DMA  busy errors.<br>
       Write to SI DMA ADDR register while DMA is busy to cause error.<br>
       Uses button queries with random expected values for buttons and x,y.<br>
     The default value written to the register is 0x40.<br>
                               <b>    &nbsp;<br>
                             </b></blockquote>
   <b>                          <tt><b>TEST( 10, 1, SiTestSingleCmdDetection
 ( levels,  &nbsp;sgl_err_bit = 0,&nbsp;&nbsp; &nbsp; 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
                             </b></tt>
                                                </b>

                              <blockquote>Test single cmd indicated by block
 byte = 0<br>
      Try with SI_CONFIG bit 23 set to 0 so single cmd should not be detected
  and the commands should &nbsp;work normally.<br>
                               <br>
      Try with lc, j1, j2, and j3 block byte 0 and with j1, j2, j3 block
byte   0 but lc block byte FF .<br>
                                 <b>    &nbsp;<br>
                               </b></blockquote>
   <b>                            <tt><b>TEST( 11, 0, SiTestSingleCmdDetection
 (  levels, &nbsp;1</b></tt><tt><b>sgl_err_bit = 1,&nbsp;&nbsp; &nbsp; 0,</b></tt><tt><b>
      &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
                               </b></tt>
                                                        </b>

                                <blockquote>Test single cmd indicated by block
 byte = 0<br>
       Try with SI_CONFIG bit 23 set to 1 to cause all 1's to be returned
by  DMA  read.<br>
                                 <br>
      Try with lc, j1, j2, and j3 block byte 0 and with j1, j2, j3 block
byte   0 but lc block byte FF .<br>
                                   <b>    &nbsp;<br>
                                 </b></blockquote>
   <b>                              <tt><b>TEST( 12, 0, SiTestJChannelReset&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
                                 </b></tt>
                                                                </b>

                                  <blockquote>Do a DMA write to SI with button/xy
  querries for all controllers. &nbsp;Start an SI DMA read. &nbsp; While the
  DMA read is busy, set the JCRST bit to cause a reset of all joy channel
controllers.<br>
                                   <br>
      Wait 805 microsec and clear the JCRST.&nbsp; &nbsp;Do an SI DMA read
 and verify   that the controller reset error bit is set for all controllers.<br>
                                   <br>
      Do another button/xy querry to verify that controllers are operating
 normally.<br>
                                     <b>    &nbsp;<br>
                                   </b></blockquote>
   <b>                                <tt><b>TEST( 13, 0, SiTestDmaSpecificAddrs&nbsp;&nbsp;
   ( levels, writes,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
                                   </b></tt>
                                                                        </b>


                                    <blockquote>Test SI DMA writes from buffers
  at interesting addresses.<br>
      This also tests aspects of SI ctrlr cmd/response that are expected
to  complete  without errors.<br>
                                     <br>
      Start write with DMA buffer at non-8byte alligned addr for lsbs 1,2,3,4,5,6,7.
   &nbsp;SI should ignore the lsbs.<br>
                                     <br>
      Do DMA writes with buffers that cross boundaries: 16bytes, 32bytes,
64bytes,   128bytes, 256bytes , 512bytes, 1K, 2K, 4K, 8K, 16K, 32K, 64K, 128K,
256K,   512K, 1M, 2M, 4M<br>
      includes jctrl and lctrl cmds/response check<br>
      &nbsp;&nbsp;&nbsp; walks through bit set for each jctrl/lctrl&nbsp;
button<br>
      &nbsp;&nbsp;&nbsp; random x/y's<br>
      includes random write values to start write/read DMAs<br>
      Before doing DMAs with buffer that crosses megabyte boundary (or 2
megabyte    for 64 bit mode) zero 32 bytes at addr 0 and megabyte boundaries.<br>
                                     <br>
      check crossing bank 0/1 (already done above) and&nbsp; 2/3<br>
      bank 0/1 crossed when bit 6 goes from 0-&gt;1 for address under 1M
(i.e.    starting at 64-8 == 0x00000040 - 8)<br>
      bank 2/3 crossed when bit 6 goes from 0-&gt;1 for address over 1M&nbsp;
  (i.e. starting at 0x00101040 - 16)<br>
                                     <br>
      do x64 mode, bank crossing starting dma buffer at 0x01201080 - 16<br>
                                       <b>    &nbsp;<br>
                                     </b></blockquote>
   <b>                                  <tt><b>TEST( 14, 0, SiTestDmaSpecificAddrs&nbsp;&nbsp;
   ( levels, reads,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
                                     </b></tt>

       </b>

                                      <blockquote>Test SI DMA reads to interesting
  addresses.<br>
       This also tests aspects of SI ctrlr cmd/response that are expected
to  complete  without errors.<br>
                                       <br>
       Start read with DMA buffer at non-8byte alligned addr for lsbs 1,2,3,4,5,6,7.
   &nbsp;SI should ignore the lsbs.<br>
                                       <br>
       Do DMA reads with buffers that cross boundaries: 16bytes, 32bytes,
64bytes,   128bytes, 256bytes , 512bytes, 1K, 2K, 4K, 8K, 16K, 32K, 64K, 128K,
256K,   512K, 1M, 2M, 4M<br>
       includes jctrl and lctrl cmds/response check<br>
       &nbsp;&nbsp;&nbsp; walks through bit set for each jctrl/lctrl&nbsp;
 button<br>
       &nbsp;&nbsp;&nbsp; random x/y's<br>
       includes random write values to start write/read DMAs<br>
       Before doing DMAs with buffer that crosses megabyte boundary (or 2
megabyte    for 64 bit mode) zero 32 bytes at addr 0 and megabyte boundaries.<br>
                                       <br>
       check crossing bank 0/1 (already done above) and&nbsp; 2/3<br>
       bank 0/1 crossed when bit 6 goes from 0-&gt;1 for address under 1M
(i.e.   starting at 64-8 == 0x00000040 - 8)<br>
       bank 2/3 crossed when bit 6 goes from 0-&gt;1 for address over 1M&nbsp;
   (i.e. starting at 0x00101040 - 16)<br>
                                       <br>
       do x64 mode, bank crossing starting dma buffer at 0x01201080 - 16<br>
                                         <b>    &nbsp;<br>
                                       </b></blockquote>
   <b>                                    <tt><b>TEST( 15, 0, SiTestDmaWalkBits&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, writes,&nbsp;&nbsp;&nbsp; walk_ones,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
                                       </b></tt>

               </b>

                                        <blockquote>Walk 1&#8217;s: Test SI DMA
Writes   with starting addresses  defined by the bit sequence below (r stands
for  random).  Do this in separate loops for x36 addresses and x64 addresses.<br>
         &nbsp;<br>
                                         <span style="font-family: &quot;Courier New&quot;; ">
      00000000000000000000000000000000<br>
         00000000000000000000000000001000<br>
         0000000000000000000000000001r000<br>
         000000000000000000000000001rr000<br>
         00000000000000000000000001rrr000<br>
         0000000000000000000000001rrrr000<br>
                                         <span style="mso-spacerun:yes">&nbsp;</span><span style="mso-spacerun:yes">
        &nbsp;&nbsp; </span>:<br>
         0000000001rrrrrrrrrrrrrrrrrrr000<br>
         000000001rrrrrrrrrrrrrrrrrrrr000<br>
         00000001rrrrrrrrrrrrrrrrrrrrr000<br>
         00000010rrrrrrrrrrrrrrrrrrrrr000</span><br>
     &nbsp;<br>
                                         </blockquote>
   <b>                                      <tt><b>TEST( 16, 3, SiTestDmaWalkBits&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, reads,&nbsp;&nbsp;&nbsp;&nbsp; walk_ones,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
                                         </b></tt>

                       </b>

                                          <blockquote>Walk 1&#8217;s: Test SI DMA
 Reads  with starting addresses  defined by the bit sequence below (r stands
 for random). Do this in separate loops for x36 addresses and x64 addresses.<br>
         &nbsp;<br>
                                           <span class="SpellE"></span><span style="font-family: &quot;Courier New&quot;; ">
        00000000000000000000000000000000<br>
         00000000000000000000000000001000<br>
         0000000000000000000000000001r000<br>
         000000000000000000000000001rr000<br>
         00000000000000000000000001rrr000<br>
         0000000000000000000000001rrrr000<br>
                                           <span style="mso-spacerun:yes">
 &nbsp;</span><span style="mso-spacerun:yes">       &nbsp;&nbsp; </span>:<br>
         0000000001rrrrrrrrrrrrrrrrrrr000<br>
         000000001rrrrrrrrrrrrrrrrrrrr000<br>
         00000001rrrrrrrrrrrrrrrrrrrrr000<br>
         00000010rrrrrrrrrrrrrrrrrrrrr000</span><br>
     &nbsp;<br>
                                           </blockquote>
   <b>                                        <tt><b>TEST( 17, 1, SiTestDmaWalkBits&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, writes,&nbsp;&nbsp;&nbsp; walk_zeros,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
                                           </b></tt>

                               </b>

                                            <blockquote>Walk 0&#8217;s: Test SI
DMA  Writes with starting addresses  defined by the bit sequence below (r
stands  for random). Do this in separate loops for x36 addresses and x64
addresses.</blockquote>


                                              <blockquote><span style="font-family: &quot;Courier New&quot;; ">
        00000010111111111111111111100000</span><br>
                                               <span style="font-family: &quot;Courier New&quot;; ">
         000000101111111111111111110rr000</span><br>
                                               <span style="font-family: &quot;Courier New&quot;; ">
         00000010111111111111111110rrr000</span><br>
                                               <span style="font-family: &quot;Courier New&quot;; ">
         0000001011111111111111110rrrr000</span><br>
                                               <span style="font-family: &quot;Courier New&quot;; ">
         000000101111111111111110rrrrr000</span><br>
                                               <span style="font-family: &quot;Courier New&quot;; ">
         00000010111111111111110rrrrrr000</span><br>
                                               <span style="font-family: &quot;Courier New&quot;; "><span style="mso-spacerun:yes">
      &nbsp;</span><span style="mso-spacerun:yes">  &nbsp;&nbsp; </span>:</span><br>
                                               <span style="font-family: &quot;Courier New&quot;; ">
         0000001010rrrrrrrrrrrrrrrrrrr000</span><br>
                                               <span style="font-family: &quot;Courier New&quot;; ">
         000000100rrrrrrrrrrrrrrrrrrrr000</span><br>
                                               <span style="font-family: &quot;Courier New&quot;; ">
         00000010rrrrrrrrrrrrrrrrrrrrr000</span><br>
                                               <span style="font-family: &quot;Courier New&quot;; ">
         0000000rrrrrrrrrrrrrrrrrrrrrr000</span><br>
                                                 <b>    &nbsp;<br>
                                               <span style="font-family: &quot;Courier New&quot;; "><o:p></o:p></span></b></blockquote>
   <b>
                                                                       </b>


                                                <blockquote></blockquote>
   <b>                                              <tt><b>TEST( 18, 1, SiTestDmaWalkBits&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, reads,&nbsp;&nbsp;&nbsp;&nbsp; walk_zeros,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
                                                 </b></tt>

                                                       </b>


                                                  <blockquote>Walk 0&#8217;s: Test
 SI DMA Reads with starting addresses  defined by the bit sequence below
(r  stands  for random). Do this in separate loops for x36 addresses and
x64 addresses.<br>
                                                   <br>
                                                   <span style="font-family: &quot;Courier New&quot;; ">
        00000010111111111111111111100000</span><br>
                                                   <span style="font-family: &quot;Courier New&quot;; ">
         000000101111111111111111110rr000</span><br>
                                                   <span style="font-family: &quot;Courier New&quot;; ">
         00000010111111111111111110rrr000</span><br>
                                                   <span style="font-family: &quot;Courier New&quot;; ">
         0000001011111111111111110rrrr000</span><br>
                                                   <span style="font-family: &quot;Courier New&quot;; ">
         000000101111111111111110rrrrr000</span><br>
                                                   <span style="font-family: &quot;Courier New&quot;; ">
         00000010111111111111110rrrrrr000</span><br>
                                                   <span style="font-family: &quot;Courier New&quot;; "><span style="mso-spacerun:yes">
      &nbsp;</span><span style="mso-spacerun:yes">  &nbsp;&nbsp; </span>:</span><br>
                                                   <span style="font-family: &quot;Courier New&quot;; ">
         0000001010rrrrrrrrrrrrrrrrrrr000</span><br>
                                                   <span style="font-family: &quot;Courier New&quot;; ">
         000000100rrrrrrrrrrrrrrrrrrrr000</span><br>
                                                   <span style="font-family: &quot;Courier New&quot;; ">
         00000010rrrrrrrrrrrrrrrrrrrrr000</span><br>
                                                   <span style="font-family: &quot;Courier New&quot;; ">
         0000000rrrrrrrrrrrrrrrrrrrrrr000</span><br>
     &nbsp;<br>
                                                   <span style="font-family: &quot;Courier New&quot;; "><o:p></o:p></span></blockquote>
   <b>                                                <tt><b>TEST( 19, 1,
SiTestRandom&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   (&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 5, ForceFail_None,&nbsp;&nbsp; StartWithXs,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );</b></tt>

                       </b>

                                                    <blockquote>Do SI DMA
tests  with random values for addresses, expected ctrlr buttons, x, y, type,
and  status.<br>
     no forced failures,&nbsp; write Xs to start regs<br>
     num_random_tests: 5<br>
                                                       <b>    &nbsp;<br>
                                                     </b></blockquote>
   <b>                                                  <tt><b>TEST( 20,
2,  SiTestRandom&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   (&nbsp;&nbsp;&nbsp;&nbsp; 10, ForceFail_None,&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
                                                     </b></tt>

                                                                       </b>


                                                      <blockquote>Do SI DMA
 tests with random values for addresses, expected ctrlr buttons, x, y, type,
 and status.<br>
      no forced failures<br>
      num_random_tests: 10<br>
                                                         <b>    &nbsp;<br>
                                                       </b></blockquote>
   <b>                                                    <tt><b>TEST( 21,
 3, SiTestRandom&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   (&nbsp;&nbsp;&nbsp;&nbsp; 10, ForceFail_Random, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
                                                       </b></tt>


      </b>

                                                        <blockquote>Do SI
DMA  tests with random values for addresses, expected ctrlr buttons, x, y,
type,  and status.<br>
     Use random forced failures for each controller.<br>
      num_random_tests: 10<br>
                                                           <b>    &nbsp;<br>
                                                         </b></blockquote>
   <b>                                                      <tt><b>TEST(
22,  2,  SiTestRandom&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   (&nbsp;&nbsp;&nbsp;&nbsp; 10, ForceFail_None,&nbsp;&nbsp; JChannel_Resp_Rand,
   seed) );<br>
                                                         </b></tt>


              </b>

                                                          <blockquote> Do
SI  DMA tests with random values for addresses, expected ctrlr buttons, x,
y,  type, and status.<br>
      no forced failures, enable response randomization<br>
      num_random_tests: 10<br>
                                                             <b>    &nbsp;<br>
                                                           </b></blockquote>
   <b>                                                        <tt><b>TEST(
 23, 2,  SiTestLCtrlJSRST&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
( levels,   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
                                                           </b></tt>


                      </b>


                                                            <blockquote>
Set  local ctrlr L, R, and START at same time to reset stick reference<br>
     Start with x,y non-zero and verify that after JSRST, x,y goes to zero.<br>
     Verify that button status H[7] (i.e. JSRST) gets set.<br>
                                                               <b>    &nbsp;<br>
                                                             </b></blockquote>
   <b>                                                          <tt><b>TEST(
 24,  1, SiTestLCtrlButRate ( levels, num_tests = default</b></tt><tt><b>
,  random_rates  = false, seed) );</b></tt>


                                                                 </b>


                                                              <blockquote>
   <b>

                                            </b>


                                                                <p>Verify
 for  several rates that local controller buttons values set via the backdoor
 are  seen in DMA button query within 3 button sample periods. &nbsp;With
the backdoor  writes sync'd to the sample &nbsp;times so the writes are just
after a sample  time, verify that the expected values do not show earlier
than 25 &nbsp;us  before 3 button sample periods and do show up no more than
25 us after 3 sample periods.</p>


                                                                <p>Use sample
 rates with but_rate 1, 2 (i.e the default), and 10. &nbsp;The but_rate 0
case is special because it is so fast that we expect the change to be seen
 with no need for any explicit wait time.</p>


                                                                <p>Other
rates  can be specified in the default rates array or by function argument.
&nbsp;Slower  rates require a long time to perform the test.<br>
                                                               </p>


                                                                <p>Sync with
 button samples by disable button samples, set button rate, enable button
 samples. &nbsp;Then, for each test at this rate, set button value via backdoor,
 read&nbsp; at 100 us before 3 button sample periods and keep reading as
fast  as possible until&nbsp; the change is seen. &nbsp; Since the writes
are sync'd  to happen just after a button sample, the change should be seen
close to 3 button periods after the write.</p>


                                                                <p>Do 2 tests
 per but_rate or as specified by argument.<br>
                                                               </p>
                                                               </blockquote>
                                                               <b><tt><b><br>
     TEST( 25, 1, SiTestLCtrlJsxy&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   ( levels, LCTRL_SOMEJITTER, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
                                                               </b></tt>


                                      </b>


                                                                <blockquote>
   <b>

                                                    </b>


                                                                  <p>Test
 local  controller X,Y movement</p>


                                                                  <p> &nbsp;For
 (+x, -y), (+x, +y), (-x, -y), and (-x, +y)&nbsp; counts:</p>


                                                                  <blockquote>
    cmd via bd to move part way to limit,<br>
     &nbsp;&nbsp;&nbsp;&nbsp; do button request until dest reached<br>
     &nbsp;&nbsp;&nbsp;&nbsp; and no movement verified after reached<br>
     cmd via bd to move past the limit,<br>
     &nbsp;&nbsp;&nbsp;&nbsp; do button request until dest reached<br>
     &nbsp;&nbsp;&nbsp;&nbsp; and no movement verified after reached<br>
     cmd via bd to move part way away from limit<br>
     &nbsp;&nbsp;&nbsp;&nbsp; do button request until dest reached<br>
     &nbsp;&nbsp;&nbsp;&nbsp; and no movement verified after reached</blockquote>


                                                                    <p>  Use
 jitter mask 0xFF during the tests to give jitter up to 256 ns added to pulse
 timing values.</p>


                                                                    <p> When
 checking local controller X,Y movement during any test, verifies that the
 expected X,Y is reached within the expected max time and that the position
  doesn't change after reaching the expected position until the next backdoor
  X,Y move commands are issued. &nbsp;During movement, each X,Y sample is
checked  to see that it is moving closer to the target values. &nbsp; Once
an X,Y movement  is started during a test, no new X,Y movement backdoor cmds
will be issued  until the previous movement has been completely verified
or a reset has been  performed. &nbsp;When resets are commanded, it is verified
 that X,Y goes to and stays at 0.<br>
                                                                   <b><br>
                                                                   </b></p>
   <b>                                                                </b></blockquote>
   <b>                                                                <tt><b>
  TEST(   26, 2, SiTestRandom&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   (&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1, ForceFail_ClearSiIntMask, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) );<br>
                                                                   </b></tt>


                                                      </b>


                                                                    <blockquote>
      Test that when the SI interrupt mask bit is not set in the MI_INTR_MASK_REG,
  the interrupt does not show up in the lsb of int_l.<br>
                                                                     <br>
     All other DMA tests verify that the int does appear if the SI interrupt
  mask bit is set.<br>
                                                                     <br>
      num_random_tests: 1<br>
                                                                       <b>
     &nbsp;<br>
                                                                     </b></blockquote>
   <b>                                                                  <b><tt>
   TEST(  27, 2, SiTestLCtrlButDeglitch&nbsp;&nbsp; ( levels, </tt></b><tt><b>
   button_rate  = 1</b></tt><b><tt>,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; seed) );<br>
                                                                     </tt></b>


                                                             </b>


                                                                      <blockquote>
   <b>

                                                                        </b>


                                                                        <p>
    Test local controller button sample deglitching.</p>


                                                                        <p>
     Set buttons to 0<br>
      Set button rate to 1 or as specifed by argument<br>
      Use default jc_div = 31, tXfer = tHigh = tLow = 2000, jitter = 0<br>
     Set buttons on via bd for 1.25 sample period, verify no change in button
  state<br>
      Set buttons off via bd, verify no change in button state<br>
      Verify buttons don't show up in dma button query within the max time
 they  would have shown up if we didn't turn them off.<br>
      Set buttons on for 2.25 sample period, verify they don't show as on<br>
      set buttons off, verify they don't show as on<br>
      Verify buttons don't show up in dma button query within the max time
 they  would have shown up if we didn't turn them off.
                                                 </p>
                                                                   </blockquote>
                                                                        <br>
                                                                        <b><b><tt>
      TEST( 28, 2,&nbsp;SiTestLCtrlJsxyDeglitch</tt><tt>&nbsp; ( levels,
0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) )<b><b><tt>;<br>
                                                                        </tt></b></b></tt></b></b>
                                                                        <blockquote>
                                                                          <p>
    Test local controller X,Y sample deglitching.</p>
                                                                          </blockquote>


                                                                          <blockquote>
      Set x,y to 0<br>
     Use default jc_div = 31, tXfer = tHigh = tLow = 2000,<br>
     &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; jitter
  = 0<br>
     Cause xglitch=0x01 via backdoor, verify no change in x,y state<br>
     Cause xglitch=0x10 via backdoor, verify no change in x,y state<br>
     Cause yglitch=0x01 via backdoor, verify no change in x,y state<br>
     Cause yglitch=0x10 via backdoor, verify no change in x,y state</blockquote>
                                                                            <b><b><tt><br>
TEST( 30, 2,&nbsp;SiTestBugFixes</tt><tt>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) )<b><b><tt>;<br>
                                                                            </tt></b></b></tt></b></b>
                                                                            <blockquote>
                                                                              <p>
    This test is for testing specific miscellaneous bug fixes.&nbsp; It can
be used to test fixes for bugs that show up for random values that may or
may not occur in other tests.</p>
                                                                              </blockquote>


                                                                              <blockquote>
 It currently tests the fix for bug bug 1481 - SI lctrl error bits anomaly
for unsupported cmd with invalid tx size<br>

    </blockquote>

   <br>

    <b><b><tt>      TEST( 31, 2,&nbsp;SiTest</tt><tt>Slave&nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; &nbsp;( levels, 0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   0,&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
   seed) )<b><b><tt><b><b><tt>;<br>
                                                                                </tt></b></b></tt></b></b></tt></b></b>
                                                                                <blockquote>
                                                                                  <p>
    Using Bill's master model, in slave mode setup  jctrl  1 to receive cmds
from the master. &nbsp;Request the master model to send  each of the valid
cmds (0,1,255), &nbsp;get the response from the local controller,  prepare
and transmit the response to the master, retrieve and verify the data received
by the master. &nbsp;Test getting the lctrl response in a separate  DMA after
receiving the cmd from the master. &nbsp;Test getting the lctrl  response
for button/joystick x,y in the same DMA in which the master cmd is received.</p>
                                                                                  <p>
While doing slave mode transactions verify expected  behavior of all assoiated
register bits and interrupts. This includes at least, SI_CONFIG JC_SLAVE,
&nbsp;SI_CTRL XMIT, BUSY, REQ, SI_STATUS bits assoiated with DMA's used during
slave mode transactions, and interrupt indications.</p>
                                                                                  </blockquote>
                                                                                  <blockquote>
                                                                                    <p>
Test Joy Channel resets commanded by master while in slave  mode. <br>

    </p>
                                                                                    </blockquote>


                                                                                    <blockquote>
                                                                                      <ol>

      <li> with rcv active (before cmd rqstd) start a reset, after reset
should  have completed, check, should get reset error bit set (plus maybe
no response)</li>

      <li> with rcv active (before cmd rqstd) start a reset, after it should
 have completed, rqst cmd and check, should get reset error bit set (plus
maybe no response</li>

      <li> with rcv active (before cmd rqstd) start a reset, during reset,
check,  should get reset error bit set (plus maybe no response)</li>

      <li> before start cmd receive start a reset, start rcv during reset,
check,  should get reset error bit set</li>

      <li> reset during reception of a cmd from the master, (use Franks backdoor
 reset for this one</li>


                                                                                      </ol>
Using Frank's master model:
                                 </blockquote>
                                                                                      <blockquote>
                                                                                        <ol>

      <li> Use the backdoor rsp_random setting to test randomly stretched
bit  pulses within the spec limits.</li>

      <li> Use the backdoor to generate bit timing violations to test the
frame  error detection. Verify that the frame error bit gets set.</li>

      <li> Use the backdoor to disable the master model during a command
transmition  to the slave to test truncated commands. &nbsp;Verify that truncated
commands  cause a no response error and&nbsp; that a good command can be
received after  64us.</li>

      <li> Use the backdoor to force a collision during trasnmission of the
slave  response to the master. &nbsp;Verify that the collision error is indicated
 in the error bits.</li>

      <li> Verify that the SI can receive random commands in the range 4
to 254  with the number of bytes received indicated by bits [2:0] of the
cmd.<br>

      </li>


                                                                                        </ol>

    </blockquote>
                                                                                        <blockquote><b><br>

      </b></blockquote>

      <br>

      <b>
         <br>

                                                                                          <br>

                                                                                          <br>


                                                                                          </b>


                                                                                          <p><b><br>

                                                                                          </b></p>
   <b>


   </b>


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